CN113972265B - Method for improving LDMOS (laterally diffused metal oxide semiconductor) manufacturing process with field plate - Google Patents
Method for improving LDMOS (laterally diffused metal oxide semiconductor) manufacturing process with field plate Download PDFInfo
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- CN113972265B CN113972265B CN202010718128.7A CN202010718128A CN113972265B CN 113972265 B CN113972265 B CN 113972265B CN 202010718128 A CN202010718128 A CN 202010718128A CN 113972265 B CN113972265 B CN 113972265B
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- field plate
- oxide layer
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 4
- 150000004706 metal oxides Chemical class 0.000 title abstract description 4
- 239000004065 semiconductor Substances 0.000 title abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000002035 prolonged effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a method for improving an LDMOS (laterally diffused metal oxide semiconductor) manufacturing process with a field plate, which comprises the following steps: providing a substrate and forming a gate on the substrate; depositing a first oxide layer on the gate electrode; depositing a field plate on the first oxide layer; depositing a second oxide layer on the field plate; covering the second oxide layer with photoresist, developing, and etching the second oxide layer; etching the field plate; and forming the LDMOS with the field plate. By the method for improving the LDMOS manufacturing process with the field plate, the problem that the step height of the field plate is too large is solved by redeposition or adding the oxide layer after the field plate is deposited, and the added oxide layer can be used as a hard mask to protect the area of the field plate which needs to be left, so that the etching time can be prolonged to ensure that no residues exist.
Description
Technical Field
The present invention relates to an improvement of an LDMOS process, and more particularly, to a method of improving an LDMOS process with a field plate.
Background
At present, different from the conventional LDMOS, the source-drain region electric field when a channel is opened can be reduced by matching a field plate technology in the LDMOS process requirement, so that the breakdown voltage is improved. In the conventional process of manufacturing the LDMOS with a field plate, an oxide layer is usually deposited as an isolation layer after the gate is defined, then the field plate is deposited, and then the field plate is directly etched after photoresist development to obtain the LDMOS with a field plate.
Referring to fig. 1, fig. 1 illustrates the prior art situation in more detail: fig. 1 shows a schematic outline of an LDMOS with a field plate prepared by a conventional process, as shown in the drawing, after etching the field plate 4, a residual field plate 5 remains between two gates 2, which is not etched cleanly, and defects shown by the residual field plate 5 are generated, mainly, after the oxide layer 3 is deposited, a deep recess is generated, and the recess is generated in the subsequent photoresist applying and developing process, because the recess is deep and narrow, the photoresist is not easy to remove in the photoresist developing process, so that photoresist residues may exist, and the residual photoresist becomes a mask (mask) in the subsequent etching process, and the underlying field plate/oxide layer/gate is not etched in the subsequent etching process, so that the residual photoresist becomes defects.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a method for improving the LDMOS manufacturing process with a field plate, which is characterized in that an oxide layer is deposited on the field plate after the field plate is deposited to improve the problem that the step height of the field plate is too large, then a photoresist is covered on the oxide layer and developed for a required area, then the oxide layer deposited on the field plate is etched, and then the field plate is etched, so that the field plate is etched completely, and no field plate residue between grid electrodes is realized.
In order to solve the technical problems, the invention adopts the following technical scheme:
according to an aspect of the present invention, there is provided a method for improving an LDMOS process with a field plate, the method comprising the steps of:
(1) Providing a substrate and forming a gate on the substrate;
(2) Depositing a first oxide layer on the gate electrode;
(3) Depositing a field plate on the first oxide layer;
(4) Depositing a second oxide layer on the field plate;
(5) Covering the second oxide layer with photoresist, developing, and etching the second oxide layer;
(6) Etching the field plate;
(7) And forming the LDMOS with the field plate.
In one embodiment of the invention, the substrate in step (1) is made of silicon, germanium or silicon carbide material.
In one embodiment of the present invention, the gate formed in step (1) is a polysilicon gate (poly gate), wherein the gate comprises a gate polysilicon layer and a gate silicon oxide layer below the gate polysilicon layer.
In one embodiment of the invention, the number of gates is two or more, and the gates therein are spaced apart on the substrate.
In one embodiment of the present invention, the first oxide layer in step (2) has a thickness of
In one embodiment of the present invention, the field plate in step (3) is made of polysilicon (poly).
In one embodiment of the present invention, the second oxide layer in step (4) has a thickness of
In one embodiment of the invention, the second oxide layer has a thickness of
In one embodiment of the present invention, a step of removing the photoresist is further included between the step (6) and the step (7).
According to another aspect of the present invention, there is provided a field plate LDMOS fabricated using the improved field plate LDMOS fabrication method as described above.
By adopting the technical scheme, compared with the prior art, the invention has the following advantages:
in the method for improving the LDMOS manufacturing process with the field plate, the problem that the step height of the field plate is too large is solved by redepositing or adding an oxide layer on the field plate after the field plate is deposited, and the added oxide layer can be used as a hard mask to protect the area of the field plate which needs to be left, so that the etching time can be prolonged to ensure that no residues exist.
Drawings
The foregoing and/or additional aspects and advantages of the invention will be more readily apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, wherein:
fig. 1 shows a schematic outline of an LDMOS with a field plate prepared by a conventional process;
FIG. 2 is a schematic diagram of an LDMOS with a field plate to meet the process requirements in the present invention;
FIG. 3 is a flow chart of a method for improving the LDMOS process with field plate according to the present invention;
fig. 4 is a schematic diagram of an improved LDMOS process with field plates according to the present invention.
Description of the reference numerals
1 substrate, 2 grid electrode, 3 first oxide layer, 4 field plate, 5 residual field plate, 6 second oxide layer and 7 photoresistance
Detailed Description
It should be understood that the embodiments of the invention shown in the exemplary embodiments are only illustrative. Although only a few embodiments have been described in detail in this disclosure, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the teachings of the subject matter of this disclosure. Accordingly, all such modifications are intended to be included within the scope of present invention. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and parameters of the exemplary embodiments without departing from the spirit of the present inventions.
The invention provides a method for improving an LDMOS (laterally diffused metal oxide semiconductor) manufacturing process with a field plate, which comprises the following steps: providing a substrate and forming a gate on the substrate; depositing a first oxide layer on the gate electrode; depositing a field plate on the first oxide layer; depositing a second oxide layer on the field plate; covering the second oxide layer with photoresist, developing, and etching the second oxide layer; etching the field plate; and forming the LDMOS with the field plate.
In the above preparation method, the substrate is made of silicon, germanium or silicon carbide material.
In the above manufacturing method, the gate electrode is formed as a polysilicon gate electrode, wherein the gate electrode includes a gate polysilicon layer and a gate silicon oxide layer under the gate polysilicon layer.
In the above manufacturing method, the number of the gate electrodes is two or more, and the gate electrodes therein are distributed on the substrate at intervals.
In the above preparation method, the first oxide layer has a thickness of
In the above manufacturing method, the field plate is made of polysilicon.
In the above preparation method, the thickness of the second oxide layer is
Preferably the thickness of the second oxide layer is +.>
In the above preparation method, the method further comprises a step of removing the photoresist.
In addition, the invention also provides the LDMOS with the field plate, which is prepared by adopting the method for improving the LDMOS manufacturing process of the field plate.
The technical scheme of the present invention will be described in detail with reference to fig. 2 to 4.
Referring to fig. 2, fig. 2 is a schematic outline diagram of an LDMOS with a field plate, which meets the requirements of a manufacturing process in the present invention, that is, the LDMOS with a field plate manufactured by the improved process/method of the present invention, compared with the LDMOS with a field plate manufactured by the existing manufacturing process of fig. 1, the LDMOS with a field plate manufactured by the improved method of the present invention has no field plate residue between the gates 2, that is, no residual field plate 5 between the gates 2 in fig. 1.
Referring to fig. 3-4, fig. 3 and 4 are a flow chart and a schematic diagram, respectively, of a method for improving the LDMOS process with field plates according to the present invention. The method 300 of the invention starts in block 301, in which a substrate 1 is provided and a gate 2 is formed on the substrate 1, then proceeds to block 302, in which a step of depositing a first oxide layer 3 on the gate 2 is performed, then proceeds to block 303, where the deposition of a field plate 4 on the first oxide layer 3 is completed, the method 300 proceeds to block 304, where a second oxide layer 6 is deposited on the field plate 4, then proceeds to block 305, where a photoresist 7 is covered on the second oxide layer 6 and developed, where the second oxide layer 6 is etched, then proceeds to block 306, where the field plate 4 is etched, finally proceeds to block 307, where the field plate LDMOS meeting the requirements is obtained after removal of the photoresist 7.
The invention improves on the basis of the existing LDMOS manufacturing process, and the invention deposits an oxide layer on the field plate after the field plate is deposited to improve the problem that the step height of the field plate is too large, then covers a photoresistance on the oxide layer and develops the photoresistance aiming at a required area, then etches the oxide layer deposited again on the field plate, and then etches the field plate. In the improved process or method, the invention improves the problem of too large a step height of the field plate by redepositing or adding an oxide layer on the field plate after the field plate is deposited, and the added oxide layer can be used as a hard mask to protect the area of the field plate which needs to be left, so that the etching time can be prolonged to ensure that no residue exists.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention; modifications and equivalent substitutions are intended to be included in the scope of the claims without departing from the spirit and scope of the present invention.
Claims (10)
1. The method for improving the LDMOS manufacturing process with the field plate is characterized by comprising the following steps of:
(1) Providing a substrate and forming two gates on the substrate;
(2) Depositing a first oxide layer on the gate;
(3) Depositing a field plate on the first oxide layer;
(4) Depositing a second oxide layer on the field plate;
(5) Covering a photoresist on the second oxide layer, developing, and etching the second oxide layer to completely etch the second oxide layer between the two gates;
(6) Etching the field plate so that the field plate between two gates is entirely etched away;
(7) And forming the LDMOS with the field plate.
2. The method of claim 1, wherein the substrate in step (1) is made of silicon, germanium or silicon carbide material.
3. The method of claim 1, wherein the gate formed in step (1) is a polysilicon gate, wherein the gate comprises a gate polysilicon layer and a gate silicon oxide layer below the gate polysilicon layer.
4. The method of claim 1, wherein two of the gates are spaced apart on the substrate.
5. The method of claim 1, wherein the thickness of the first oxide layer in step (2) is
6. The method of claim 1, wherein the field plate in step (3) is made of polysilicon.
7. The method of claim 1, wherein the second oxide layer in step (4) has a thickness of
8. The method of claim 7, wherein the second oxide layer has a thickness of
9. The method of claim 1, further comprising a step of removing photoresist between the step (6) and the step (7).
10. An LDMOS with field plate manufactured by the method of improving the process of manufacturing an LDMOS with field plate according to any of the claims 1-9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010718128.7A CN113972265B (en) | 2020-07-23 | 2020-07-23 | Method for improving LDMOS (laterally diffused metal oxide semiconductor) manufacturing process with field plate |
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| CN202010718128.7A CN113972265B (en) | 2020-07-23 | 2020-07-23 | Method for improving LDMOS (laterally diffused metal oxide semiconductor) manufacturing process with field plate |
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| CN113972265A CN113972265A (en) | 2022-01-25 |
| CN113972265B true CN113972265B (en) | 2023-07-04 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777497A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Production method of power MOS field-effect tube |
| CN106206310A (en) * | 2015-05-07 | 2016-12-07 | 北大方正集团有限公司 | The manufacture method of rf-ldmos semiconductor device |
| CN111063737A (en) * | 2019-11-25 | 2020-04-24 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3831602B2 (en) * | 2000-12-07 | 2006-10-11 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| US9012988B2 (en) * | 2013-08-15 | 2015-04-21 | Vanguard International Semiconductor Corporation | Semiconductor device with a step gate dielectric structure |
| CN105374686A (en) * | 2014-09-02 | 2016-03-02 | 无锡华润上华半导体有限公司 | Method for manufacturing LDMOS device |
| US9590053B2 (en) * | 2014-11-25 | 2017-03-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methodology and structure for field plate design |
| CN110310892A (en) * | 2018-03-20 | 2019-10-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN110838524B (en) * | 2018-08-16 | 2023-07-07 | 中芯国际集成电路制造(上海)有限公司 | LDMOS device and forming method thereof |
| CN111200006B (en) * | 2018-11-19 | 2021-12-21 | 无锡华润上华科技有限公司 | Lateral double-diffusion metal oxide semiconductor field effect transistor and preparation method thereof |
| CN111092123A (en) * | 2019-12-10 | 2020-05-01 | 杰华特微电子（杭州）有限公司 | Lateral double-diffused transistor and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777497A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Production method of power MOS field-effect tube |
| CN106206310A (en) * | 2015-05-07 | 2016-12-07 | 北大方正集团有限公司 | The manufacture method of rf-ldmos semiconductor device |
| CN111063737A (en) * | 2019-11-25 | 2020-04-24 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
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