TWI838718B - Trench power semiconductor device and manufactureing method thereof - Google Patents

Abstract

A trench power semiconductor device and a manufacturing method thereof are provided. The trench power semiconductor device includes a semiconductor substrate, a shield gate, an oxidation layer, a gate layer and a gate oxide layer. The shield gate is disposed in a first trench of the semiconductor substrate and includes a first shield portion and a second shield portion disposed on the first shield portion. A width of the second shield portion is larger than a width of the first shield portion. The oxidation layer is disposed between the shield gate and the semiconductor substrate, and includes a first oxidation portion surrounding the first shield portion and a second oxidation portion surrounding the second shield portion. A thickness of the first oxidation portion is larger than a thickness of the second oxidation portion. The gate layer is disposed in the first trench and located on the shield gate. The gate oxide layer includes a first gate oxide portion disposed between the gate layer and the second shield portion, and a second gate oxide portion disposed between the gate layer and the semiconductor substrate. A thickness of the second gate oxide portion is smaller than the thickness of the second oxidation portion.

Description

Trench type power semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a trench power semiconductor device and a manufacturing method thereof.

Trench power semiconductor devices such as trench split-gate power metal oxide semiconductor field effect transistors (split-gate MOSFETs) have the characteristics of high breakdown voltage and low on-resistance, and are suitable as medium and low voltage high power components.

However, the current process of manufacturing trench-type separated-gate power MOSFETs is deep in the trench, so during the process of depositing the shielding gate, a seam is easily formed in the shielding gate, and a sharp recess is generated on the surface of the shielding gate after etching back, resulting in the gate formed on the shielding gate also having corresponding sharp corners, which is easy to cause the problem of tip discharge, thereby affecting the performance of the trench power semiconductor device.

The present invention provides a trench power semiconductor device that can improve the problem of tip discharge at the gate and enhance the reliability of the trench power semiconductor device.

The present invention also provides a method for manufacturing a trench power semiconductor device, which can prevent the formation of gaps in the shielding gate or prevent the gaps from approaching the shielding gate surface, so as to avoid the generation of sharp recesses on the shielding gate surface, thereby improving the problem of tip discharge and improving the reliability of the trench power semiconductor device.

The trench power semiconductor device of the present invention includes a semiconductor substrate, a shielding gate, an oxide layer, a gate layer and a gate oxide layer. The semiconductor substrate has a first trench, and the shielding gate is arranged in the first trench. The shielding gate includes a first shielding portion and a second shielding portion, the second shielding portion is located on the first shielding portion, and the width of the second shielding portion is greater than the width of the first shielding portion. The oxide layer is arranged between the shielding gate and the semiconductor substrate. The oxide layer includes a first oxide portion and a second oxide portion, the first oxide portion surrounds the first shielding portion, the second oxide portion surrounds the second shielding portion, and the thickness of the first oxide portion is greater than the thickness of the second oxide portion. The gate layer is arranged in the first trench and is located on the shielding gate. The gate oxide layer includes a first gate oxide portion and a second gate oxide portion. The first gate oxide portion is disposed between the gate layer and the second shielding portion that shields the gate, and the second gate oxide portion is disposed between the gate layer and the semiconductor substrate. The thickness of the second gate oxide portion is less than the thickness of the second oxide portion.

In one embodiment of the present invention, the ratio of the thickness of the first oxidized portion to the thickness of the second oxidized portion is greater than 7/6.

In one embodiment of the present invention, the thickness of the first gate oxide portion is greater than the thickness of the second gate oxide portion.

In one embodiment of the present invention, the height of the first oxidation portion is 3±0.6μm, the height of the second oxidation portion is 1.5±0.3μm, and the height of the second gate oxidation portion is 1.5±0.3μm.

In one embodiment of the present invention, the semiconductor substrate includes a cell region and a terminal region, the first trench is disposed in the cell region, and the semiconductor substrate further includes a second trench in the terminal region.

In one embodiment of the present invention, the trench power semiconductor device further includes at least one guard ring and a terminal oxide layer. At least one guard ring is disposed in the second trench. The guard ring may include a first guard ring portion and a second guard ring portion, the second guard ring portion is located on the first guard ring portion, and the width of the second guard ring portion is greater than the width of the first guard ring portion. The terminal oxide layer is located between the guard ring and the semiconductor substrate, the terminal oxide layer includes a first terminal oxide portion and a second terminal oxide portion, the first terminal oxide portion surrounds the first guard ring portion, the second terminal oxide portion surrounds the second guard ring portion, and the thickness of the second terminal oxide portion is less than the thickness of the first terminal oxide portion.

The manufacturing method of the trench power semiconductor device of the present invention includes the following steps. A semiconductor substrate is provided, and a first trench is formed in the semiconductor substrate. Then, a first oxidized portion is formed at the bottom and part of the sidewall of the first trench, and a second oxidized portion is formed on the sidewall of the first trench not covered by the first oxidized portion, wherein the thickness of the first oxidized portion is greater than the thickness of the second oxidized portion. Then, a shielding gate is formed in the first trench, and a part of the second oxidized portion is exposed, and then the exposed second oxidized portion is removed to expose part of the sidewall of the first trench. A gate oxide layer is formed on the surface of the shielding gate and the exposed sidewall of the first trench, wherein the thickness of the gate oxide layer is less than the thickness of the second oxidized portion. Then, a gate electrode layer is formed on the gate oxide layer in the first trench.

In another embodiment of the present invention, the semiconductor substrate includes a cell region and a terminal region, the first trench is formed in the cell region, and the step of forming the first trench includes simultaneously forming a second trench in the terminal region of the semiconductor substrate.

In another embodiment of the present invention, the step of forming the first oxidation portion includes simultaneously forming the first terminal oxidation portion at the bottom and part of the sidewall of the second trench.

In another embodiment of the present invention, the step of forming the second oxide portion includes simultaneously forming the second terminal oxide portion on the sidewall of the second trench not covered by the first terminal oxide portion.

In another embodiment of the present invention, the step of forming the shielding gate includes depositing a polysilicon material layer in the first trench and the second trench, wherein the polysilicon material layer in the second trench serves as a protective ring. Then, a patterned photoresist layer is formed on the second trench to cover the protective ring in the second trench, and the polysilicon material layer in the cell area is etched using the patterned photoresist layer as a mask to form a shielding gate in the cell area.

In another embodiment of the present invention, the step of forming the first trench in the semiconductor substrate includes: forming a patterned hard mask layer on the surface of the semiconductor substrate, using the patterned hard mask layer as a mask, etching the exposed semiconductor substrate to form a shallow trench. Then forming a thin oxide layer on the sidewall and bottom of the shallow trench, forming a silicon nitride spacer on the thin oxide layer on the sidewall of the shallow trench. Using the silicon nitride spacer as a mask, etching away the thin oxide layer on the bottom of the shallow trench, and then using the patterned hard mask layer and the silicon nitride spacer as masks, etching the semiconductor substrate exposed at the bottom of the shallow trench to form the first trench.

In another embodiment of the present invention, the step of forming the first oxidized portion includes performing a first oxidation reaction to form the first oxidized portion on the sidewalls and bottom of the first trench outside the silicon nitride spacer.

In another embodiment of the present invention, the step of forming the second oxidized portion includes removing the thin oxide layer, the patterned hard mask layer and the silicon nitride spacer to expose part of the sidewall of the first trench, and then performing a second oxidation reaction to form the second oxidized portion.

Based on the above, the oxide layer formed on the trench sidewall of the trench power semiconductor device of the present invention has the characteristics of being thin at the top and thick at the bottom, so the shielding gate formed therein has a structure of being wide at the top and narrow at the bottom, thereby preventing the generation of gaps when the shielding gate is formed by deposition. Even if a gap is formed in the shielding gate, due to the structural characteristics of the oxide layer, there will only be a gap at the bottom of the shielding gate, and no sharp recess will be generated on the surface of the shielding gate, thereby improving the problem of discharge at the gate tip, increasing the breakdown voltage of the trench power semiconductor device, and improving reliability.

In order to make the above features and advantages of the present invention more clearly understood, the following is a detailed description of the embodiments with the accompanying drawings.

10, 20: Trench power semiconductor device

100, 200: semiconductor substrate

100s, 200s: surface

110, 262: shielding gate

110’, 264: Protective ring

112: First shielding part

112’: First protection ring section

114: Second shielding part

114’: Second protection ring section

120: Oxide layer

120’: terminal oxide layer

122, 242: First oxidation part

122', 244: first terminal oxidation part

124, 252: Second oxidation part

124', 254: second terminal oxidation part

130, 280: Gate layer

140, 270: Gate oxide layer

142, 272: First gate oxidation part

144, 274: Second gate oxidation part

210: Patterned hard cover layer

220: Thin oxide layer

230: Silicon nitride material layer

230a: Silicon nitride spacer

h1, h2, h3, h1’, h2’: height

PR: Patterned photoresist layer

R1: Unit area

R2: Terminal area

S: Gap

t1, t2, t3, t4, t5, t6, t7, t8, t1’, t2’, t3’, t4’: thickness

T, T’: shallow groove

T1: First groove

T2: Second groove

w1, w2, w1’, w2’: width

Figure 1 is a schematic cross-sectional view of a trench power semiconductor device according to an embodiment of the present invention.

Figures 2A to 2H are cross-sectional schematic diagrams of a manufacturing process of a trench power semiconductor device according to another embodiment of the present invention.

The following examples are listed and described in detail with the attached drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn in original size. For ease of understanding, the same components in the following description will be indicated by the same symbols.

In addition, the terms "include", "including", "have", etc. used in this article are all open terms, which means "including but not limited to".

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer", or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

In addition, the directional terms mentioned in the text, such as "upper", "lower", etc., are only used to refer to the directions of the drawings and are not used to limit the present invention.

Figure 1 is a schematic cross-sectional view of a trench power semiconductor device according to an embodiment of the present invention.

1 , the trench power semiconductor device 10 includes a semiconductor substrate 100, a shielding gate 110, an oxide layer 120, a gate layer 130, and a gate oxide layer 140. The semiconductor substrate 100 has a first trench T1. The shielding gate 110 is disposed in the first trench T1, and the shielding gate 110 includes a first shielding portion 112 and a second shielding portion 114. The second shielding portion 114 is located on the first shielding portion 112, and the width w2 of the second shielding portion 114 is greater than the width w1 of the first shielding portion 112. The oxide layer 120 is disposed between the shielding gate 110 and the semiconductor substrate 100, and the oxide layer 120 includes a first oxide portion 122 and a second oxide portion 124. The first oxidized portion 122 surrounds the first shielding portion 112, the second oxidized portion 124 surrounds the second shielding portion 114, and the thickness t1 of the first oxidized portion 122 is greater than the thickness t2 of the second oxidized portion 124. In the first embodiment, there may be a gap S inside the shielding gate 110, which is formed in the first shielding portion 112 and the lower part of the second shielding portion 114. However, the existence of the gap S does not affect the interface profile between the gate layer 130 and the shielding gate 110; that is, no sharp recess will be generated on the surface of the shielding gate 110. In a preferred embodiment, there is no gap S inside the shielding gate 110, or the gap S is only formed in the first shielding portion 112.

In one embodiment, the ratio of the thickness t1 of the first oxidized portion 122 to the thickness t2 of the second oxidized portion 124 may be greater than 7/6, for example, between 7/6 and 4/3. If the ratio of the thickness t1 of the first oxidized portion 122 to the thickness t2 of the second oxidized portion 124 is greater than 7/6, it can ensure that the upper edge of the gap is maintained near the junction of the first oxidized portion 122 and the second oxidized portion 124; if the ratio of the thickness t1 of the first oxidized portion 122 to the thickness t2 of the second oxidized portion 124 is less than 4/3, it can avoid that the width of the first trench T1 within the height h1 of the first oxidized portion 122 is too wide, which in turn limits the micro-reduction range of the first trench T1 spacing.

Please continue to refer to FIG. 1 . The gate layer 130 is disposed in the first trench T1 and is located on the shielding gate 110. The gate oxide layer 140 includes a first gate oxide portion 142 and a second gate oxide portion 144. The first gate oxide portion 142 is disposed between the gate layer 130 and the second shielding portion 114 of the shielding gate 110, and the second gate oxide portion 144 is disposed between the gate layer 130 and the semiconductor substrate 100, wherein the second gate oxide portion 144 may extend from the sidewall of the first trench T1 to the surface 100s of the semiconductor substrate 100, but the present invention is not limited thereto; in another embodiment, the second gate oxide portion 144 may be formed only on the sidewall of the first trench T1. In the first embodiment, the thickness t4 of the second gate oxide portion 144 is less than the thickness t2 of the second oxide portion 124, so that the shielding gate 110 and the semiconductor substrate 100 have a sufficiently low drain-source capacitance. The ratio of the thickness t2 of the second oxide portion 124 to the thickness t4 of the second gate oxide portion 144 can be adjusted according to actual needs, and the present invention is not limited thereto. The gate oxide layer 140 can be formed by a furnace oxidation method, and because the material of the semiconductor substrate 100 is usually silicon and the material of the shielding gate 110 is usually polysilicon, the oxidation rates of the two are different, resulting in the thickness t3 of the first gate oxide portion 142 being different from the thickness t4 of the second gate oxide portion 144, and the thickness t3 of the first gate oxide portion 142 is usually greater than the thickness t4 of the second gate oxide portion 144. However, the material of the semiconductor substrate 100 and the material of the shielding gate 110 are not limited to the above, and other materials known in the semiconductor field may also be used.

In one embodiment, the ratio of the thickness t3 of the first gate oxide portion 142 to the thickness t4 of the second gate oxide portion 144 may be between 3/1 and 4/1. If the ratio of the thickness t3 of the first gate oxide portion 142 to the thickness t4 of the second gate oxide portion 144 is greater than 3/1, it can be ensured that there is sufficient withstand voltage between the shielding gate 110 and the gate layer 130; if the ratio of the thickness t3 of the first gate oxide portion 142 to the thickness t4 of the second gate oxide portion 144 is less than 4/1, it can be ensured that the gate layer 130 has sufficient thickness to withstand the subsequent dry etching process.

In one embodiment, the height h1 of the first oxidized portion 122 may be above 2.4 μm, the height h2 of the second oxidized portion 124 may be above 1.2 μm, and the height h3 of the second gate oxidized portion 144 may be above 1.2 μm. For example, the height h1 of the first oxidized portion 122 may be 3±0.6 μm, the height h2 of the second oxidized portion 124 may be 1.5±0.3 μm, and the height h3 of the second gate oxidized portion 144 may be 1.5±0.3 μm. In this way, the gap S can be further prevented from extending to the surface of the second shielding portion 114, which is beneficial to the flatness of the surface of the second shielding portion 114. In a preferred embodiment, the ratio of the height h1 of the first oxidized portion 122, the height h2 of the second oxidized portion 124, and the height h3 of the second gate oxidized portion 144 is 2:1:1.

In FIG. 1 , the first trench T1 is disposed in the unit region R1 of the semiconductor substrate 100, and the semiconductor substrate 100 may further include a terminal region R2, and other component structures may exist between the unit region R1 and the terminal region R2. The terminal region R2 may surround the unit region R1, and the present invention is not limited to the layout of FIG. 1 . The semiconductor substrate 100 also includes a second trench T2 in the terminal region R2.

In the first embodiment, the trench power semiconductor device 10 further includes at least one guard ring 110' and a terminal oxide layer 120'. The guard ring 110' is disposed in the second trench T2, and includes a first guard ring portion 112' and a second guard ring portion 114'. The second guard ring portion 114' is located on the first guard ring portion 112', and the width w2' of the second guard ring portion 114' is greater than the width w1' of the first guard ring portion 112'. The terminal oxide layer 120' is located between the guard ring 110' and the semiconductor substrate 100, and includes a first terminal oxide portion 122' and a second terminal oxide portion 124'. The first terminal oxidation portion 122' surrounds the first protection ring portion 112', the second terminal oxidation portion 124' surrounds the second protection ring portion 114', and the thickness t2' of the second terminal oxidation portion 124' is less than the thickness t1' of the first terminal oxidation portion 122'. Since the protection ring 110' is disposed in the terminal region R2 and surrounds the cell region R1, the withstand voltage capability of the trench power semiconductor device 10 can be improved to prevent the components in the cell region R1 from being damaged by high voltage. It should be noted that although FIG. 1 shows only one guard ring 110', the number of guard rings 110' is usually related to the voltage range of the trench power semiconductor device 10, so the number of guard rings 110' is generally multiple.

In one embodiment, the height h1' of the first terminal oxidation portion 122' may be the same as the height h1 of the first oxidation portion 122. The height of the second terminal oxidation portion 124' is substantially the sum of the height h2 of the second oxidation portion 124 and the height h3 of the second gate oxidation portion 144.

In one embodiment, the second terminal oxidation portion 124' may extend from the sidewall of the second trench T2 to the surface 100s of the semiconductor substrate 100, but the present invention is not limited thereto.

In one embodiment, the material of the semiconductor substrate 100 includes silicon, for example. It should be understood that the semiconductor substrate 100 can be doped according to the prior art in the field to form doped regions (not shown) with different conductive properties therein, as the source, body region, etc. of the trench power semiconductor device 10, but the present invention is not limited thereto.

In one embodiment, the materials of the shielding gate 110, the gate layer 130 and the protection ring 110' are all polysilicon, for example, but the present invention is not limited thereto.

In one embodiment, the material of the oxide layer 120 and the terminal oxide layer 120' is, for example, silicon oxide, but the present invention is not limited thereto.

In one embodiment, the breakdown voltage of the trench power semiconductor device 10 may be greater than or equal to 30V.

In this embodiment, since the thickness t1 of the first oxidized portion 122 of the trench power semiconductor device 10 is greater than the thickness t2 of the second oxidized portion 124, the width w2 of the second shielding portion 114 deposited in the first trench T1 is greater than the width w1 of the first shielding portion 112, thereby avoiding the formation of a gap S at the top of the shielding gate 110; that is, no sharp recess will be generated on the surface of the shielding gate 110, thereby solving the problem of gate tip discharge, increasing the breakdown voltage of the trench power semiconductor device 10, and improving reliability.

Figures 2A to 2H are cross-sectional schematic diagrams of a manufacturing process of a trench power semiconductor device according to another embodiment of the present invention.

Referring to FIG. 2A , a semiconductor substrate 200 is provided. The material of the semiconductor substrate 200 is, for example, silicon. The semiconductor substrate 200 may include a cell region R1 and a terminal region R2. The terminal region R2 may surround the cell region R1 to improve the voltage resistance of the trench power semiconductor device and prevent the components in the cell region R1 from being damaged by high voltage.

Please continue to refer to FIG. 2A , a patterned hard mask layer 210 is formed on the surface 200s of the semiconductor substrate 200. The material of the patterned hard mask layer 210 is, for example, silicon nitride, but the present invention is not limited thereto. If the material of the patterned hard mask layer 210 is silicon nitride, the steps may be to first form a silicon oxide layer (not shown) on the surface 200s of the semiconductor substrate 200, then deposit a silicon nitride layer, and then form a patterned photoresist layer on the silicon nitride layer by a lithography process, and then use the aforementioned patterned photoresist layer as a mask to etch the silicon nitride layer to obtain the aforementioned patterned hard mask layer 210. Then, the patterned hard mask layer 210 is used as a mask to etch the exposed semiconductor substrate 200 to form a shallow trench T in the cell area R1 and a shallow trench T' in the terminal area R2 at the same time. If there is a silicon oxide layer on the surface 200s, the patterned hard mask layer 210 is also used as a mask to etch the oxide layer first and then the semiconductor substrate 200.

Next, please refer to FIG. 2B to form a thin oxide layer 220 on the sidewalls and bottom surface of the shallow trenches T and T’. The method of forming the thin oxide layer 220 is, for example, thermal oxidation. Then, in order to form a silicon nitride spacer on the thin oxide layer 220 on the sidewalls of the shallow trenches T and T’, a silicon nitride material layer 230 can be conformally formed on the surface of the patterned hard mask layer 210 and the sidewalls and bottom surface of the shallow trenches T and T’.

Afterwards, referring to FIG. 2C , the silicon nitride material layer 230 of FIG. 2B is etched back to form a silicon nitride spacer 230a. Next, the silicon nitride spacer 230a is used as a mask to etch away the thin oxide layer 220 on the bottom surface of the shallow trenches T, T’, exposing the bottom surface of the shallow trenches T, T’. Then, the patterned hard mask layer 210 and the silicon nitride spacer 230a are used as masks to etch the semiconductor substrate 200 exposed by the bottom surface of the shallow trenches T, T’, so as to form a first trench T1 in the cell region R1 and a second trench T2 in the terminal region R2. That is to say, the first trench T1 and the second trench T2 can be formed in the same process step without adding an additional mask process.

Subsequently, referring to FIG. 2D , a first oxidized portion 242 is formed at the bottom and part of the sidewall of the first trench T1. For example, a first oxidation reaction, such as a furnace oxidation method, may be performed to oxidize the semiconductor substrate 200 exposed by the first trench T1 to form the first oxidized portion 242 at the sidewall and bottom of the first trench T1 outside the silicon nitride spacer 230a. In this embodiment, during the first oxidation reaction, the semiconductor substrate 200 exposed by the second trench T2 may be oxidized at the same time to form the first terminal oxidized portion 244 at the sidewall and bottom of the second trench T2 outside the silicon nitride spacer 230a.

2D to 2E, in order to form the second oxidized portion on the sidewall of the first trench T1 not covered by the first oxidized portion 242, for example, the thin oxide layer 220, the patterned hard mask layer 210 and the silicon nitride spacer 230a can be removed by wet etching to expose a portion of the sidewall of the first trench T1 and a portion of the sidewall of the second trench T2. Thereafter, a second oxidation reaction is performed, such as a furnace oxidation method, to form the second oxidized portion 252 on the sidewall of the first trench T1, and the surface 200s of the semiconductor substrate 200 also has the second oxidized portion 252 formed. The thickness t5 of the first oxidized portion 242 is greater than the thickness t6 of the second oxidized portion 252. Since the first oxidized portion 242 and the second oxidized portion 252 are formed by a secondary oxidation reaction, and the thickness t5 of the first oxidized portion 242 is greater than the thickness t6 of the second oxidized portion 252, the first trench T1 has a space that is wide at the top and narrow at the bottom. In this embodiment, during the second oxidation reaction, the semiconductor substrate 200 exposed by the second trench T2 can be oxidized at the same time to form a second terminal oxidized portion 254 on the sidewall of the second trench T2, wherein the thickness t3' of the first terminal oxidized portion 244 is also greater than the thickness t4' of the second terminal oxidized portion 254.

Then, referring to FIG. 2F , in order to form a shielding gate 262 in the first trench T1, for example, a first polysilicon material layer (not shown) may be deposited by chemical vapor deposition to fill the first trench T1 and the second trench T2, and then chemical mechanical planarization (CMP) may be performed to remove the first polysilicon material layer outside the first trench T1 and the second trench T2, so that the first polysilicon material layer in the second trench T2 serves as a protective ring 264. Then, a patterned photoresist layer PR is formed on the second trench T2 to cover the protective ring 264 in the second trench T2. Afterwards, the first polysilicon material layer of the cell region R1 is etched using the patterned photoresist layer PR as a mask to form a shielding gate 262 in the cell region R1 and expose part of the second oxidized portion 252 on the sidewall of the first trench T1.

In FIG. 2F , a gap S may be formed during the process of depositing the first polysilicon material layer in the first trench T1 and the second trench T2. Since the first trench T1 has a space that is wide at the top and narrow at the bottom, the gap S mostly appears at the relatively narrow part of the protection ring 264 and the shielding gate 262; that is, the lower part of the protection ring 264 and the shielding gate 262 may have a gap S, and the upper part of the protection ring 264 and the shielding gate 262 basically has no gap S. In this way, the surface of the shielding gate 262 can be prevented from having sharp concave parts, thereby improving the problem of tip discharge and enhancing the reliability of the trench power semiconductor device.

Then, referring to FIG. 2G , the exposed second oxidized portion 252 is removed to expose a portion of the sidewall of the first trench T1. For example, the patterned photoresist layer PR can be used as a mask to etch the exposed second oxidized portion 252, but the present invention is not limited thereto. The patterned photoresist layer PR can be a photoresist layer different from the first polysilicon material layer for etching the cell region R1.

Afterwards, referring to FIG. 2H , a gate oxide layer 270 is formed on the surface of the shielding gate 262 and the exposed sidewall of the first trench T1. The method for forming the gate oxide layer 270 is, for example, a thermal oxidation method, wherein the material of the semiconductor substrate 100 is usually silicon and the material of the shielding gate 262 is polysilicon, so the oxidation rate of the surface of the shielding gate 262 is greater than the oxidation rate of the semiconductor substrate 200, and therefore the thickness t7 of the gate oxide layer 270 (i.e., the first gate oxide portion 272) formed on the surface of the shielding gate 262 is greater than the thickness t8 of the gate oxide layer 270 (i.e., the second gate oxide portion 274) formed on the sidewall of the first trench T1. In one embodiment, the ratio of the oxidation rate of the surface of the shielding gate 262 to the oxidation rate of the semiconductor substrate 200 is 2:1.

Please continue to refer to FIG. 2H to form a gate layer 280 on the gate oxide layer 270 in the first trench T1. For example, a second polysilicon material layer (not shown) can be deposited by chemical vapor deposition to fill the first trench T1, and then chemical mechanical planarization is performed to remove the second polysilicon material layer outside the first trench T1 to form a gate layer 280 on the first gate oxide portion 272. Then, the patterned photoresist layer PR is removed.

After the above process, the manufacturing of the trench power semiconductor device 20 of this embodiment can be basically completed.

Through the manufacturing method of the trench power semiconductor device 20, the thickness of the first oxidized portion 242 is greater than the thickness of the second oxidized portion 252, so that the shielding gate 262 has a shape that is wide at the top and narrow at the bottom, thereby preventing the gap S from being formed on the surface of the shielding gate 262, resulting in the surface of the shielding gate 262 having a sharp concave portion, thereby improving the problem of tip discharge and improving the breakdown voltage and reliability of the trench power semiconductor device 20.

In summary, the shielding gate of the trench power semiconductor device of the present invention includes a first shielding portion and a second shielding portion, the second shielding portion is located on the first shielding portion, and the width of the second shielding portion is greater than the width of the first shielding portion, so that the problem of tip discharge can be improved, the breakdown voltage of the trench power semiconductor device can be increased, and the reliability can be improved. In addition, the manufacturing method of the trench power semiconductor device of the present invention forms a first oxidation portion and a second oxidation portion on the side wall of the first trench through a secondary oxidation reaction, and the thickness of the first oxidation portion is greater than the thickness of the second oxidation portion. Therefore, the surface of the shielding gate can be prevented from generating a sharp concave area, thereby improving the problem of tip discharge and improving the breakdown voltage and reliability of the trench power semiconductor device.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

10: Trench power semiconductor device

100:Semiconductor substrate

100s: Surface

110: Shield gate

110’: Protective ring

112: First shielding part

112’: First protection ring section

114: Second shielding part

114’: Second protection ring section

120: Oxide layer

120’: terminal oxide layer

122: First oxidation part

122’: first terminal oxidation part

124: Second oxidation part

124': Second terminal oxidation part

130: Gate layer

140: Gate oxide layer

142: First gate oxidation part

144: Second gate oxidation part

h1, h2, h3, h1’, h2’: height

R1: Unit area

R2: Terminal area

S: Gap

t1, t2, t3, t4, t1’, t2’: thickness

T1: First groove

T2: Second groove

w1, w2, w1’, w2’: width

Claims (12)

A trench power semiconductor device comprises: a semiconductor substrate having a first trench; a shielding gate arranged in the first trench, wherein the shielding gate comprises a first shielding portion and a second shielding portion, the second shielding portion is located on the first shielding portion, and the width of the second shielding portion is greater than the width of the first shielding portion; an oxide layer arranged between the shielding gate and the semiconductor substrate, wherein the oxide layer comprises a first oxide portion and a second oxide portion, the first oxide portion surrounds the first shielding portion, the second oxide portion surrounds the second shielding portion, and the thickness of the first oxide portion is greater than the thickness of the second oxide portion, wherein the first oxide layer is The ratio of the thickness of the first oxide portion to the thickness of the second oxide portion is between 7/6 and 4/3; a gate layer is arranged in the first trench and is located on the shielding gate; and a gate oxide layer includes: a first gate oxide portion is arranged between the gate layer and the second shielding portion of the shielding gate; and a second gate oxide portion is arranged between the gate layer and the semiconductor substrate, wherein the thickness of the second gate oxide portion is less than the thickness of the second oxide portion, wherein the height of the first oxide portion is 3±0.6μm, the height of the second oxide portion is 1.5±0.3μm, and the height of the second gate oxide portion is 1.5±0.3μm. A trench power semiconductor device as described in claim 1, wherein the thickness of the first gate oxide portion is greater than the thickness of the second gate oxide portion. A trench-type power semiconductor device as described in claim 1, wherein the semiconductor substrate includes a cell region and a terminal region, the first trench is disposed in the cell region, and the semiconductor substrate further includes a second trench in the terminal region. The trench power semiconductor device as described in claim 3 further comprises: at least one guard ring disposed in the second trench, wherein the guard ring comprises a first guard ring portion and a second guard ring portion, the second guard ring portion is located on the first guard ring portion, and the width of the second guard ring portion is greater than the width of the first guard ring portion; and a terminal oxide layer disposed between the guard ring and the semiconductor substrate, wherein the terminal oxide layer comprises a first terminal oxide portion and a second terminal oxide portion, the first terminal oxide portion surrounds the first guard ring portion, the second terminal oxide portion surrounds the second guard ring portion, and the thickness of the second terminal oxide portion is less than the thickness of the first terminal oxide portion. A method for manufacturing a trench power semiconductor device, comprising: providing a semiconductor substrate; forming a first trench in the semiconductor substrate; forming a first oxide portion at the bottom and part of the sidewall of the first trench; forming a second oxide portion on the sidewall of the first trench not covered by the first oxide portion, wherein the thickness of the first oxide portion is greater than the thickness of the second oxide portion; forming a shielding gate in the first trench and exposing part of the second oxide portion; removing the exposed second oxide portion to expose part of the sidewall of the first trench; forming a gate oxide layer on the surface of the shielding gate and the exposed sidewall of the first trench, wherein the thickness of the gate oxide layer is less than the thickness of the second oxide portion; and forming a gate layer on the gate oxide layer in the first trench. The manufacturing method of the trench power semiconductor device as described in claim 5, wherein the semiconductor substrate includes a cell region and a terminal region, the first trench is formed in the cell region, and the step of forming the first trench includes: simultaneously forming a second trench in the terminal region of the semiconductor substrate. The manufacturing method of the trench power semiconductor device as described in claim 6, wherein the step of forming the first oxidation portion includes: simultaneously forming a first terminal oxidation portion at the bottom and part of the sidewall of the second trench. The manufacturing method of the trench power semiconductor device as described in claim 7, wherein the step of forming the second oxidation portion includes: simultaneously forming a second terminal oxidation portion on the sidewall of the second trench not covered by the first terminal oxidation portion. The manufacturing method of the trench power semiconductor device as described in claim 8, wherein the step of forming the shielding gate includes: depositing a polysilicon material layer in the first trench and the second trench, wherein the polysilicon material layer in the second trench serves as a protective ring; forming a patterned photoresist layer on the second trench to cover the protective ring in the second trench; and etching the polysilicon material layer in the cell area using the patterned photoresist layer as a mask to form the shielding gate in the cell area. The manufacturing method of the trench power semiconductor device as described in claim 5, wherein the step of forming the first trench in the semiconductor substrate comprises: forming a patterned hard mask layer on the surface of the semiconductor substrate; using the patterned hard mask layer as a mask to etch the exposed semiconductor substrate to form a shallow trench; forming a thin oxide layer on the sidewall and bottom of the shallow trench; A silicon nitride spacer is formed on the thin oxide layer of the sidewall of the shallow trench; the silicon nitride spacer is used as a mask to etch away the thin oxide layer on the bottom surface of the shallow trench; and the patterned hard mask layer and the silicon nitride spacer are used as a mask to etch the semiconductor substrate exposed on the bottom surface of the shallow trench to form the first trench. The manufacturing method of the trench power semiconductor device as described in claim 10, wherein the step of forming the first oxidized portion includes: performing a first oxidation reaction to form the first oxidized portion on the sidewall and the bottom of the first trench outside the silicon nitride spacer. The manufacturing method of the trench power semiconductor device as described in claim 11, wherein the step of forming the second oxidized portion includes: removing the thin oxide layer, the patterned hard mask layer and the silicon nitride spacer to expose a portion of the sidewall of the first trench; and performing a second oxidation reaction to form the second oxidized portion.

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