CN116845102A - Trench power semiconductor device and method of manufacturing the same - Google Patents
Trench power semiconductor device and method of manufacturing the same Download PDFInfo
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- CN116845102A CN116845102A CN202210485429.9A CN202210485429A CN116845102A CN 116845102 A CN116845102 A CN 116845102A CN 202210485429 A CN202210485429 A CN 202210485429A CN 116845102 A CN116845102 A CN 116845102A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 130
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000007254 oxidation reaction Methods 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 30
- 230000003647 oxidation Effects 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 230000008021 deposition Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention provides a trench type power semiconductor device and a method for manufacturing the same. The trench type power semiconductor device comprises a semiconductor substrate, a shielding gate, an oxide layer, a gate layer and a gate oxide layer. The shielding gate is arranged in the first groove of the semiconductor substrate and comprises a first shielding part and a second shielding part positioned on the first shielding part, wherein the width of the second shielding part is larger than that of the first shielding part. The oxide layer is arranged between the shielding gate and the semiconductor substrate, and comprises a first oxide part surrounding the first shielding part and a second oxide part surrounding the second shielding part, wherein the thickness of the first oxide part is larger than that of the second oxide part. The grid layer is arranged in the first groove and is positioned on the shielding grid. The gate oxide layer includes a first gate oxide portion disposed between the gate layer and the second shielding portion and a second gate oxide portion disposed between the gate layer and the semiconductor substrate. The thickness of the second gate oxide portion is smaller than the thickness of the second oxide portion.
Description
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a trench type power semiconductor device and a method for manufacturing the same.
Background
Trench power semiconductor devices such as trench split gate power metal oxide semiconductor field effect transistors (split-gate MOSFETs) have high breakdown voltage and low on-resistance characteristics and are suitable for use as medium and low voltage high power devices.
However, in the existing trench type split gate power mosfet technology, because the trench depth is deep, a slit (sea) is easily formed in the shielding gate during the deposition of the shielding gate, and a sharp recess is formed on the surface of the shielding gate after etching back, so that the gate subsequently formed on the shielding gate has a corresponding sharp corner, which easily causes a problem of tip discharge, and further affects the performance of the trench type power semiconductor device.
Disclosure of Invention
The invention provides a trench power semiconductor device, which can improve the problem of tip discharge at a gate and improve the reliability of the trench power semiconductor device.
The invention also provides a manufacturing method of the trench type power semiconductor device, which can prevent a gap from being formed in the shielding gate or prevent the gap from approaching the surface of the shielding gate, so as to avoid sharp concave parts from being generated on the surface of the shielding gate, further improve the problem of tip discharge and improve the reliability of the trench type power semiconductor device.
According to an embodiment of the present invention, the trench power semiconductor device includes a semiconductor substrate, a shielding gate, an oxide layer, a gate layer, and a gate oxide layer. The semiconductor substrate is provided with a first groove, and the shielding gate is arranged in the first groove. The shielding grid comprises a first shielding part and a second shielding part, wherein the second shielding part is positioned on the first shielding part, and the width of the second shielding part is larger than that of the first shielding part. The oxide layer is arranged between the shielding gate and the semiconductor substrate. The oxide layer comprises a first oxide part and a second oxide part, the first oxide part surrounds the first shielding part, the second oxide part surrounds the second shielding part, and the thickness of the first oxide part is larger than that of the second oxide part. The grid electrode layer is arranged in the first groove and is positioned on the shielding grid. The gate oxide layer includes a first gate oxide portion and a second gate oxide portion. The first gate oxide part is arranged between the gate layer and a second shielding part of the shielding gate, and the second gate oxide part is arranged between the gate layer and the semiconductor substrate. The thickness of the second gate oxide portion is smaller than the thickness of the second oxide portion.
In the trench power semiconductor device according to the embodiment of the invention, a ratio of the thickness of the first oxidized portion to the thickness of the second oxidized portion is 7/6 or more.
In the trench power semiconductor device according to the embodiment of the invention, the thickness of the first gate oxide portion is greater than the thickness of the second gate oxide portion.
In the trench power semiconductor device according to the embodiment of the invention, the height of the first oxide portion is 3±0.6 μm, the height of the second oxide portion is 1.5±0.3 μm, and the height of the second gate oxide portion is 1.5±0.3 μm.
In the trench power semiconductor device according to the embodiment of the invention, the semiconductor substrate includes a cell region and a termination region, the first trench is disposed in the cell region, and the semiconductor substrate further includes a second trench in the termination region.
In the trench power semiconductor device according to the embodiment of the invention, the trench power semiconductor device further includes at least one protection ring and a termination oxide layer. At least one protection ring is disposed in the second trench. The guard ring may include a first guard ring portion and a second guard ring portion, the second guard ring portion being located on the first guard ring portion, and a width of the second guard ring portion being greater than a width of the first guard ring portion. The terminal oxide layer is positioned between the protection ring and the semiconductor substrate, the terminal oxide layer comprises a first terminal oxide part and a second terminal oxide part, the first terminal oxide part surrounds the first protection ring part, the second terminal oxide part surrounds the second protection ring part, and the thickness of the second terminal oxide part is smaller than that of the first terminal oxide part.
According to another embodiment of the present invention, the method of manufacturing a trench power semiconductor device of the present invention includes the following steps. A semiconductor substrate is provided, and a first trench is formed in the semiconductor substrate. Then, a first oxidation part is formed at the bottom and part of the side wall of the first groove, and a second oxidation part is formed on the side wall of the first groove which is not covered by the first oxidation part, wherein the thickness of the first oxidation part is larger than that of the second oxidation part. And forming a shielding gate in the first trench, exposing a part of the second oxidation part, and removing the exposed second oxidation part to expose a part of the side wall of the first trench. And forming a gate oxide layer on the surface of the shielding gate and the exposed side wall of the first groove, wherein the thickness of the gate oxide layer is smaller than that of the second oxide part. And forming a gate layer on the gate oxide layer in the first trench.
In the method for manufacturing the trench power semiconductor device according to the embodiment of the invention, the semiconductor substrate includes a cell region and a termination region, the first trench is formed in the cell region, and the step of forming the first trench includes forming the second trench in the termination region of the semiconductor substrate at the same time.
In the method for manufacturing a trench power semiconductor device according to an embodiment of the invention, the step of forming the first oxide portion includes forming a first termination oxide portion at the bottom and a portion of the sidewall of the second trench at the same time.
In the method of manufacturing a trench type power semiconductor device according to an embodiment of the present invention, the step of forming the second oxide portion includes forming the second terminal oxide portion on the sidewall of the second trench not covered by the first terminal oxide portion at the same time.
In the method for manufacturing a trench type power semiconductor device according to an embodiment of the invention, the step of forming the shielding gate includes depositing a polysilicon material layer in the first trench and the second trench, wherein the polysilicon material layer in the second trench is used as a guard ring. Then, a patterned photoresist layer is formed on the second trench to cover the guard ring in the second trench, and the polysilicon material layer of the cell area is etched by taking the patterned photoresist layer as a mask, so as to form a shielding gate in the cell area.
In the method for manufacturing a trench power semiconductor device according to an embodiment of the invention, the step of forming the first trench in the semiconductor substrate includes: forming a patterned hard mask layer on the surface of the semiconductor substrate, and etching the exposed semiconductor substrate by using the patterned hard mask layer as a mask to form a shallow trench. And forming a thin oxide layer on the side wall and the bottom surface of the shallow trench, and forming a silicon nitride spacer on the thin oxide layer on the side wall of the shallow trench. And etching to remove the thin oxide layer on the bottom surface of the shallow trench by using the silicon nitride spacer as a mask, and etching the semiconductor substrate exposed on the bottom surface of the shallow trench by using the patterned hard mask layer and the silicon nitride spacer as masks to form a first trench.
In the method for manufacturing a trench power semiconductor device according to an embodiment of the invention, the step of forming the first oxide portion includes performing a first oxidation reaction to form the first oxide portion on the sidewall and the bottom of the first trench except the silicon nitride spacer.
In the method for manufacturing a trench type power semiconductor device according to an embodiment of the invention, the step of forming the second oxide portion includes removing the thin oxide layer, patterning the hard mask layer and the silicon nitride spacer to expose a portion of the sidewall of the first trench, and performing a second oxidation reaction to form the second oxide portion.
Based on the above, the oxide layer formed on the trench sidewall of the trench type power semiconductor device of the present invention has the feature of being thin at the top and thick at the bottom, so that the shield gate formed therein has a structure with wide top and narrow bottom, thereby preventing the generation of a gap when the shield gate is formed by deposition. Even if a gap is formed in the shielding gate, only the lower part of the shielding gate is provided with the gap due to the structural characteristics of the oxide layer, and no sharp concave is generated on the surface of the shielding gate, so that the problem of gate tip discharge can be solved, the breakdown voltage of the trench type power semiconductor device can be improved, and the reliability can be improved.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic cross-sectional view of a trench power semiconductor device according to an embodiment of the invention.
Fig. 2A to 2H are schematic cross-sectional views illustrating a manufacturing process of a trench power semiconductor device according to another embodiment of the present invention.
Description of the reference numerals
10. 20 trench power semiconductor device
100. 200 semiconductor substrate
100s, 200s surface
110. 262 of the shielding grid
110', 264 guard ring
112 first masking portion
112' first guard ring portion
114 a second shielding portion
114': second guard ring portion
120 oxide layer
120' terminal oxide layer
122. 242 first oxidized portion
122', 244 first terminal oxidation portion
124. 252 second oxidation portion
124', 254 second terminal oxidation portion
130. 280 gate layer
140. 270 gate oxide layer
142. 272 first gate oxide portion
144. 274 second gate oxide portion
210 patterning hard mask layer
220 thin oxide layer
230 silicon nitride material layer
230a silicon nitride spacer
height of h1, h2, h3, h1', h2'
PR patterning photoresist layer
R1:unit region
R2:
s is a gap
thickness of t1, t2, t3, t4, t5, t6, t7, t8, t1', t2', t3', t4'
T, T' shallow trench
T1 first groove
T2:second trench
width w1, w2, w1', w2'
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
The following examples are set forth in detail in connection with the accompanying drawings, but are not intended to limit the scope of the invention. Moreover, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, like components in the following description will be described with like reference numerals.
Furthermore, the terms "comprising," including, "" having, "and the like, as used herein, are open-ended terms, meaning" including, but not limited to.
It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various components, elements, regions, layers and/or sections, these components, elements, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first component," "section," "region," "layer," or "portion" discussed below could be termed a second component, region, layer, or portion without departing from the teachings herein.
In addition, directional terms, such as "upper", "lower", etc., are used only with reference to the directions of the drawings, and are not intended to limit the present invention.
Fig. 1 is a schematic cross-sectional view of a trench power semiconductor device according to an embodiment of the invention.
Referring to fig. 1, the trench power semiconductor device 10 includes a semiconductor substrate 100, a shielding gate 110, an oxide layer 120, a gate layer 130 and a gate oxide layer 140. The semiconductor substrate 100 has a first trench T1. The shielding gate 110 is disposed in the first trench T1, and the shielding gate 110 includes a first shielding portion 112 and a second shielding portion 114. The second shielding portion 114 is located on the first shielding portion 112, and a width w2 of the second shielding portion 114 is greater than a width w1 of the first shielding portion 112. The oxide layer 120 is disposed between the shielding gate 110 and the semiconductor substrate 100, and the oxide layer 120 includes a first oxide portion 122 and a second oxide portion 124. The first oxidized portion 122 surrounds the first shielding portion 112, the second oxidized portion 124 surrounds the second shielding portion 114, and the thickness t1 of the first oxidized portion 122 is greater than the thickness t2 of the second oxidized portion 124. In the first embodiment, there may be a slit S formed in the first shielding portion 112 and at a lower portion of the second shielding portion 114 in the inside of the shielding gate 110. However, the presence of the slit S does not affect the interface profile between the gate 130 and the shielding gate 110; that is, the surface of the shielding gate 110 does not generate a sharp recess. In a preferred embodiment, the shielding gate 110 has no slit S inside or the slit S is formed only in the first shielding portion 112.
In one embodiment, the ratio of the thickness t1 of the first oxidized portion 122 to the thickness t2 of the second oxidized portion 124 may be above 7/6, such as between 7/6 and 4/3. If the ratio of the thickness t1 of the first oxidized portion 122 to the thickness t2 of the second oxidized portion 124 is 7/6 or more, the upper edge of the gap can be ensured to be maintained near the junction of the first oxidized portion 122 and the second oxidized portion 124; if the ratio of the thickness T1 of the first oxidized portion 122 to the thickness T2 of the second oxidized portion 124 is less than 4/2, the width of the first trench T1 within the range of the height h1 of the first oxidized portion 122 is prevented from being too wide, which limits the micro-scale range of the first trench T1 pitch.
With continued reference to fig. 1, the gate layer 130 is disposed in the first trench T1 and is located on the shielding gate 110. The gate oxide layer 140 includes a first gate oxide portion 142 and a second gate oxide portion 144. The first gate oxide portion 142 is disposed between the gate layer 130 and the second shielding portion 114 of the shielding gate 110, and the second gate oxide portion 144 is disposed between the gate layer 130 and the semiconductor substrate 100, wherein the second gate oxide portion 144 may extend from a sidewall of the first trench T1 to the surface 100s of the semiconductor substrate 100, but the present invention is not limited thereto; in another embodiment, the second gate oxide portion 144 may be formed only on the sidewall of the first trench T1. In the first embodiment, the thickness t4 of the second gate oxide 144 is smaller than the thickness t2 of the second oxide 124, so that the drain-source capacitance between the shielding gate 110 and the semiconductor substrate 100 is sufficiently low. The ratio of the thickness t2 of the second oxide portion 124 to the thickness t4 of the second gate oxide portion 144 can be adjusted according to practical requirements, and the invention is not limited thereto. The gate oxide layer 140 may be formed by a furnace oxidation method, and because the material of the semiconductor substrate 100 is typically silicon, and the material of the shielding gate 110 is typically polysilicon, the thickness t3 of the first gate oxide portion 142 is typically greater than the thickness t4 of the second gate oxide portion 144 due to the difference in oxidation rates between the two, resulting in the thickness t3 of the first gate oxide portion 142 being different from the thickness t4 of the second gate oxide portion 144. However, the material of the semiconductor substrate 100 and the material of the shielding gate 110 are not limited to the above, and other materials known in the semiconductor field may be used instead.
In one embodiment, the ratio of the thickness t3 of the first gate oxide portion 142 to the thickness t4 of the second gate oxide portion 144 may be between 3/1 and 4/1. If the ratio of the thickness t3 of the first gate oxide portion 142 to the thickness t4 of the second gate oxide portion 144 is 3/1 or more, a sufficient withstand voltage between the shield gate 110 and the gate layer 130 can be ensured; if the ratio of the thickness t3 of the first gate oxide portion 142 to the thickness t4 of the second gate oxide portion 144 is less than 4/1, a sufficient thickness of the gate layer 130 can be ensured to withstand the subsequent dry etching process.
In one embodiment, the height h1 of the first oxide portion 122 may be above 2.4 μm, the height h2 of the second oxide portion 124 may be above 1.2 μm, and the height h3 of the second gate oxide portion 144 may be above 1.2 μm. For example: the height h1 of the first oxide portion 122 may be 3±0.6 μm, the height h2 of the second oxide portion 124 may be 1.5±0.3 μm, and the height h3 of the second gate oxide portion 144 may be 1.5±0.3 μm. In this way, the slit S can be further prevented from extending toward the surface of the second shielding portion 114, which is beneficial to the flatness of the surface of the second shielding portion 114. In a preferred embodiment, the ratio of the height h1 of the first oxide portion 122, the height h2 of the second oxide portion 124, and the height h3 of the second gate oxide portion 144 is 2:1:1.
In fig. 1, the first trench T1 is disposed in the cell region R1 of the semiconductor substrate 100, and the semiconductor substrate 100 may further include a terminal region R2, and other device structures may exist between the cell region R1 and the terminal region R2. The termination region R2 may surround the cell region R1, and the present invention is not limited to the layout of fig. 1. The semiconductor substrate 100 further includes a second trench T2 in the termination region R2.
In the first embodiment, the trench power semiconductor device 10 further includes at least one protection ring 110 'and a termination oxide layer 120'. The guard ring 110' is disposed in the second trench T2, and includes a first guard ring portion 112' and a second guard ring portion 114'. The second guard ring portion 114 'is located on the first guard ring portion 112', and a width w2 'of the second guard ring portion 114' is greater than a width w1 'of the first guard ring portion 112'. The termination oxide layer 120 'is located between the guard ring 110' and the semiconductor substrate 100, and includes a first termination oxide portion 122 'and a second termination oxide portion 124'. The first terminal oxide portion 122 'surrounds the first guard ring portion 112', the second terminal oxide portion 124 'surrounds the second guard ring portion 114', and the thickness t2 'of the second terminal oxide portion 124' is less than the thickness t1 'of the first terminal oxide portion 122'. Since the guard ring 110' is disposed in the terminal region R2 and surrounds the cell region R1, the voltage withstanding capability of the trench type power semiconductor device 10 can be improved, and the components in the cell region R1 are prevented from being damaged due to high voltage. It should be noted that although only one guard ring 110' is shown in fig. 1, the number of guard rings 110' is generally related to the voltage range of the trench type power semiconductor device 10, so the number of guard rings 110' is generally plural.
In an embodiment, the height h1 'of the first terminal oxidation part 122' may be the same as the height h1 of the first oxidation part 122. The height of the second terminal oxide portion 124' is substantially the sum of the height h2 of the second oxide portion 124 and the height h3 of the second gate oxide portion 144.
In an embodiment, the second terminal oxide portion 124' may extend from the sidewall of the second trench T2 to the surface 100s of the semiconductor substrate 100, but the invention is not limited thereto.
In one embodiment, the material of the semiconductor substrate 100 includes, for example, silicon. It should be appreciated that the semiconductor substrate 100 may be doped with dopants according to the prior art to form doped regions (not shown) having different conductive properties therein as source, body, etc. of the trench type power semiconductor device 10, but the invention is not limited thereto.
In an embodiment, the materials of the shielding gate 110, the gate layer 130 and the guard ring 110' are polysilicon, but the invention is not limited thereto.
In an embodiment, the material of the oxide layer 120 and the termination oxide layer 120' is, for example, silicon oxide, but the invention is not limited thereto.
In one embodiment, the breakdown voltage of the trench power semiconductor device 10 may be greater than or equal to 30V.
In the present embodiment, since the thickness T1 of the first oxidized portion 122 of the trench type power semiconductor device 10 is greater than the thickness T2 of the second oxidized portion 124, the width w2 of the second shielding portion 114 deposited in the first trench T1 is made greater than the width w1 of the first shielding portion 112, so that the formation of the gap S on top of the shielding gate 110 is avoided; that is, the surface of the shielding gate 110 does not generate a sharp recess, so that the problem of gate tip discharge can be solved, the breakdown voltage of the trench type power semiconductor device 10 can be increased, and the reliability can be improved.
Fig. 2A to 2H are schematic cross-sectional views illustrating a manufacturing process of a trench power semiconductor device according to another embodiment of the present invention.
Referring to fig. 2A, a semiconductor substrate 200 is provided. The material of the semiconductor substrate 200 is, for example, silicon. The semiconductor substrate 200 may include a cell region R1 and a terminal region R2, wherein the terminal region R2 may surround the cell region R1 to improve the voltage endurance of the trench type power semiconductor device and prevent components in the cell region R1 from being damaged due to high voltage.
With continued reference to fig. 2A, a patterned hard mask layer 210 is formed on the surface 200s of the semiconductor substrate 200. The material of the patterned hard mask layer 210 is, for example, silicon nitride, but the invention is not limited thereto. If the material of the patterned hard mask layer 210 is silicon nitride, a silicon oxide layer (not shown) may be formed on the surface 200s of the semiconductor substrate 200, a silicon nitride layer may be formed by deposition, a patterned photoresist layer may be formed on the silicon nitride layer by using a photolithography process, and the patterned photoresist layer may be used as a mask to etch the silicon nitride layer, thereby obtaining the patterned hard mask layer 210. Then, the exposed semiconductor substrate 200 is etched using the patterned hard mask layer 210 as a mask to form a shallow trench T in the cell region R1 and a shallow trench T' in the terminal region R2 at the same time. If the surface 200s has a silicon oxide layer, the oxide layer is etched and then the semiconductor substrate 200 is etched, again using the patterned hard mask layer 210 as a mask.
Next, referring to fig. 2B, a thin oxide layer 220 is formed on the sidewalls and bottom of the shallow trench T, T'. The method of forming the thin oxide layer 220 is, for example, a thermal oxidation method. Then, to form a silicon nitride spacer on the thin oxide layer 220 on the sidewall of the shallow trench T, T ', a silicon nitride material layer 230 may be conformally formed on the surface of the patterned hard mask layer 210 and the sidewalls and bottom surface of the shallow trench T, T'.
Then, referring to fig. 2C, the silicon nitride material layer 230 of fig. 2B is etched back to form silicon nitride spacers 230a. Next, using the silicon nitride spacers 230a as a mask, the thin oxide layer 220 on the bottom surface of the shallow trench T, T 'is etched away, exposing the bottom surface of the shallow trench T, T'. Then, the semiconductor substrate 200 exposed at the bottom of the shallow trench T, T' is etched using the patterned hard mask layer 210 and the silicon nitride spacers 230a as a mask to form a first trench T1 in the cell region R1 and a second trench T2 in the terminal region R2. That is, the first trench T1 and the second trench T2 may be formed in the same process step without adding an additional masking process.
Next, referring to fig. 2D, a first oxide portion 242 is formed at the bottom and a portion of the sidewall of the first trench T1. For example, a first oxidation reaction, such as a furnace oxidation, may be performed to oxidize the semiconductor substrate 200 exposed by the first trench T1, so as to form a first oxidized portion 242 on the sidewall and the bottom of the first trench T1 except for the silicon nitride spacer 230a. In this embodiment, during the first oxidation reaction, the exposed semiconductor substrate 200 of the second trench T2 is oxidized simultaneously to form the first terminal oxide 244 on the sidewall and bottom of the second trench T2 except the silicon nitride spacer 230a.
Referring to fig. 2D to fig. 2E, in order to form a second oxide portion on the sidewall of the first trench T1 not covered by the first oxide portion 242, for example, the thin oxide layer 220, the patterned hard mask layer 210 and the silicon nitride spacer 230a may be removed by wet etching to expose a portion of the sidewall of the first trench T1 and a portion of the sidewall of the second trench T2. Then, a second oxidation reaction, such as a furnace oxidation, is performed to form a second oxidized portion 252 on the sidewall of the first trench T1, and the second oxidized portion 252 is also formed on the surface 200s of the semiconductor substrate 200. The thickness t5 of the first oxidized portion 242 is greater than the thickness t6 of the second oxidized portion 252. Since the first oxidized portion 242 and the second oxidized portion 252 are formed by the secondary oxidation reaction, and the thickness T5 of the first oxidized portion 242 is greater than the thickness T6 of the second oxidized portion 252, the first trench T1 has a space with a wide upper portion and a narrow lower portion. In this embodiment, during the second oxidation reaction, the semiconductor substrate 200 exposed by the second trench T2 is oxidized simultaneously to form the second terminal oxide portion 254 on the sidewall of the second trench T2, wherein the thickness T3 'of the first terminal oxide portion 244 is also greater than the thickness T4' of the second terminal oxide portion 254.
Then, referring to fig. 2F, in order to form the shielding gate 262 in the first trench T1, for example, a first polysilicon material layer (not shown) is deposited by chemical vapor deposition to fill the first trench T1 and the second trench T2, and then Chemical Mechanical Planarization (CMP) is performed to remove the first polysilicon material layer outside the first trench T1 and the second trench T2, so that the first polysilicon material layer in the second trench T2 serves as the guard ring 264. Then, a patterned photoresist layer PR is formed on the second trench T2 to cover the guard ring 264 in the second trench T2. Then, the first polysilicon material layer of the cell region R1 is etched using the patterned photoresist layer PR as a mask, so as to form a shielding gate 262 in the cell region R1 and expose a portion of the second oxide portion 252 of the sidewall of the first trench T1.
In fig. 2F, a gap S may be formed during the deposition of the first polysilicon material layer in the first trench T1 and the second trench T2. Because the first trench T1 has a space with a wide upper part and a narrow lower part, the gap S is mostly formed at the relatively narrow part of the protection ring 264 and the shielding gate 262; that is, the lower portions of the guard ring 264 and the shielding gate 262 may have a slit S, and the upper portions of the guard ring 264 and the shielding gate 262 may have substantially no slit S. In this way, the sharp recess on the surface of the shielding gate 262 can be avoided, so as to improve the problem of the tip discharge and improve the reliability of the trench type power semiconductor device.
Then, referring to fig. 2G, the exposed second oxide portion 252 is removed to expose a portion of the sidewall of the first trench T1. For example, the exposed second oxide portion 252 may be etched using the patterned photoresist layer PR as a mask, but the invention is not limited thereto. The patterned photoresist layer PR may be a photoresist layer different from the first polysilicon material layer of the etched cell region R1.
Then, referring to fig. 2H, a gate oxide layer 270 is formed on the surface of the shielding gate 262 and the exposed sidewalls of the first trench T1. The gate oxide layer 270 is formed by a method such as a thermal oxidation method in which the material of the semiconductor substrate 100 is typically silicon and the material of the shielding gate 262 is polysilicon, so that the oxidation rate of the surface of the shielding gate 262 is greater than that of the semiconductor substrate 200, and thus the thickness T7 of the gate oxide layer 270 (i.e., the first gate oxide portion 272) formed on the surface of the shielding gate 262 is greater than the thickness T8 of the gate oxide layer 270 (i.e., the second gate oxide portion 274) formed on the sidewall of the first trench T1. In one embodiment, the ratio of the oxidation rate of the surface of the shielding gate 262 to the oxidation rate of the semiconductor substrate 200 is 2:1.
With continued reference to fig. 2H, a gate layer 280 is formed on the gate oxide layer 270 in the first trench T1. For example, a second polysilicon material layer (not shown) may be deposited by chemical vapor deposition to fill the first trench T1, and then subjected to chemical mechanical planarization to remove the second polysilicon material layer outside the first trench T1, thereby forming the gate layer 280 on the first gate oxide portion 272. Then, the patterned photoresist layer PR is removed.
After the above process, the fabrication of the trench power semiconductor device 20 of the present embodiment is substantially completed.
By the above method for manufacturing the trench power semiconductor device 20, the thickness of the first oxide portion 242 is greater than the thickness of the second oxide portion 252, so that the shielding gate 262 has a shape with a wide upper portion and a narrow lower portion, and thus the formation of the slit S on the surface of the shielding gate 262 can be avoided, the surface of the shielding gate 262 has a sharp recess, and the problem of tip discharge is improved, and the breakdown voltage and reliability of the trench power semiconductor device 20 are improved.
In summary, the shielding gate of the trench type power semiconductor device of the present invention includes the first shielding portion and the second shielding portion, the second shielding portion is located on the first shielding portion, and the width of the second shielding portion is greater than that of the first shielding portion, so that the problem of the tip discharge can be improved, the breakdown voltage of the trench type power semiconductor device can be increased, and the reliability can be improved. In addition, the manufacturing method of the trench type power semiconductor device forms the first oxidation part and the second oxidation part on the side wall of the first trench through the secondary oxidation reaction, and the thickness of the first oxidation part is larger than that of the second oxidation part, so that sharp concave parts generated on the surface of the shielding gate can be avoided, the problem of tip discharge is further improved, and the breakdown voltage and the reliability of the trench type power semiconductor device are improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (14)
1. A trench power semiconductor device, comprising:
a semiconductor substrate having a first trench;
the shielding grid is arranged in the first groove, wherein the shielding grid comprises a first shielding part and a second shielding part, the second shielding part is positioned on the first shielding part, and the width of the second shielding part is larger than that of the first shielding part;
the oxide layer is arranged between the shielding grid and the semiconductor substrate, wherein the oxide layer comprises a first oxide part and a second oxide part, the first oxide part surrounds the first shielding part, the second oxide part surrounds the second shielding part, and the thickness of the first oxide part is larger than that of the second oxide part;
the grid electrode layer is arranged in the first groove and is positioned on the shielding grid; and
a gate oxide layer comprising:
a first gate oxide portion disposed between the gate layer and the second shielding portion of the shielding gate; and
and a second gate oxide portion disposed between the gate layer and the semiconductor substrate, wherein a thickness of the second gate oxide portion is less than the thickness of the second oxide portion.
2. The trench power semiconductor device according to claim 1, wherein a ratio of the thickness of the first oxidized portion to the thickness of the second oxidized portion is 7/6 or more.
3. The trench power semiconductor device of claim 1 wherein a thickness of the first gate oxide portion is greater than a thickness of the second gate oxide portion.
4. The trench power semiconductor device of claim 1 wherein the height of the first oxide portion is 3±0.6 μm, the height of the second oxide portion is 1.5±0.3 μm, and the height of the second gate oxide portion is 1.5±0.3 μm.
5. The trench power semiconductor device of claim 1 wherein the semiconductor substrate comprises a cell region and a termination region, the first trench is disposed in the cell region, and the semiconductor substrate further comprises a second trench in the termination region.
6. The trench power semiconductor device of claim 5, further comprising:
at least one guard ring disposed in the second trench, wherein the guard ring comprises a first guard ring portion and a second guard ring portion, the second guard ring portion is located on the first guard ring portion, and a width of the second guard ring portion is greater than a width of the first guard ring portion; and
the terminal oxide layer is positioned between the protection ring and the semiconductor substrate, wherein the terminal oxide layer comprises a first terminal oxide part and a second terminal oxide part, the first terminal oxide part surrounds the first protection ring part, the second terminal oxide part surrounds the second protection ring part, and the thickness of the second terminal oxide part is smaller than that of the first terminal oxide part.
7. A method of manufacturing a trench power semiconductor device, comprising:
providing a semiconductor substrate;
forming a first groove in the semiconductor substrate;
forming a first oxidation part at the bottom and part of the side wall of the first groove;
forming a second oxidized portion on the sidewall of the first trench not covered by the first oxidized portion, wherein the thickness of the first oxidized portion is greater than the thickness of the second oxidized portion;
forming a shielding gate in the first trench and exposing a part of the second oxide portion;
removing the exposed second oxidized portion to expose a portion of the sidewall of the first trench;
forming a gate oxide layer on the surface of the shielding gate and the exposed side wall of the first groove, wherein the thickness of the gate oxide layer is smaller than that of the second oxide part; and
forming a gate layer on the gate oxide layer in the first trench.
8. The method of claim 7, wherein the semiconductor substrate includes a cell region and a termination region, the first trench is formed in the cell region, and the step of forming the first trench comprises: and forming a second trench in the termination region of the semiconductor substrate.
9. The method of manufacturing a trench power semiconductor device according to claim 8, wherein the step of forming the first oxidized portion comprises: and forming a first terminal oxidation part at the bottom and part of the side wall of the second groove.
10. The method of manufacturing a trench power semiconductor device according to claim 9, wherein the step of forming the second oxidized portion includes: and forming a second terminal oxide portion on the sidewall of the second trench not covered by the first terminal oxide portion.
11. The method of manufacturing a trench power semiconductor device of claim 10, wherein forming the shield gate comprises:
depositing a polysilicon material layer in the first groove and the second groove, wherein the polysilicon material layer in the second groove is used as a protection ring;
forming a patterned photoresist layer on the second trench to cover the guard ring in the second trench; and
and etching the polysilicon material layer of the unit area by taking the patterned photoresist layer as a mask so as to form the shielding gate in the unit area.
12. The method of manufacturing a trench power semiconductor device of claim 7, wherein forming the first trench in the semiconductor substrate comprises:
forming a patterned hard mask layer on the surface of the semiconductor substrate;
etching the exposed semiconductor substrate by using the patterned hard mask layer as a mask to form a shallow trench;
forming a thin oxide layer on the side wall and the bottom surface of the shallow trench;
forming a silicon nitride spacer on the thin oxide layer of the side wall of the shallow trench;
etching to remove the thin oxide layer on the bottom surface of the shallow trench by using the silicon nitride spacer as a mask; and
and etching the semiconductor substrate exposed from the bottom surface of the shallow trench by using the patterned hard mask layer and the silicon nitride spacer as masks to form the first trench.
13. The method of manufacturing a trench power semiconductor device according to claim 12, wherein the step of forming the first oxidized portion comprises:
a first oxidation reaction is performed to form the first oxidized portion on the sidewall and the bottom of the first trench except the silicon nitride spacer.
14. The method of manufacturing a trench power semiconductor device according to claim 13, wherein the step of forming the second oxidized portion includes:
removing the thin oxide layer, the patterned hard mask layer and the silicon nitride spacer to expose a portion of the sidewall of the first trench; and
a second oxidation reaction is performed to form the second oxidized portion.
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| Application Number | Priority Date | Filing Date | Title |
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| TW111111353 | 2022-03-25 | ||
| TW111111353A TWI838718B (en) | 2022-03-25 | Trench power semiconductor device and manufactureing method thereof |
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