TWM464821U - Semiconductor device and its terminal area structure - Google Patents

Description

Semiconductor device and its terminal area structure

The present invention relates to a semiconductor device and its termination region structure, and more particularly to a semiconductor device having a trench structure and its termination region structure.

Schottky diode is a semiconductor device composed of a metal and a semiconductor junction. Due to its low starting voltage and fast response speed, it is widely used in various electronic circuits, such as power conversion circuits. . The conventional Schottky diode structure comprises a high concentration doped semiconductor substrate, the material of which is usually a single crystal germanium; and a semiconductor layer as a cathode region, which has a lower concentration of a carrier having the same conductivity as the substrate described above. a hetero-material; and having a metal layer or a metal telluride layer formed on the lightly doped cathode region to form a Schottky barrier and constituting the anode of the diode.

Schottky diodes are characterized by high speed and require only a low forward bias to have a large forward current and a short reverse recovery time. However, when the reverse bias voltage continues to increase, there is a large leakage current (depending on the work function of the metal and the doping concentration of the semiconductor). Therefore, the trench type Schottky barrier diode of the prior art is to pinch off the reverse leakage current by filling the trench with polysilicon or metal.

A conventional grooved Schottky diode can be found in U.S. Patent Application Serial No. 2010/0327,288. Figure 1 (a) shows the trench Schottky diode disclosed in the case. The device comprises: a semiconductor substrate 12 having a multi-ditch structure 11; a first mask layer 13 formed on a surface of the semiconductor substrate 12; and a gate oxide layer 14 formed on a surface of the multi-ditch structure 11 The gate oxide layer 14 protrudes from the surface of the semiconductor substrate 12; a polysilicon structure 15 is formed on the gate oxide layer 14, and the polysilicon structure 15 protrudes from the surface of the semiconductor substrate 12; a second mask layer 16 formed on the first mask layer 13 and a portion of the polysilicon structure 15; and a metal sputtering layer 17 formed on the second mask layer 16, the semiconductor substrate 12, and the polysilicon layer Structure 15 and a portion of the surface of the gate oxide layer 14.

In addition, the trench Schottky diode of FIG. 1(a) is formed by: providing a semiconductor substrate (12); forming a first mask layer (13) on the semiconductor substrate (12); The semiconductor substrate (12) is etched according to the first mask layer (13) to form a multi-ditch structure (11) in the semiconductor substrate (12); formed on the surface of the multi-ditch structure (11) a gate oxide layer (14); forming a polysilicon structure (15) on the gate oxide layer (14) and the first mask layer (13); etching the polysilicon structure (15) to The top surface and a portion of the first mask layer (13) are exposed; a second mask is formed on a portion of the polysilicon structure (15) and a portion of the first mask layer (13) a layer (16) for exposing a portion of the surface of the semiconductor substrate (12), the polysilicon structure (15) and the gate oxide layer (14); and the semiconductor on the second mask layer (16) Forming a metal sputter layer (17) on a portion of the substrate (12), the polysilicon structure (15), and the gate oxide layer (14); and etching the metal sputter layer (17) to Part of the second cover layer (16) The surface is exposed and the like.

However, in the termination region of the conventional trench Schottky diode, the polysilicon in the plurality of trenches is not electrically connected to the metal layer, so that the plurality of trenches in the reverse operation of the component The slots are all in a potential floating state, and the electric field distribution in the terminal region cannot be extended and dispersed, resulting in a strong electric field crowding, so that the breakdown voltage cannot be effectively increased for a higher power or voltage semiconductor device. There are still restrictions on its application. Therefore, how to design and fabricate a Schottky diode with high breakdown voltage and low reverse leakage current has become an urgent problem to be solved.

In view of the deficiencies of the prior art, the present invention proposes a joint trench structure that can be widely applied to trench type semiconductor devices. By conducting a portion or portions of adjacent trenches in the plurality of trenches, the electric field distribution in the semiconductor device changes, thereby improving current-voltage characteristics. Similarly, the characteristics of the semiconductor device can be further adjusted by changing the configuration of the connection trenches to suit the needs of different applications.

One aspect of the present invention is a termination region structure of a semiconductor device, comprising: a semiconductor layer; a plurality of trenches formed on a surface of the semiconductor layer; formed on a surface of the semiconductor layer for connecting adjacent ones of the plurality of trenches a first trench having a first trench and a second trench; a surface formed on the surface of the plurality of trenches, a surface of the bonding trench, and the semiconductor layer not forming the plurality of trenches or the connecting trench a first insulating layer on the surface; forming and filling the plurality of trenches having the first insulating layer on the surface and a conductive material (such as polysilicon or tungsten) in the first connecting trench, the first trench and the The conductive material filled in the second trench is turned on by the conductive material filled in the first connecting trench; at least a portion of the surface of the first insulating layer not contacting the conductive material and the conductive material are not covered a second insulating layer contacting the surface of the first insulating layer; and a metal layer covering at least a portion of the surface of the second insulating layer. In the first trench, the second insulating layer may be covered by the portion of the guide a surface of the electrically insulating material that is not in contact with the first insulating layer, and the metal layer covers a surface of the other portion of the electrically conductive material that is not in contact with the first insulating layer; and the other portion of the electrically conductive material covered by the metal layer is further A metal telluride layer or a Schottky metal layer may be formed. The first connecting trench can be further configured to be perpendicular to the first trench and the second trench, or perpendicular to a tangent to the first trench and a tangent to the second trench. The terminal region structure of the semiconductor device may further include a second connection trench for connecting the second trench and the third trench in the plurality of trenches, the third trench being adjacent to the second trench a trench; wherein the second connecting trench and the first connecting trench are staggered, that is, the two are not collinear. The second connecting trench in the terminal region structure of the semiconductor device may also be used to connect adjacent one of the third trench and the fourth trench in the plurality of trenches, and the first connecting trench and the The second joint groove is not electrically conductive. The terminal region structure of the semiconductor device can be applied to different types of semiconductor devices, such as Schottky diodes, metal oxide semiconductor field effect transistors, bipolar junction transistors, or insulated gate bipolar transistors.

Another aspect of the present invention is a semiconductor device having an active region and a termination region, including a semiconductor layer; a plurality of trenches formed on a surface of the semiconductor layer; formed on a surface of the semiconductor layer and located in the termination region, connected a connecting trench of two adjacent trenches in the plurality of trenches; a first insulating layer formed on the surface of the plurality of trenches and the connecting trenches in the active region, the upper edge of which is lower than the semiconductor layer is not formed a surface of the trench formed in the termination region, a surface of the plurality of trenches, a surface of the bonding trench, and a surface of the semiconductor layer not forming the plurality of trenches or the bonding trench; a conductive material formed on the surface a plurality of trenches and the first insulating layer in the connecting trench and completely covering the bottom of the plurality of trenches and the bottom of the connecting trench; a second insulating layer covering at least a portion of the first insulating layer in the termination region a surface not contacting the conductive material and a portion of the conductive material not contacting the surface of the first insulating layer; and a metal layer covering at least a portion of the surface of the active region and the second insulating layer.

Another aspect of the present invention is a Schottky diode having an active region and a termination region, comprising: a semiconductor layer; a plurality of trenches formed on a surface of the semiconductor layer; formed on a surface of the semiconductor layer and a connecting trench located in the terminal region for connecting one of the first trench and the second trench in the plurality of trenches; forming at least part of a surface of the plurality of trenches, at least a portion of the connecting trench a first insulating layer on the surface and the semiconductor layer in the terminal region where the plurality of trenches or the surface of the connecting trench is not formed; the plurality of trenches having the first insulating layer formed on the surface and the first connecting trench a conductive material (for example, polysilicon or tungsten), wherein the conductive material filled in the first trench and the second trench is turned on by the conductive material filled in the first connecting trench; At least a portion of the first insulating layer not contacting the surface of the conductive material and a portion of the second insulating layer not contacting the surface of the first insulating layer; and covering at least the active region and the second insulating layer Partial surface metal . In the first trench, the second insulating layer may cover a surface of the conductive material not in contact with the first insulating layer, and the metal layer covers other surfaces of the conductive material not in contact with the first insulating layer . In addition, in the active region, the semiconductor layer and the conductive material are not in contact with the surface of the first insulating layer, and a metal telluride layer or a Schottky metal layer may be further formed.

Another aspect of the present invention is a method for fabricating a Schottky diode, comprising the steps of: (1) forming a trench structure on a semiconductor layer, the trench structure comprising a plurality of trenches and connecting the phase of the plurality of trenches a plurality of adjacent trenches connecting the trenches; (2) forming a first insulating layer, the first insulating layer covering a surface of the trench structure and the semiconductor layer not forming the trench structure a surface; (3) forming a conductive material in the trench structure covering the first insulating layer to fill the trench structure; (4) forming a second insulating layer for covering the first insulating layer not contacting the The surface of the conductive material and the conductive material are not in contact with the surface of the first insulating layer; (5) removing portions of the second and first insulating layers such that the upper edge of the conductive material and the semiconductor layer are not grooved (6) forming a metal telluride layer or a Schottky metal layer at least on the exposed upper surface of the conductive material and the surface of the semiconductor layer where the trench region is not formed; (7) forming a first metal layer And covering the region of the second and first insulating layers and a portion of the second insulating layer; and (8) forming a protective layer to cover a portion of the first metal layer and a portion of the second insulating layer . The step of forming the trench structure may further include: (1A) forming a hard mask layer on the semiconductor layer; (1B) patterning the hard mask layer to expose a portion of the semiconductor layer to form the trench structure; (1C) forming a trench structure by a region that is not covered by the hard mask layer by dry etching; and (1D) removing the patterned hard mask layer. The step of patterning the hard mask layer may further include using light lithography and dry etching. In the above step of forming the first insulating layer, a cerium oxide layer may be formed by thermal oxidation or chemical vapor deposition. The step of forming the conductive material may further include: (3A) depositing the polysilicon by chemical vapor deposition, covering the first insulating layer and filling the trench structure having the first insulating layer on a surface; and (3B) removing a portion of the polysilicon by dry etching, exposing an upper edge of the first insulating layer and an upper edge of the polysilicon filling the trench structure; wherein after removing the second and first insulating layers, The upper edge of the first insulating layer in the trench in the active region may be lower than the surface of the semiconductor layer where the trench is not formed. The step of forming a metal telluride layer on the exposed upper surface of the conductive material and the surface of the semiconductor layer not forming the trench region may include: (6A) removing the portion of the second and first insulating layers Forming a second metal layer in the domain; (6B) reacting the upper edge of the conductive material and the surface of the semiconductor layer not forming the trench region with the second metal layer by thermal annealing to form the metal telluride And removing (6C) the second metal layer. In the above method for manufacturing a Schottky diode, the upper edge of the first insulating layer in the trench in the region of the second insulating layer and the region of the first insulating layer is removed, which may be lower than the semiconductor The layer does not form a surface of the trench portion; further, after the step (5) removes the portion of the first insulating layer and the second insulating layer, the boundary of the first insulating layer and the second insulating layer that are not removed may be An upper edge of the conductive material located in one of the plurality of trenches.

Based on the above intention of the present invention, the semiconductor device can be made to have a higher breakdown voltage than the prior art by adding the termination region structure of the connection trench. The specific implementation of this creation is described later.

11‧‧‧Multi-ditch structure

12‧‧‧Semiconductor substrate

13‧‧‧First mask layer

14‧‧‧ gate oxide layer

15‧‧‧ Polycrystalline structure

16‧‧‧Second mask

17‧‧‧Metal Sputter

34, 34a, 34b, 34c, 221~223‧‧‧ trench

31‧‧‧Active Area

32‧‧‧ Terminal Area

33‧‧‧Semiconductor layer

37‧‧‧Electrical materials

38,67‧‧‧metal layer

39,68‧‧‧Protective layer

61‧‧‧ epitaxial layer

62‧‧‧ hard cover

65‧‧‧Polysilicon

66‧‧‧metal telluride layer (Schottky metal layer)

211~216,351,352‧‧‧Link groove

361,641‧‧‧first insulation

362,642‧‧‧Second insulation

631, 632, 633, 634 ‧ ‧ photoresist layer

1(a) is a schematic cross-sectional view of a conventional trench Schottky diode, and FIG. 1(b) is a top plan view of a portion of the trench structure.

2(a) is a schematic top view of a portion of a trench and a connecting trench of a Schottky diode according to the present invention; FIG. 2(b) is a partial trench of another Schottky diode of the present invention. FIG. 2(c) is a top view of a portion of the trench and the connecting trench of another Schottky diode proposed by the present invention; FIG. 2(d) is another schematic of the present invention. Partial trench and joint trench of base diode A bird's eye view.

3(a) to (c) are schematic cross-sectional views of different positions of the Schottky diode proposed in the present application.

4(a) is a schematic diagram showing the electric field distribution of a conventional Schottky diode, and FIG. 4(b) is a schematic diagram showing the electric field distribution of the Schottky diode proposed in the present invention.

FIG. 5 is a schematic diagram showing current-voltage curves of a Schottky diode and a conventional Schottky diode according to the present invention.

Fig. 6(a)~(z) are schematic diagrams showing the manufacturing process of the Schottky diode proposed in the creation.

Illustrative of the specific embodiments of the present invention will be described below in conjunction with the drawings. The structure of the components disclosed in the drawings is for illustrative purposes only, and does not represent the size or proportion of the actual structure, nor does it limit the overall composition of the actual components.

Corresponding to the conventional Schottky diode structure of FIG. 1(a), FIG. 1(b) corresponds to a top view of the trench portion of the termination region, and can also be understood as a part of the light used in the manufacturing process of the semiconductor device. Cover pattern. One specific example of the present invention is a terminal region of a semiconductor device having a connection trench, and some trenches in a conventional trench semiconductor device are turned on by using a connection trench, and a top view of a terminal region portion thereof can be as shown in FIG. 2 ( a)~(d). Similarly, Figures 2(a)-(d) can also be understood as the reticle pattern of the groove portion. The difference between Fig. 2(a) and (d) and Fig. 1(b) is that the connection trenches with different configurations are added, and the corresponding components will also have different voltage-currents depending on the difference of the configuration of the connection trenches. characteristic. 2(a), the plurality of connection trenches 211 are used to turn on the innermost trenches 221 and trenches 222 of the termination region; after the trenches and the trenches are filled with conductive material, the trenches 221 , 222 and the joint groove 211 The potential of the conductive material inside will be the same. However, the joining grooves can also continue to extend outwardly. As shown in the pattern of FIG. 2( b ), a plurality of connecting trenches 212 are further included for connecting the trenches 222 and the trenches 223 . The connecting trenches 211 and the connecting trenches 212 can be correspondingly disposed on a straight line. As shown in Fig. 2(b), they are not collinearly staggered, and the relative positions of the two will correspond to different electric field distributions in the semiconductor device, that is, different current-voltage curves. In addition, the connection trench can also be configured in a partition as shown in FIG. 2(c). 2(c), in addition to the plurality of connecting grooves 211 corresponding to FIG. 2(a), for connecting the innermost two grooves, further comprising a plurality of connecting grooves 213, 214, 215, and 216 for the outermost side The five grooves are turned on. 2(d) is based on FIG. 2(b), and further, a plurality of connecting grooves 214, 215, and 216 are provided to connect the four outermost grooves. In other words, the structure disclosed in Figures 2(c) and (d) has two sets of trenches, and the same set of trenches are electrically connected to each other, and different sets of trenches are not turned on. In other words, after filling the conductive material, the trenches of the same group will be equipotential. Based on the same concept, more sets of trench designs can be extended.

The term "conduction" as used herein refers to the fabrication of a trench structure in which two or more trenches are connected and connected; when the trench is filled with a conductive material, the effect is electrically conductive. . However, the type or size of the connection grooves 211 to 216 is not limited to those shown in FIGS. 2(a) to (d), and those skilled in the art may select the appropriate ones depending on the requirements of the component performance or the process conditions. Type and size. For example, the connecting grooves disclosed in FIGS. 2(a) to (d) are perpendicular to the respective plural grooves or perpendicular to the tangent of the bending of each of the plurality of grooves, but this is merely an illustration of the present creation, and is not a connecting groove. The limitations of the structural features of the trough. On the other hand, the conduction between the trenches is not limited to the use of the connection trenches. For example, in the conventional structure of FIG. 1(a), the second mask layer 16 can be opened and the metal sputter layer 17 can be Fill it up When the holes are opened, the polysilicon structure 15 in the partial trenches is also turned on by the metal sputtering layer 17. For those of ordinary skill in the field of semiconductor devices, the proposed connection trenches can be applied to various semiconductor devices having trench terminal regions, such as Schottky diodes, metal oxide semiconductor field effect transistors (MOSFETs). ), bipolar junction transistor (BJT), or insulated gate bipolar transistor (IGBT).

Taking the trench structure shown in FIG. 2(b) as an example, FIG. 3 discloses the cross-sectional structure of the corresponding Schottky diode. First, Fig. 3(a) is equivalent to the cross-sectional structure along line A-A' of Fig. 2(b). The groove portion shown in Fig. 3(a) and the conventional structure are due to the position of the line segment A-A'. Approximate [see Figure 1 (a)]. However, Fig. 3(b) and Fig. 3(c) correspond to the cross-sectional structure of the line segment B-B' and the line segment C-C' in Fig. 2(b), respectively. It can be clearly seen from Fig. 3(b) that the bonding trenches are electrically connected to the trenches 221 and 222 along the line segment B-B', and in Fig. 3(b), it is apparent that the bonding trenches are turned on 222 and 223 along the line segment B-B'. .

Another specific example of the present invention is a Schottky diode structure, as shown in FIG. 3(a), the structure of which can be divided into an active region 31 and a termination region 32, and includes a semiconductor layer 33 (which can be, for example, lower) A doped concentration epitaxial layer) and a plurality of trenches 34, and the boundary between the active region 31 and the termination region 32 is located on a sidewall of one of the trenches. Referring to FIGS. 3(b) and 3(c), the present embodiment includes a plurality of connection trenches 351 and 352 formed on the surface of the semiconductor layer 33 and located in the termination region 32 for connecting the plurality of trenches 34. Adjacent to the two grooves. The connection groove 351 of FIG. 3(b) corresponds to the connection groove 211 of FIG. 2(b), and the connection groove 352 of FIG. 3(c) corresponds to the connection groove 212 of FIG. 2(b). The first insulating layer 361 is formed on at least a part of the surface of the plurality of trenches 34, the plurality of connection trenches 351, 352, and the surface of the termination region 32 where the semiconductor layer 33 is not formed with a trench. Please refer to Figure 6(p) for a description of the "partial surface" here. It is meant that in the trench of the active region, the uppermost edge of the first insulating layer 641 is lower than the original surface of the epitaxial layer 61 where the trench is not formed; in other words, the first insulating layer 641 does not completely cover all surfaces of each trench. However, this feature is merely an illustration of the present invention, and may vary depending on the component structure and process characteristics, and it is also possible that the first insulating layer 641 completely covers all surfaces of each trench. The conductive material 37 is formed in the plurality of trenches 34 and the plurality of connection trenches 351 and 352. The conductive material 37 filled in the plurality of trenches 351 and 352 can electrically conduct the conductive material in the adjacent trenches. Referring again to FIG. 6(p), the polysilicon 65 fills the space inside the first insulating layer 641 in the trench. In the prior art, whether the conductive material fills the trench may vary depending on the component structure and the process characteristics; for example, when the trench width (relative to the depth) is large, the conductive material may not fill the inside of the first insulating layer. The space, that is, the central depression of the conductive material is too large, resulting in the first insulating layer not completely covering the bottom of the trench. However, based on the main idea of the present invention, if the conductive material does not completely cover the first insulating layer at the bottom of the trench, the conductive material in the same trench may not be turned on, and the connecting trench may not turn on the adjacent trench. In addition, in the termination region 32, the second insulating layer 362 covers the upper edge surface of the first insulating layer 361 and the surface of the upper edge of the conductive material 37. In the active region 31, a metal telluride layer is formed on the surface of the upper edge of the semiconductor layer 33 and the upper surface of the conductive material 37, and may also be formed on the surface of the first insulating layer 361 which is not exposed to the semiconductor layer 33 and the conductive material 37. (Because of the small proportion, not shown in Figure 3 (a) ~ (c), please refer to Figure 6 (q) component number 65). The metal layer 38 covers the surface of the metal telluride layer and a portion of the surface of the second insulating layer 362, and the outermost layer may cover the protective layer 39.

In the structures disclosed in FIGS. 3(a) to (c), FIG. 6(q) and the preceding paragraph, the metal telluride layer is used to form a Schottky barrier, and a Schottky metal layer may be used instead. The material may be, for example, aluminum or molybdenum; and the metal layer 38 functions as a contact electrode. However, this is merely an illustration of the Schottky barrier of this creation. If a suitable material, such as aluminum, is used, the metal layer 38 can serve as both an electrode and a Schottky barrier. At this time, the metal germanide layer or the Schottky metal layer is not required in the active region, and the metal layer 38 can be directly formed on the surface of the conductive material not contacting the first insulating layer, the surface of the first insulating layer not contacting the conductive material, and the semiconductor The layer does not form a trench or a surface that joins the trench.

In addition, in the specific example of the present invention shown in FIGS. 3(a) to (c), the innermost trench adjacent to the termination region in the active region is the trench 34a, that is, the conductive material 37 of each trench in the active region. The metal layer 38 is electrically connected to the conductive material 37 in the trench 34a of the termination region, and the trench 34a is electrically connected to the trenches 34b, 34c by the connection trenches 351, 352, so that the potential of the conductive material in the trench 34a The potentials of the conductive materials in the associated trenches 34b, 34c are the same. In contrast, in the terminal region structure shown in FIGS. 3(a) to (c), the trenches other than the trenches 34a, 34b, and 34c are not electrically connected to each other, and the conductive material 37 therein still has a floating potential.

The Schottky diode structure proposed in the present invention can change the electric field distribution in the element by the arrangement of the connection grooves, and has the effect of improving electrical properties. 4(a) and 4(b) show the electric field distribution of the conventional Schottky diode and the Schottky diode of the present invention, and the difference between the two can be seen. 4(a) corresponds to the conventional Schottky diode structure, and FIG. 4(b) is a structure in which the three trenches of the terminal region adjacent to the active region are turned on based on the main purpose of the present invention. It can be seen from the comparison between Fig. 4(a) and Fig. 4(b) that the electric field distribution of the conventional structure is concentrated, and the structure proposed by the present invention can extend the electric field distribution so that the electric field is not excessively concentrated. Active area. Since the electric field intensity is more concentrated, the voltage breakdown or breakdown is more likely to occur, so the structure proposed by the present invention can have higher withstand voltage, that is, a high breakdown when reverse bias is applied. Voltage. Based on the above description, FIG. 5 is a voltage-current curve simulation comparison between the Schottky diode of the present invention and the conventional Schottky diode. It can be seen that the Schottky diode of this creation does have a significantly increased breakdown voltage. The main purpose of the present invention is to turn on a part or a plurality of trenches in a conventional trench type semiconductor device, thereby dispersing the electric field intensity of the active region; and the feature is not limited to the above-described trench Schottky diode. It can be applied to other semiconductor devices having similar principles and structures, such as diodes or transistors.

Another specific example of the present invention is a method for producing a Schottky diode. The structure formed in each step is as shown in Figs. 6(a) to (z), and will be described below in order. 6(a) to (z) are cross-sectional views, which are the same as those of FIG. 3(a) (Fig. 2(b) along line A-A'), so it is not as shown in Fig. 3 ( b) or (c) may exhibit a cross-sectional structure of the joint grooves 351, 352. However, those skilled in the art will fully understand and implement the following description by referring to the top view of the trench structure disclosed in FIGS. 2(a) to (d).

As shown in FIG. 6(a), a lower doping concentration epitaxial layer 61 is first formed on a highly doped germanium substrate (not shown), and the material thereof may be, for example, an N-type single crystal germanium. And the thickness needs to be able to form a trench structure in a subsequent step, for example, about 1 to 60 micrometers (μm).

As shown in FIG. 6(b), a hard mask layer 62 is formed on the epitaxial layer 61. The material of the hard mask layer 62 may be, for example, hafnium oxide (SiO ₂ ). Thermal oxidation or chemical vapor deposition. The main function of the hard mask layer 62 is to shield the non-trench regions when subsequently etching the trenches, so the thickness depends on the etching depth required for the trenches, and the epitaxial layer 61 and the hard mask layer 62 are different in the etching process. The etch rate ratio of the material.

In order to form the hard mask layer 62 into a desired pattern, Figures 6(c) to (f) are used to light micro- The process of photo lithography and dry etch is not limited to the process. First, a photo resist layer 631 is applied on the hard mask layer 62 (FIG. 6(c)); secondly, a portion of the photoresist layer 631 is removed by exposure, development, etc. to form a desired pattern (FIG. 6 (FIG. 6) d)]; then etching is performed, for example, dry etching may be employed, and substantially the same pattern is formed on the hard mask layer 62 according to the pattern of the photoresist layer 631 [FIG. 6(e)]; after the remaining photoresist layer 631 is removed, The hard mask layer 62 after patterning as shown in Fig. 6(f) can be obtained. Referring to the foregoing description, the Schottky diode structure proposed in the present invention has a plurality of joint trenches, so that in the exposure step of forming the structure of FIG. 6(d), the mask pattern used in the trench portion of the termination region can be as Figure 2 (a) ~ (d). Taking the positive photoresist as an example, the groove structure in FIGS. 2(a) to (d) is the light transmitting portion in the reticle.

The pattern of the hard mask layer 62 is used to form a trench structure in the epitaxial layer 61 as shown in FIG. 6(g). The etching process used herein may use, for example, a dry etching which is preferably anisotropic, and after forming a trench on the surface of the epitaxial layer 61 not covered by the hard mask layer 62, the remaining hard mask layer 62 is removed. An epitaxial layer 61 having a trench structure as shown in Fig. 6(h) is obtained. The depth of the trench structure can generally be, for example, about 0.5 to 30 microns.

After the epitaxial layer 61 is formed, the first insulating layer 641 can be formed thereon by, for example, but not limited to, thermal oxidation or chemical vapor deposition. As shown in FIG. 6(i), the first insulating layer 641 completely covers the surface of each trench of the epitaxial layer 61 and the original surface where the trench is not formed, and the thickness thereof may be, for example, about 0.08 to 1 micrometer, and generally the trench depth is The thickness of the first insulating layer 641 is deeper. Different from the prior art, the first insulating layer 641 formed in this step is equivalent to simultaneously forming the gate oxide layer 43 and the first mask layer A1 in FIG. 1(a).

After the first insulating layer 641 is formed, then polycrystalline is formed in the trench 矽; The materials that can be used here are not limited to polysilicon, and tungsten or other conductive materials can also be used. 6(j) is a polycrystalline germanium 65 formed on the first insulating layer 641 by chemical vapor deposition. By virtue of the characteristics of chemical vapor deposition, the polysilicon 65 can fill the trench and form a film of a certain thickness over the entire substrate. The thickness of the upper film layer generally depends on the width of the trench, and the wider the trench, the thicker the film layer above the desired polysilicon 65. Next, the polysilicon 65 over the substrate is etched back by dry etching, and the upper polysilicon film layer is removed to expose the upper edge surface of the first insulating layer 641 (ie, not part of the inner surface of the trench), such as Figure 6 (k). The degree of filling of the polysilicon 65 in the trench depends on the different process and structure design. In Fig. 6(k), the polycrystalline germanium fills the space surrounded by the first insulating layer. As described above, since the present invention connects the adjacent trenches in the termination region by the connection trenches. If the trench is wider or shallower, the reverse etching step may completely remove the polysilicon in the central portion, and the first insulating layer at the bottom of the trench is exposed; at this time, the polysilicon in the same trench itself is not fully turned on. The formation of the joint groove also prevents the adjacent two grooves from being completely turned on. Therefore, in accordance with the teachings of the present invention, the reverse etching step herein must retain the polysilicon at least filling the bottom of the trench, that is, completely covering the first insulating layer at the bottom of the trench.

After the foregoing steps, a second insulating layer 642 is formed on the substrate. For example, a ceria layer can be formed by chemical vapor deposition, as shown in FIG. 6(1).

6(m) to (p) are steps of removing a portion of the first insulating layer 641 and the second insulating layer 642 for forming an opening of the active region. First, a photoresist layer 632 is applied on the second insulating layer 642 (Fig. 6(m)), and the photoresist layer 632 in the open region is removed after exposure and development, etc. (Fig. 6(n)); secondly by The photoresist layer 632 which is not removed serves as a mask, and the first insulating layer 641 and the second insulating layer 642 of the opening portion are removed by etching (FIG. 6(o)). Among them, For example, dry etching or other etching methods are used. In addition, FIG. 6(o) also discloses that the portion of the first insulating layer 641 in the trench is not removed, so that the first insulating layer 641 in the trench of the active region has the function of a gate oxide layer. After removing the remaining photoresist layer 632, the structure of the cross section is as shown in Fig. 6(p).

After completing the structure of Fig. 6(p), the next step is to form a metal silicide layer 66 in the active region of the element, as shown in Fig. 6(q). First, a metal layer is formed in the active region. For example, a nickel or titanium film can be formed by evaporation or sputtering, and the metal and the surface of the epitaxial layer 61 are formed through a thermal annealing process. The trench portion) reacts with the upper surface of the polysilicon 65 in the trench, and a metal telluride layer 66 is formed at the junction, and the junction of the metal telluride layer 66 and the epitaxial layer 61 forms a Schottky barrier (Schottky Barrier). However, in an actual process, a metal telluride layer may also be formed on the surface of the first insulating layer 641 not in contact with the polysilicon 65 or the epitaxial layer 61. As previously mentioned, the metal telluride layer 66 can also be replaced with a Schottky metal layer, for example, an aluminum film or a molybdenum film can be formed to cover at least the active region. In addition, it is also possible to omit this step and directly form a Schottky barrier in the subsequent step in the junction of the metal layer 67 and the epitaxial layer 61.

6(r) to (v) are steps of forming a metal electrode structure. First, a metal layer 67 is deposited on the surface of the entire device (Fig. 6(r)), followed by coating the photoresist layer 633 (Fig. 6(s)), and then removing the peripheral portion of the photoresist layer 633 by exposure and development, etc. The unremoved photoresist layer 633 covers the active region and the termination region (Fig. 6(t)), and then the metal layer 67 is etched under the shielding of the photoresist, that is, the metal layer 67 outside the component region is removed. 6(u)], finally removing the remaining photoresist layer 633 [Fig. 6(v)]. The metal layer 67 can be formed as an electrode and a Schottky barrier can be formed by using a suitable material (for example, aluminum), so that the aforementioned metal germanide layer can be omitted. Or Schottky metal layer.

Finally, Figures 6(w)~(z) show the steps of forming a protective layer structure. First, a protective layer 68 (Fig. 6(w)) is deposited on the surface of the entire device, and for example, ceria or tantalum nitride can be used as a material; then the photoresist layer 634 is coated and exposed to the active region by exposure and development, etc. An opening is formed (Fig. 6(x)); then the protective layer 68 is etched to remove the protective layer 68 over the active region that is not covered by the photoresist to expose the electrode as an ohmic contact (Fig. 6(y)); Except for the remaining photoresist layer 634 (Fig. 6(z)). Thus far, the basic structure of the semiconductor device of one specific example of the present creation is completed.

The specific examples described above are merely illustrative of the embodiments of the present invention and are not exhaustive of all possible variations. The scope of the claims of the applicant is set forth in the scope of the patent application, and the scope of the claims and the scope of the claims are covered by the scope of the patent, and the contents of the foregoing inventions or drawings are not to be construed as limiting the scope of the patent application. .

211,213,214,215,216‧‧‧Link trench

Claims (13)

A termination region structure of a semiconductor device, comprising: a semiconductor layer; a plurality of trenches formed on a surface of the semiconductor layer; a first connection trench formed on a surface of the semiconductor layer for connecting the phase of the plurality of trenches a first trench and a second trench; a first insulating layer formed on a surface of the plurality of trenches, a surface of the bonding trench, and the semiconductor layer not forming the plurality of trenches or the connecting trench a surface of the trench; the conductive material is formed on the surface of the plurality of trenches having the first insulating layer and the first interconnecting trench, and the conductive material in the first trench and the second trench is formed by the conductive material The conductive material in the first connection trench is turned on; a second insulating layer covers at least a portion of the surface of the first insulating layer not contacting the conductive material and a portion of the conductive material not contacting the surface of the first insulating layer; A metal layer covering at least a portion of the surface of the second insulating layer. The terminal region structure of the semiconductor device according to claim 1, wherein the second insulating layer covers a surface of the first insulating layer that is not in contact with the first insulating layer, and the metal layer Covering other portions of the surface of the conductive material that are not in contact with the first insulating layer. The terminal region structure of the semiconductor device according to claim 2, wherein the other portion of the conductive material covered by the metal layer is further formed with a metal telluride layer or a Schottky metal layer. The termination structure of the semiconductor device of claim 1, wherein the first connection trench is perpendicular to the first trench and the second trench, or a tangent to the first trench and the first two The tangent of the groove is vertical. The termination structure of the semiconductor device of claim 1, further comprising a second connection trench for connecting the second trench and the third trench in the plurality of trenches, the third The trench is adjacent to the second trench. The termination structure of the semiconductor device of claim 5, wherein the second connection trench is not collinear with the first connection trench. The termination structure of the semiconductor device of claim 1, further comprising a second connection trench for connecting adjacent one of the third trench and the fourth trench. The terminal region structure of the semiconductor device according to claim 1, wherein the semiconductor device is a Schottky diode, a metal oxide semiconductor field effect transistor, a bipolar junction transistor, or a Insulated gate bipolar transistor. A semiconductor device having an active region and a termination region, comprising: a semiconductor layer; a plurality of trenches formed on a surface of the semiconductor layer; a bonding trench formed on a surface of the semiconductor layer and located in the termination region, And connecting a first trench and a second trench adjacent to the plurality of trenches; a first insulating layer is formed on the surface of the plurality of trenches and the connecting trench in the active region, and The surface of the plurality of trenches or the connecting trench is not formed on the semiconductor layer, and the first insulating layer is formed on the surface of the plurality of trenches, the surface of the connecting trench, and the semiconductor layer in the termination region The surface of the plurality of trenches or the connecting trench is not formed; a conductive material is formed on the surface of the plurality of trenches having the first insulating layer and the connecting trench, and completely covers the bottom of the plurality of trenches and the connecting trench a first insulating layer at the bottom of the groove; a second insulating layer covering at least a portion of the surface of the first insulating layer not contacting the conductive material and a portion of the conductive material not contacting the surface of the first insulating layer; and a metal layer covering at least the active a portion of the surface of the second insulating layer. A Schottky diode having an active region and a termination region, comprising: a semiconductor layer; a plurality of trenches formed on a surface of the semiconductor layer; a bonding trench formed on a surface of the semiconductor layer and located at the surface a terminal region for connecting one of the first trenches and a second trench adjacent to the plurality of trenches; a first insulating layer formed on at least a portion of the surface of the plurality of trenches, at least a portion of the bonding trenches The surface of the semiconductor layer does not form the surface of the plurality of trenches or the connecting trench; the conductive material is formed on the surface of the plurality of trenches having the first insulating layer and the connecting trench, and the The conductive material in the first trench and the second trench is electrically connected by the conductive material in the connecting trench; a second insulating layer covering at least a portion of the first insulating layer in the termination region is not in contact The surface of the conductive material and a portion of the conductive material are not in contact with the surface of the first insulating layer; and a metal layer covering at least a portion of the surface of the active region and the second insulating layer. The Schottky diode according to claim 10, wherein in the first trench, the second insulating layer covers a surface of the conductive material not in contact with the first insulating layer, and the metal layer Covering other portions of the surface of the conductive material that are not in contact with the first insulating layer. The Schottky diode according to claim 10, wherein the conductive material is polycrystalline germanium or tungsten. The Schottky diode according to claim 10, further comprising a metal telluride layer or a Schottky metal layer, at least formed in the active region, the semiconductor layer and the conductive material not contacting the first The surface of an insulating layer.