CN203277389U - Semiconductor device - Google Patents
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- CN203277389U CN203277389U CN 201320300434 CN201320300434U CN203277389U CN 203277389 U CN203277389 U CN 203277389U CN 201320300434 CN201320300434 CN 201320300434 CN 201320300434 U CN201320300434 U CN 201320300434U CN 203277389 U CN203277389 U CN 203277389U
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Abstract
The utility model discloses a semiconductor device. The semiconductor device comprises a substrate, a first fin-shaped structure, an electric contact structure, and a gate structure. The first fin-shaped structure comprises a horizontal fin-shaped structure extending along a first direction, and a vertical fin-shaped structure extending along a second direction. The substrate is defined with a first area and a second area. Part sections of the horizontal fin-shaped structure and the vertical fin-shaped structure are disposed in a first region, and the electric contact structure directly covers the horizontal fin-shaped structure and the vertical fin-shaped structure in the first region. The gate structure portion is overlapped with the horizontal fin-shaped structure in a second region.
Description
Technical field
The utility model relates to a kind of field of semiconductor device, particularly relates to structure in a kind of semiconductor device trap bonding pad and preparation method thereof.
Background technology
Along with field-effect transistor (field effect transistors, FETs) component size is dwindled constantly, the development of existing plane formula (planar) field effect transistor element has faced the limit on manufacture craft.In order to overcome the manufacture craft restriction, field effect transistor element with on-plane surface (non-planar), for example fin-shaped field-effect transistor (fin field effect transistor, FinFET) element replaces the flat crystal tube elements has become present mainstream development trend.
In the manufacture craft generation of present inferior optical lithography characteristic dimension (sub-lithographic feature), generally pass through sidewall design transfer (sidewall image transfer, SIT) technology to form required fin structure.In general, the execution mode of sidewall design transfer technology is normally prior to forming a plurality of sacrificial pattern on substrate.Then utilize deposition and etching process, form respectively a clearance wall in the sidewall of each sacrificial pattern.And after removing those sacrificial pattern, continue to utilize clearance wall as the etching mask of substrate, further with the design transfer of each clearance wall to substrate, forming many fin structures arranged of flat shape each other, thereby define shape and the width of transistor unit charge carrier passage.Yet the surface area that fin structure is less has also limited the contact area between itself and electric contact structure, particularly limited the position in the trap bonding pad fin structure and the contact area between electric contact structure.Because resistance value and contact area present inverse ratio, this structure can make the significant voltage drop of generation of interfaces between fin structure/electric contact structure in the trap bonding pad, and is unfavorable for the electrical performance of transistor unit.
Therefore, structure of the semiconductor device of wanting a kind of Improvement type of still needing and preparation method thereof is to overcome the too high problem of contact resistance value in above-mentioned trap bonding pad.
The utility model content
For achieving the above object, structure that provides by a kind of semiconductor device and preparation method thereof is provided the purpose of this utility model, to improve disappearance of the prior art.
According to an embodiment of the present utility model, provide a kind of semiconductor device.Semiconductor device comprises substrate, the first fin structure, electric contact structure and grid structure, and wherein the first fin structure comprises the horizontal fin structure that extends along first direction, and the vertical fin shaped structure of extending along second direction.On substrate, definition has a first area and a second area, and the part section of horizontal fin structure and vertical fin shaped structure are arranged in the first area.Electric contact structure directly covers horizontal fin structure and the vertical fin shaped structure in the first area, and grid structure partially overlaps the horizontal fin structure in second area.
Vertical this second direction of this first direction.This first fin structure is a ring-type (loop) structure.This first fin structure is one to have the circulus of opening.This first fin structure comprises the horizontal fin structure that another extends along this first direction, and wherein this electric contact structure can directly contact those horizontal fin structures and this vertical fin shaped structure in this first area.This horizontal fin structure and this vertical fin shaped structure have the two sides that are oppositely arranged separately, and this electric contact structure can directly contact those sides.This first area is a trap bonding pad (well pick-up region), and this second area is an active region (active region).
This semiconductor device comprises that separately one has the trap connecting doped area of the first conductivity type, is arranged in this trap bonding pad.This semiconductor device comprises that separately one has the source/drain doping region of the second conductivity type, is arranged in this active region.This source/drain doping region is arranged in this horizontal fin structure and is positioned at a side of this grid structure.This semiconductor device separately comprises a trap connecting doped area and one source/drain doping region, be arranged at respectively in this first area and in this second area, wherein this trap connecting doped area has one first conductivity type, this source/drain doping region has one second conductivity type, and this first conductivity type is different from this second conductivity type.
This semiconductor device separately comprises a masking structure, covers the part section of this horizontal fin structure, and wherein this electric contact structure can this masking structure of cover part.This semiconductor device separately comprises: the second fin structure, be arranged on this substrate, this second fin structure comprises at least one horizontal fin structure that extends along this first direction, and a vertical fin shaped structure of extending along this second direction, wherein the part section of those horizontal fin structures and those vertical fin shaped structures all are arranged in this first area.
Vertical this second direction of this first direction.This electric contact structure is those horizontal fin structures of contact and those vertical fin shaped structures directly.This horizontal fin structure and this vertical fin shaped structure have the two sides that are oppositely arranged separately, and this electric contact structure can directly contact those sides.
This semiconductor device separately comprises a trap connecting doped area and one source/drain doping region, be arranged at respectively in this first area and in this second area, wherein this source/drain doping region is arranged at least one those horizontal fin structures and is positioned at a side of this grid structure.This trap connecting doped area has the first conductivity type, and this source/drain doping region has the second conductivity type, and this first conductivity type is different from this second conductivity type.
According to another embodiment of the present utility model, a kind of manufacture method of semiconductor device is provided, comprise the following steps: at first, form sacrificial pattern on substrate, and form clearance wall in the surrounding sidewall of sacrificial pattern.Then shift the pattern to substrate of clearance wall, and form a fin structure, wherein fin structure comprises along the horizontal fin structure of first direction extension and the vertical fin shaped structure of extending along second direction.Then sequentially form grid structure, source/drain electrode structure and electric contact structure, wherein grid structure can be overlapping with the part of horizontal fin structure, source/drain electrode structure can be positioned at each side of grid structure separately, and electric contact structure can directly cover horizontal fin structure and vertical fin shaped structure.
Before forming this electric contact structure, this vertical fin shaped structure still can exist.
the utility model has the advantage of, all can be arranged at due to horizontal fin structure and vertical fin shaped structure in the trap bonding pad of semiconductor device, therefore be positioned at trap bonding pad electric contact structure except the horizontal fin structure of meeting covering, it also can cover the vertical fin shaped structure simultaneously, and have larger contact area and lower contact resistance, under this spline structure, if apply a voltage in the trap bonding pad, only can produce less pressure drop between electric contact structure and horizontal/vertical fin structure, therefore can smoothly voltage be applied to the trap doped region via the trap connecting doped area, and then the usefulness of having promoted semiconductor device.
Description of drawings
Fig. 1 to Fig. 7 has illustrated the manufacture method schematic diagram of the semiconductor device of the first preferred embodiment of the present utility model, wherein:
Fig. 1 has illustrated the utility model the first preferred embodiment at the initial structure vertical view of manufacture craft;
Fig. 2 is the generalized section that illustrates along Fig. 1 hatching line A-A ';
Fig. 3 has illustrated through the design transfer manufacture craft and the generalized section after forming shallow trench isolation;
Fig. 4 has illustrated the schematic top plan view after the formation grid structure;
Fig. 5 is the generalized section that illustrates along Fig. 4 hatching line A-A ';
Fig. 6 has illustrated the schematic top plan view after the formation electric contact structure;
Fig. 7 is the generalized section that illustrates along Fig. 6 Vertical Centre Line B-B ';
Fig. 8 has illustrated the schematic top plan view of the utility model first preferred embodiment the first change type;
Fig. 9 is the generalized section that illustrates along Fig. 8 Vertical Centre Line C-C ';
Figure 10 has illustrated the schematic top plan view of the utility model first preferred embodiment the second change type;
Figure 11 has illustrated the schematic top plan view of the utility model the first preferred embodiment the 3rd change type.
Symbol description
10 substrate 12 dielectric layers
14 sacrificial pattern 16 clearance walls
The 18 outstanding structures of pattern dielectric layer 20
22 shallow trench isolation layer 24 fin structure
24a first fin structure 24b the second fin structure
24c the 3rd fin structure 24d the 4th fin structure
The horizontal fin structure 26b of 26a vertical fin shaped structure
28 trap doped region 30 trap connecting doped areas
32 grid structure 34 sources/drain doping region
38 interlayer dielectric layers 40 contact the hole
42 electric contact structure 60 masking structures
62 dielectric layer 64 conductive layers
80b side, 80a side
D1 the first depth H 1 first height
R1 trap bonding pad R2 active region
W1 the first width W 2 second width
X first direction Y second direction
A-A ' hatching line B-B ' hatching line
C-C ' hatching line
Embodiment
Below, stated the embodiment of semiconductor device of the present utility model and preparation method thereof, can be implemented according to this utility model so that have in the art common operator.Those embodiments can with reference to corresponding accompanying drawing, make those accompanying drawings consist of the part of execution mode.Although it is as follows that embodiment of the present utility model discloses, yet it is not to limit the utility model, anyly is familiar with this operator, within not breaking away from spirit of the present utility model and category, when doing a little change and retouching.
At first as shown in Figures 1 and 2, Fig. 1 has illustrated at the initial structure vertical view of manufacture craft, the generalized section of Fig. 2 for illustrating along Fig. 1 hatching line A-A '.In this stage, a substrate 10 is provided, be provided with dielectric layer 12 and a plurality of sacrificial pattern 14 on it, and the surrounding sidewall of each sacrificial pattern 14 can be covered by the clearance wall 16 that an outward appearance presents ring-type (loop) all.Wherein, on substrate 10, definition has first area and second area, and it can correspond to respectively trap bonding pad R1 and the active region R2 of semiconductor device, but is not limited to this.Each sacrificial pattern 14 can be across trap bonding pad R1 and active region R2, has one first layout patterns 100 and make it overlook outward appearance, be for example the matrix layout along first direction X and second direction Y arrangement, and make the major axis of each sacrificial pattern 14 be parallel to first direction X, but be not limited to this.Better, each sacrificial pattern 14 can have one first width W 1, and each clearance wall 16 can have one second width W 2, and the first width W 1 can be greater than the second width W 2.
Above-mentioned substrate 10 is preferably semiconductor substrate, such as silicon substrate or SiGe (SiGe) substrate etc., and better silicon-on-insulator (silicon-on-insulator, the SOI) substrate of can not selecting of substrate 10.Dielectric layer 12 can be nitration case or oxide layer, for example silicon nitride, silica or other dielectric layers that is fit to, it can utilize thermal oxidation method, high density plasma CVD (high density plasma CVD, HDPCVD) or the manufacture craft such as inferior aumospheric pressure cvd (sub-atmosphere CVD, SACVD) and making.And according to other embodiment, can optionally not form dielectric layer on substrate.The composition of sacrificial pattern 14 can be semi-conducting material, polycrystalline silicon material for example, and its generation type can be by general deposition, light photoetching and etching process.And be subject to the manufacture craft ability of board, the minimum exposure limit of the optical lithography manufacture craft that the first width W 1 of each sacrificial pattern 14 can be carried out more than or equal to this board.The composition of each clearance wall 16 can be dielectric material, silicon nitride for example, and at first its generation type can comprise the following steps:, forms a dielectric materials layer (not shown), coats each sacrificial pattern 14 and covers dielectric layer 12 with orthodromic ground.Then, comprehensive ground etching (without the mode etching of mask) dielectric materials layer forms clearance wall 16 with the surrounding sidewall in each sacrificial pattern 14, and forms the outward appearance of overlooking as shown in Figure 1.Better, the composition of dielectric layer 12, sacrificial pattern 14 and clearance wall 16 each other can be not identical, makes each other to have certain etching selectivity.
With reference to shown in Figure 3, Fig. 3 has illustrated through the design transfer manufacture craft and the generalized section after forming shallow trench isolation, and it is roughly corresponding to the hatching line A-A ' in Fig. 1.As shown in Figures 2 and 3, remove the sacrificial pattern 14 in trap bonding pad R1 and active region R2 comprehensively, make only leaving gap wall 16 of dielectric layer 12 tops.Carry out afterwards a design transfer manufacture craft, for example sidewall design transfer (sidewall image transfer, SIT) manufacture craft is transferred to the surface of substrate 10 and forms a plurality of outstanding structures 20 with annular patterns with the annular patterns that each clearance wall 16 is defined.Wherein, each outstanding structure 20 all can have one first height H 1, and sequentially can stackingly there be pattern dielectric layer 18 and clearance wall 16 in its top.
Specifically, above-mentioned design transfer manufacture craft can comprise a plurality of etching steps, for instance: at first, utilize general etching process (dry ecthing or wet etching) to remove sacrificial pattern 14, only stay each clearance wall 16 on dielectric layer 12.Under this general etching process condition, the etch-rate of sacrificial pattern 14 can be greater than the etch-rate of clearance wall 16, so this etching process hardly can etched gap wall 16.Then, carry out one or multi-channel anisotropic etching manufacture craft (anisotropic etching process), with clearance wall 16 as etching mask, the downward substrate 10 of etching dielectric layer 12 and/or part sequentially.So far, just can be with the defined design transfer of clearance wall 16 to dielectric layer 12 and/or substrate 10.Should be noted at this, in full text, alleged " design transfer manufacture craft " comprises the concept of " sidewall design transfer manufacture craft ", that is " design transfer manufacture craft " can be considered to be the upperseat concept of " sidewall design transfer manufacture craft ".
Still as shown in Figure 3, and the collocation with reference to Fig. 2.After completing above-mentioned design transfer manufacture craft, can sequentially carry out dielectric layer deposition manufacture craft, dielectric layer flatening manufacture craft and dielectric layer reetching manufacture craft, form the shallow trench isolation layer 22 with one first depth D 1 with the bottom periphery in each outstanding structure 20.Therefore, the part section of each outstanding structure 20 can protrude from shallow trench isolation layer 22.This part section that protrudes from shallow trench isolation layer 22 also can b referred to as fin structure 24, and the height of fin structure 24 is approximately 300 to 400 dusts (angstroms).Should be noted at this, in above-mentioned design transfer manufacture craft, the etched reduction a littlely of the width of each clearance wall 16, therefore, the width of each corresponding fin structure 24 may be slightly less than the second width W 2 of original each clearance wall 16, but is not limited to this.
With reference to Fig. 4 and Fig. 5, wherein Fig. 4 has illustrated the schematic top plan view that forms after grid structure, and Fig. 5 is the generalized section that illustrates along Fig. 4 hatching line A-A '.As shown in Figure 4 and Figure 5, and the collocation with reference to Fig. 3.Then remove each clearance wall 16 and each pattern dielectric layer 18 of fin structure 24 tops fully, to expose each fin structure 24, for example expose the first fin structure 24a, the second fin structure 24b, the 3rd fin structure 24c and the 4th fin structure 24d, but be not limited to this.Better, each fin structure 24a, 24b, 24c, 24d all can be across trap bonding pad R1 and active region R2, and its U-shaped end is positioned at trap bonding pad R1.In other words, the end of each fin structure 24a, 24b, 24c, 24d can have two horizontal fin structure 26a and a vertical fin shaped structure 26b.
Then can carry out again other relevant semiconductor fabrication process.For example sequentially carry out the multiple tracks ion implantation technology, to have the first conductivity type in the interior formation of substrate 10, P type for example, trap doped region (well doped region) 28 and trap connecting doped area (well pick-up doped region) 30.Wherein, trap doped region 28 can be formed in trap bonding pad R1 and active region R2, and trap connecting doped area 30 only can be formed in trap bonding pad R1.Furthermore, trap connecting doped area 30 can be considered to be a heavily doped region that is arranged in trap doped region 28.In other words, the doping content of trap connecting doped area 30 can be higher than the doping content of trap doped region 28.In addition, before the ion implantation technology of dopant well also may be implemented in and forms each fin structure 24, its sequential point was not limited.Then, form at least one grid structure 32 in each active region R2, make each grid structure 32 directly to contact with a plurality of fin structures that are arranged in parallel 24 simultaneously, but the utility model is not limited to this.According to other embodiment, also can be provided with simultaneously a plurality of grid structures that are arranged in parallel in each active region.Better, arranging of each grid structure 32 can be as shown in Figure 4.Each grid structure 32 can envelope the part section of each fin structure 24, and it comprises cap rock (not shown) on a gate dielectric (scheming not formula), a grid conducting layer (scheming not formula) and to I haven't seen you for ages from bottom to up, and the sidewall of each grid structure 32 can be covered by the grid gap wall (not shown).Wherein, the material of above-mentioned gate dielectric, grid conducting layer and upper cap rock can correspond to respectively silica, polysilicon/metal material and silicon nitride, but is not limited to this.
Still as shown in Figure 4.Then can carry out coating and a photoetching making technique, to form a patterned mask layer (scheming not formula) on substrate 10, photoresist layer for example, the structure that it only can expose in each active region R2 for example exposes the interior shallow trench isolation layer 22 of active region R2, each fin structure 24, reaches each grid structure 32.Continue with under the covering of patterned mask layer, grid structure 32 and grid gap wall, carry out an ion implantation technology, with each self-forming source/drain doping region 34 in the fin structure 24 of the both sides of each grid structure 32.Wherein each source/drain doping region 34 can be considered to be a heavily doped region that is arranged in trap doped region 28, and the conductivity type of each source/drain doping region 34 can be different from the conductivity type of trap doped region 28 and trap connecting doped area 30.In other words, each source/drain doping region 34 of the present embodiment can have one second conductivity type, for example N-type.At last, remove patterned mask layer.
Should be noted at this, according to above-described embodiment, each fin structure 24a, 24b, 24c, 24d all can be across trap bonding pad R1 and active region R2.Yet according to other embodiment, the section that each fin structure is positioned between bonding pad and active region also can just be removed before or after forming the shallow trench isolation layer, can not have fin structure and make between bonding pad and active region.
With reference to Fig. 6 and Fig. 7, wherein Fig. 7 is the generalized section that illustrates along Fig. 6 Vertical Centre Line B-B '.As Fig. 6 and shown in Figure 7, after removing patterned mask layer, can carry out one the deposition manufacture craft, with dielectric layer 38 between comprehensive formation one deck on substrate 10.Continue so that interlayer dielectric layer 38 is implemented a planarization manufacture craft, make interlayer dielectric layer 38 cover each fin structure 24 and each grid structure 32 fully.Then, carry out an etching process, with in a plurality of contacts of the interior formation of interlayer dielectric layer 38 holes 40, and make the corresponding section of each fin structure 34 expose bottom for contact hole 40.In follow-up manufacture craft, exposure just can be used as for the contact area that is electrically connected to external circuit for each fin structure 34 in contact hole 40.
Should be noted at this, because the present embodiment discloses a normal-gate (gate first) manufacture craft, therefore can not replace the electric conducting material in grid structure 32 after forming interlayer dielectric layer 38, but be not limited to this.The utility model also can be applied to rear grid (gate last) manufacture craft, or claims replacement metal gate (replacement metal gate, RMG) manufacture craft, with the electric conducting material in the displacement grid structure.For instance, after forming interlayer dielectric layer, can continue to continue grinding this interlayer dielectric layer, until expose the top of grid structure, for example expose cap rock.Then carrying out at least one removes manufacture craft and metal deposition manufacture craft, to remove in grid structure grid conducting layer originally, polysilicon for example, and be replaced as the better metal material of conductivity, metals such as aluminium, tungsten or copper is to complete after this gate fabrication process.
Still as Fig. 6 and shown in Figure 7.After a plurality of contacts of the interior formation of interlayer dielectric layer 38 hole 40, then can contact the interior formation electric contact structure 42 in hole 40 in each, strip contact structures for example directly contact it and cover the part section of each fin structure 24.Of the present utility model one is characterised in that, be positioned at each electric contact structure 42 of trap bonding pad R1 except meeting covers the horizontal fin structure 26a of each fin structure 24, it also can cover the vertical fin shaped structure 26b of each fin structure 24 simultaneously, that is is positioned at the direct U-shaped end that covers each fin structure 24a, 24b, 24c, 24d of each electric contact structure 42 of trap bonding pad R1.Specifically, each electric contact structure 42 that is positioned at trap bonding pad R1 is two sides 80a, the 80b and the end face 80c that are oppositely arranged separately of exposure level fin structure 26a and vertical fin shaped structure 26b directly, has therefore increased whole contact area and has reduced contact resistance.Under this spline structure, if apply a voltage in trap bonding pad R1, only can produce less pressure drop between electric contact structure 42 and horizontal/vertical fin structure 26a, 26b, therefore can smoothly voltage be applied to trap doped region 28 via trap connecting doped area 30.Should be noted at this, electric contact structure 42 can sequentially comprise barrier layer and/or adhesion coating from the bottom to top, for example titanium nitride or tantalum nitride, and conductive layer, and high conductivity material such as aluminium, tungsten or copper, but be not limited to this.
The utility model separately can comprise the change type of other semiconductor device structures except above-mentioned the first preferred embodiment.The structure of these change types and manufacturing process steps roughly are similar to above-mentioned the first preferred embodiment, below only described with regard to the Main Differences place, and the reference of can arranging in pairs or groups of similar element and structure.
As Fig. 8 and shown in Figure 9, Fig. 8 has illustrated the schematic top plan view of the utility model first preferred embodiment the first change type, and Fig. 9 is the generalized section that illustrates along Fig. 8 Vertical Centre Line C-C '.The structure of the first change type shown in Figure 8 is probably corresponding to the structure of the first preferred embodiment shown in Figure 6, both main difference are, the semiconductor device of this first change type separately comprises a plurality of masking structures 60, and it can be used for preventing that the epitaxial loayer growth is in the specific region of fin structure 24.Wherein, one masking structure 60 can be arranged at 42 of two interior electric contact structures of trap bonding pad R1, and two masking structures 60 can directly contact a plurality of fin structures 24 in trap bonding pad R1 separately, particularly directly contact a plurality of horizontal fin structure 26a, but are not limited to this.Therefore, each electric contact structure 42 that is positioned at trap bonding pad R1 can cover and directly contact each corresponding masking structure 60, but is not limited to this.According to other embodiment, masking structure also can be arranged between the electric contact structure of trap bonding pad and active region, thereby disconnected from each other with electric contact structure.Therefore, even if be provided with masking structure 60, also can be owing to there be vertical fin shaped structure 26b in the semiconductor device of this first change type in trap bonding pad R1, the size that reduces its contact resistance and reduced trap bonding pad R1, and then promoted the degree that amasss into of semiconductor device.
Specifically, the time point of the structure of above-mentioned the first change type masking structure 60 and formation can be same as in fact the structure of active region R2 inner grid structure 32 and the time point of formation.For instance, when completing the grid structure of semiconductor device by the normal-gate manufacture craft, each masking structure 60 also can envelope the part section of each fin structure 24, and it comprises cap rock 66 on a dielectric layer 62, a conductive layer 64 and to I haven't seen you for ages from bottom to up, and the sidewall of each masking structure 60 also can be covered by clearance wall 68.Wherein, the material of above-mentioned dielectric layer, conductive layer and upper cap rock can correspond to respectively above-mentioned the first described gate dielectric of preferred embodiment, grid conducting layer and upper cap rock, but is not limited to this.But the utility model is not limited to this, and it also can utilize rear gate fabrication process to prepare grid structure and/or masking structure.
Except above-mentioned the first change type, the utility model also comprises the second change type of the first preferred embodiment.As shown in figure 10, Figure 10 has illustrated the schematic top plan view of the utility model first preferred embodiment the second change type.The structure of the second change type and manufacturing process steps roughly are similar to structure and the manufacturing process steps of the first preferred embodiment, both main difference are, the 3rd fin structure 24c that this change type is positioned at right side active region R2 only has the two horizontal fin structure 26a that are arranged in parallel, and does not have vertical fin shaped structure 26b.Remaining first, second and the 4th fin structure 24a, 24b, 24d still have the two horizontal fin structure 26a that are arranged in parallel and a vertical fin shaped structure 26b.Therefore, be positioned at the direct covering of 42 meetings of electric contact structure on R1 right side, trap bonding pad and the two horizontal fin structure 26a that are arranged in parallel of the 3rd fin structure 24c.Except the 3rd fin structure 24c does not have vertical fin shaped structure 26b, the structure of this change type embodiment or manufacture craft in fact all are similar to Fig. 1 of the first preferred embodiment and above-mentioned change type to structure or manufacture craft shown in Figure 9, just repeat no more at this.
Except above-mentioned the first and second change types, the utility model separately also comprises the 3rd change type of the first preferred embodiment.As shown in figure 11, Figure 11 has illustrated the schematic top plan view of the utility model the first preferred embodiment the 3rd change type.The structure of the 3rd change type and manufacturing process steps roughly are similar to structure and the manufacturing process steps of the first preferred embodiment, both main difference are, the same electric contact structure 42 that this change type is positioned at trap bonding pad R1 can directly cover the vertical fin shaped structure 26b of first to fourth fin structure 24a, 24b, 24c, 24d simultaneously.Except electric contact structure 42 can cover the vertical fin shaped structure 26b of first to fourth fin structure 24 simultaneously, the structure of this change type embodiment or manufacture craft in fact all are similar to Fig. 1 of the first preferred embodiment and above-mentioned change type to structure or manufacture craft shown in Figure 9, just repeat no more at this.
Should be noted at this, each above-mentioned change type also can be made up mutually according to the manufacture craft demand.For instance, can be in the situation that the trap bonding pad be provided with masking structure, an electric contact structure only is set in the trap bonding pad, contacting simultaneously the vertical fin shaped structure of first to fourth fin structure, but be not limited to this.
For the sake of brevity, the level of the various embodiments described above and vertical fin shaped structure 26a, 26b are as the contact area of trap bonding pad R1.Yet level of the present utility model and vertical fin shaped structure 26a, 26b not only are only applicable to trap bonding pad R1, and it can be applied to other suitable zones equably.For example, level of the present utility model and vertical fin shaped structure can be used in the source/drain region of transistor unit, or in the appropriate area of the semiconductor elements such as resistor (resistor), diode element, photo-sensitive cell (photosensitive device) or bipolar transistor (bipolar junction transistor, BJT).
In sum, according to embodiment of the present utility model, horizontal fin structure and vertical fin shaped structure all can be arranged in the trap bonding pad of semiconductor device.Therefore be positioned at trap bonding pad electric contact structure except the horizontal fin structure of meeting covering, its while also can cover the vertical fin shaped structure, and has larger contact area and lower contact resistance.Under this spline structure, if apply a voltage in the trap bonding pad, only can produce less pressure drop between electric contact structure and horizontal/vertical fin structure, therefore can smoothly voltage be applied to the trap doped region via the trap connecting doped area, and then promote the usefulness of semiconductor device.
Claims (18)
1. a semiconductor device, is characterized in that, this semiconductor device comprises:
Substrate, definition has a first area and a second area;
The first fin structure, be arranged on this substrate, this first fin structure comprises at least one horizontal fin structure that extends along a first direction, and a vertical fin shaped structure of extending along a second direction, wherein the part section of this horizontal fin structure and this vertical fin shaped structure are arranged in this first area;
Electric contact structure directly covers this at least one horizontal fin structure and this vertical fin shaped structure in this first area; And
Grid structure is arranged on this substrate, and this grid structure partially overlaps this at least one horizontal fin structure in this second area.
2. semiconductor device as claimed in claim 1, is characterized in that, vertical this second direction of this first direction.
3. semiconductor device as claimed in claim 1, is characterized in that, this first fin structure is a circulus.
4. semiconductor device as claimed in claim 1, is characterized in that, this first fin structure is one to have the circulus of opening.
5. semiconductor device as claimed in claim 1, it is characterized in that, this first fin structure comprises the horizontal fin structure that another extends along this first direction, and wherein this electric contact structure can directly contact those horizontal fin structures and this vertical fin shaped structure in this first area.
6. semiconductor device as claimed in claim 1, is characterized in that, this horizontal fin structure and this vertical fin shaped structure have the two sides that are oppositely arranged separately, and this electric contact structure can directly contact those sides.
7. semiconductor device as claimed in claim 1, is characterized in that, this first area is a trap bonding pad, and this second area is an active region.
8. semiconductor device as claimed in claim 7, is characterized in that, this semiconductor device comprises that separately one has the trap connecting doped area of the first conductivity type, is arranged in this trap bonding pad.
9. semiconductor device as claimed in claim 7, is characterized in that, this semiconductor device comprises that separately one has the source/drain doping region of the second conductivity type, is arranged in this active region.
10. semiconductor device as claimed in claim 9, is characterized in that, this source/drain doping region is arranged in this horizontal fin structure and is positioned at a side of this grid structure.
11. semiconductor device as claimed in claim 1, it is characterized in that, this semiconductor device separately comprises a trap connecting doped area and one source/drain doping region, be arranged at respectively in this first area and in this second area, wherein this trap connecting doped area has one first conductivity type, this source/drain doping region has one second conductivity type, and this first conductivity type is different from this second conductivity type.
12. semiconductor device as claimed in claim 1 is characterized in that, this semiconductor device separately comprises a masking structure, covers the part section of this horizontal fin structure, and wherein this electric contact structure can this masking structure of cover part.
13. semiconductor device as claimed in claim 1 is characterized in that, this semiconductor device separately comprises:
The second fin structure, be arranged on this substrate, this second fin structure comprises at least one horizontal fin structure that extends along this first direction, and a vertical fin shaped structure of extending along this second direction, wherein the part section of those horizontal fin structures and those vertical fin shaped structures all are arranged in this first area.
14. semiconductor device as claimed in claim 13 is characterized in that, vertical this second direction of this first direction.
15. semiconductor device as claimed in claim 13 is characterized in that, this electric contact structure is those horizontal fin structures of contact and those vertical fin shaped structures directly.
16. semiconductor device as claimed in claim 13 is characterized in that, this horizontal fin structure and this vertical fin shaped structure have the two sides that are oppositely arranged separately, and this electric contact structure can directly contact those sides.
17. semiconductor device as claimed in claim 16, it is characterized in that, this semiconductor device separately comprises a trap connecting doped area and one source/drain doping region, be arranged at respectively in this first area and in this second area, wherein this source/drain doping region is arranged at least one those horizontal fin structures and is positioned at a side of this grid structure.
18. semiconductor device as claimed in claim 17 is characterized in that, this trap connecting doped area has the first conductivity type, and this source/drain doping region has the second conductivity type, and this first conductivity type is different from this second conductivity type.
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| CN 201320300434 CN203277389U (en) | 2013-05-29 | 2013-05-29 | Semiconductor device |
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| CN 201320300434 CN203277389U (en) | 2013-05-29 | 2013-05-29 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185828A (en) * | 2015-06-12 | 2015-12-23 | 宁波时代全芯科技有限公司 | Fin type field effect transistor and manufacturing method thereof |
-
2013
- 2013-05-29 CN CN 201320300434 patent/CN203277389U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185828A (en) * | 2015-06-12 | 2015-12-23 | 宁波时代全芯科技有限公司 | Fin type field effect transistor and manufacturing method thereof |
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