CN105185828A - Fin type field effect transistor and manufacturing method thereof - Google Patents

Fin type field effect transistor and manufacturing method thereof Download PDF

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Publication number
CN105185828A
CN105185828A CN201510323753.0A CN201510323753A CN105185828A CN 105185828 A CN105185828 A CN 105185828A CN 201510323753 A CN201510323753 A CN 201510323753A CN 105185828 A CN105185828 A CN 105185828A
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China
Prior art keywords
basic unit
fin
hard cover
cover screen
effect transistor
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CN201510323753.0A
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Chinese (zh)
Inventor
吴孝哲
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British Vigin Islands Manufacturer Epoch Quan Xin Science And Technology Ltd
Jiangsu Advanced Memory Technology Co Ltd
Jiangsu Advanced Memory Semiconductor Co Ltd
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British Vigin Islands Manufacturer Epoch Quan Xin Science And Technology Ltd
Ningbo Epoch Quan Xin Science And Technology Ltd
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Priority to CN201510323753.0A priority Critical patent/CN105185828A/en
Publication of CN105185828A publication Critical patent/CN105185828A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a fin type field effect transistor and a manufacturing method thereof. The fin type field effect transistor comprises a base and a grid structure, wherein the base has two first fin type portions which are generally arranged in parallel, the grid structure is arranged on the first fin type portions and perpendicularly crosses the first fin type portions, and the grid structure contacts the base between the first fin type portions.

Description

Fin field-effect transistor and its preparation method
Technical field
The present invention is relevant a kind of fin field-effect transistor.
Background technology
The growth at a high speed of semiconductor integrated circuit (IC) industry experience.The integrated circuit of several generation has been created in the material of integrated circuit and the technological progress of design aspect, and the integrated circuit of every generation all has circuit than last Dai Geng little and more complicated.In the process of integrated circuit evolution, feature structure density (that is, the number of interconnective element in every chip area) reducing and increasing usually along with physical dimension (that is, the producible minimal modules of the manufacture method used or circuit).The advantage of the processing procedure of this dimension reduction is to enhance productivity and reduce relevant cost.
The reduction of size also promotes processing simultaneously and manufactures the complexity of integrated circuit, progressive in order to realize these, needs similar development in integrated circuit processing and manufacture view.Three-dimensional transistor, such as fin field-effect transistor (fin-likefield-effecttransistor, FinFET), be imported into replace planar transistor (planartransistor).Although existing fin field effect transistor element and manufacture method thereof are generally enough to reach the set goal, but all demands cannot be met completely.For example, the critical size (criticaldimension) in fin field-effect transistor between fin structure is very little, has exceeded the limit that current micro-shadow technology can reach.Therefore, industry needs a kind of novel and efficient processing procedure badly to prepare fin field-effect transistor.
Summary of the invention
An aspect of of the present present invention is to provide a kind of fin field-effect transistor, comprises a basic unit and a grid structure.Basic unit has two first fin portion in almost parallel arrangement, and grid structure to be positioned on these first fin portion and vertical across these the first fin portion, and grid structure contacts the basic unit between these first fin portion.
According to one or more execution mode of the present invention, grid structure comprises a gate dielectric and a gate electrode.Gate dielectric covers the basic unit between the sidewall of these the first fin portion and these the first fin portion, and gate electrode to be positioned on gate dielectric and vertical across these the first fin portion.
According to one or more execution mode of the present invention, basic unit also comprises two second fin portion and connects these the first fin portion, and to form an annular fin structure, and gate electrode is without across these the second fin portion.
Another aspect of the present invention is to provide a kind of preparation method of fin field-effect transistor, comprises the following step.First form one first hard cover screen in a basic unit, and basic unit has a central area and the surrounding zone around central area, then remove the basic unit of the first hard cover screen and the part being positioned at surrounding zone.Remove the first hard cover screen again, to make insulation system and between the basic unit of central area, to there is a difference in height, more form one second hard cover screen and conformally cover insulation system and basic unit.Remove part second hard cover screen afterwards, to be formed an annular hard cover screen by difference in height in basic unit, finally with annular hard cover screen for shade, depression insulation system and basic unit, has an annular fin structure to make basic unit.
According to one or more execution mode of the present invention, also comprise the following step.Form the sidewall that a gate dielectric covers annular fin structure again, with the basic unit being arranged in annular fin structure, form a gate electrode afterwards on gate dielectric.Last patterning gate electrode is to form a grid structure.
According to one or more execution mode of the present invention, after on formation insulation system to the basic unit of surrounding zone, more grind insulation system and the first hard cover screen, with a upper surface of the upper surface and the first hard cover screen that make insulation system for copline.
According to one or more execution mode of the present invention, the thickness of the first hard cover screen is between 900 to 1100 nanometers.
According to one or more execution mode of the present invention, be remove part second hard cover screen and cave in insulation system and basic unit with a dry ecthing procedure simultaneously, to make basic unit, there is ring-type fin structure.
According to one or more execution mode of the present invention, more form an oxide layer between basic unit and this first hard cover screen.
According to one or more execution mode of the present invention, be form the second hard cover screen conformally cover insulation system and basic unit with physical vaporous deposition (PVD), chemical vapour deposition technique (CVD), atomic layer deposition method (ALD) mode.
Accompanying drawing explanation
For above and other object of the present invention, feature, advantage and embodiment can be become apparent, being described in detail as follows of appended accompanying drawing:
Figure 1A illustrates the top view of a kind of fin field-effect transistor in the present invention's part execution mode;
Figure 1B illustrates the profile of fin field-effect transistor along AA hatching line of Figure 1A;
Fig. 1 C illustrates the profile of fin field-effect transistor along BB hatching line of Figure 1A;
Fig. 2 A illustrates the top view of a kind of fin field-effect transistor in the present invention's part execution mode;
Fig. 2 B illustrates the profile of fin field-effect transistor along AA hatching line of Fig. 2 A;
Fig. 2 C illustrates the profile of fin field-effect transistor along BB hatching line of Fig. 2 A;
Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A, Fig. 8 A and Fig. 9 A illustrate the fin field-effect transistor of Figure 1A respectively, at the top view in each stage of processing procedure;
Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 8 B and Fig. 9 B illustrate the fin field-effect transistor of Figure 1A respectively, the profile in each stage of processing procedure along AA hatching line;
Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, Fig. 7 C, Fig. 8 C and Fig. 9 C illustrate the fin field-effect transistor of Figure 1A respectively, the profile in each stage of processing procedure along CC hatching line.
Embodiment
Below will disclose multiple execution mode of the present invention with accompanying drawing, as clearly stated, the details in many practices will be explained in the following description.But should be appreciated that, the details in these practices is not applied to limit the present invention.That is, in some embodiments of the present invention, the details in these practices is non-essential.In addition, for simplifying for the purpose of accompanying drawing, some known usual structures and element illustrate in the mode simply illustrated in the accompanying drawings.
Please first consult Figure 1A to Fig. 1 C, along the profile of AA hatching line, Fig. 1 C illustrates the profile of fin field-effect transistor along BB hatching line of Figure 1A to the fin field-effect transistor that Figure 1A illustrates a kind of top view of fin field-effect transistor in the present invention's part execution mode, Figure 1B illustrates Figure 1A.As shown in Figure 1A to Fig. 1 C, fin field-effect transistor 100 has basic unit 110, insulation system 120, grid structure 130 and an annular hard cover screen 140.See it by Figure 1A, annular hard cover screen 140 is an enclosed construction, and basic unit 110 to be separated be that an a central area 110a and surrounding zone 110b is around central area 110a.Insulation system 120 is positioned at the surrounding zone 110b of substrate 110 and around this annular hard cover screen 140, but the basic unit 110 of central area 110a does not have any insulation system 120.Grid structure 130 is by central area 110a and marginal zone 110b, and the annular hard cover screen 140 of cover part.In section Example of the present invention, the material of annular hard cover screen 140 comprises silicon nitride, silicon oxynitride, carborundum, or other suitable materials.In other section Example of the present invention, the material of insulation system 120 comprises silicon nitride, silicon oxynitride, carborundum, fluorine silex glass or other suitable materials.
Continue to consult Figure 1B and Fig. 1 C, basic unit 110 has two first outstanding fin portion 112a and two second fin portion 112b.These first fin portion 112a is almost parallel arrangement, and these second fin portion 112b then lays respectively at the relative both sides of the first fin portion 112a to connect the first fin portion 112a.Whereby, an annular fin structure with enclosed construction can be formed, and annular hard cover screen 140 covers this annular fin structure.Annular fin structure makes nano level fin structure not easily collapse, and general upright fin structure, when nanoscale, because it is undersized, in manufacturing process, easily collapses.But be connected to form annular fin structure by the second fin portion 112b and the first fin portion 112a, make its structure more firm, and then promote yield and the reliability of fin field-effect transistor 100.In section Example of the present invention, the material of basic unit 110 comprises silicon or other semiconductor element, as germanium or iii-v element, but not as limit.
As shown in Figure 1 C, grid structure 130 is positioned on these first fin portion 112a, and vertical across these first fin portion 112a.First fin portion 112a is separated into source region and a drain region by grid structure 130, and the contact area between the first fin portion 112a and grid structure 130 is effective passage (effectivechannel) region of fin field-effect transistor 100.Vertical with the grid structure 130 of marginal zone 110b across these first fin portion 112a by central area 110a, and the grid structure 130 of part is positioned on insulation system 120.The basic unit 110 that it should be noted that central area 110a does not have insulation system 120, and therefore grid structure 130 can basic unit 110 directly between contact the first fin portion 112a, and increases the contact area between grid structure 130 and the first fin portion 112a.In the present embodiment, basic unit 110 has more an oxide layer 150, and grid structure 130 is the oxide layers 150 directly between contact the first fin portion 112a.
Specifically, grid structure 130 contacts the sidewall of the first fin portion 112a, makes it as channel transfer electric current.And because the basic unit 110 of central area 110a does not have insulation system 120, between the sidewall of grid structure 130 and the first fin portion 112a, larger contact area can be had, to increase channel width and to promote 100 drive currents of fin field-effect transistor.In other section Example of the present invention, fin field-effect transistor 100 does not have annular hard cover screen 140, and grid structure 130 more contacts the top of the first fin portion 112a, makes it also can be used as channel transfer electric current.
Please continue to refer to Figure 1B and Fig. 1 C, grid structure 130 described herein comprises gate dielectric 132 and a gate electrode 134.The sidewall of the covering first fin portion 112a that gate dielectric 132 is complied with, and the basic unit 110 between these first fin portion 112a.In addition, gate dielectric 132 more extends the sidewall of covering two second fin portion 112b.Gate electrode 134 is positioned on gate dielectric 132, and vertical across these first fin portion 112a.In section Example of the present invention, the material of gate dielectric 132 comprises silica, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, tantalum hafnium oxide, titanium oxide hafnium, tantalum hafnium oxide, or its combination, and the material of gate electrode 134 comprises polysilicon, tungsten, aluminium, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, copper, nickel or its combination.
As shown in Figure 1B, second fin portion 112b do not have gate electrode 134, and gate electrode 134 also can not across these second fin portion 112b, therefore it does not have any functional (functionality) in fin field-effect transistor 100.In other section Example of the present invention, fin field-effect transistor 100 can not have these second fin portion 112b, refers to Fig. 2 A to Fig. 2 C to understand the execution mode that fin field-effect transistor 100 does not have the second fin portion 112b.Along the profile of AA hatching line, Fig. 2 C illustrates the profile of fin field-effect transistor along BB hatching line of Fig. 2 A to the fin field-effect transistor that Fig. 2 A illustrates a kind of top view of fin field-effect transistor in other part execution modes of the present invention, Fig. 2 B illustrates Fig. 2 A.The fin field-effect transistor 200 of Fig. 2 A to Fig. 2 C is with the difference of the fin field-effect transistor 100 of Figure 1A to Fig. 1 C, the first fin portion 112a of Fig. 2 A to Fig. 2 C is almost parallel arrangement and separated from one another, there is not any second fin portion and connects these first fin portion 112a.The sidewall of the covering first fin portion 112a that gate dielectric 132 is complied with, and the basic unit 110 between two first fin portion 112a.Gate electrode 134 is positioned on gate dielectric 132, and vertical across these first fin portion 112a.
Please continue to refer to Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A, Fig. 8 A and Fig. 9 A, Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 8 B and Fig. 9 B, with Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, Fig. 7 C, Fig. 8 C and Fig. 9 C to understand the preparation method of the fin field-effect transistor 100 of Figure 1A.Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A, Fig. 8 A and Fig. 9 A illustrate the fin field-effect transistor 100 of Figure 1A respectively, the fin field-effect transistor 100 of Figure 1A is illustrated respectively at the top view in each stage of processing procedure, Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 8 B and Fig. 9 B, in each stage of processing procedure along the profile of AA hatching line and Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, Fig. 7 C, Fig. 8 C and Fig. 9 C illustrate the fin field-effect transistor 100 of Figure 1A, the profile in each stage of processing procedure along CC hatching line respectively.
As shown in Fig. 3 A to Fig. 3 C, first form one first hard cover screen 310 in basic unit 110, and basic unit 110 has central area 110a and the surrounding zone 110b around central area 110a, then formed on photoresist layer 320 to the first hard cover screen 310.The mode forming the first hard cover screen 310 can be such as physical vapour deposition (PVD), chemical vapour deposition (CVD) or ald, and the thickness T1 of this first hard cover screen 310 is between 900 to 1100 nanometers.Then by photoresist layer 320 rotary coating to the first hard cover screen 310, and exposure can be utilized by the design transfer of a light shield (not illustrating) on photoresist layer 320, to expose the first hard cover screen 310 being positioned at surrounding zone 110b.In section Example of the present invention, be in first deposited oxide layer 150 to basic unit 110, then deposit the first hard cover screen 310 in oxide layer 150, to form oxide layer 150 between basic unit 110 and the first hard cover screen 310.In other part embodiments of the present invention, the mode forming oxide layer 150 can be such as physical vapour deposition (PVD), chemical vapour deposition (CVD) or ald.Finally use dry ecthing or wet etching processing procedure, to be removed the basic unit 110 of the first hard cover screen 310, oxide layer 150 and the part that are positioned at surrounding zone 110b by photoresist layer 320.
Please then consult Fig. 4 A to Fig. 4 C, first remove photoresist layer 320, then formed in the basic unit 110 of insulation system 120 to surrounding zone 110b.Physical vapour deposition (PVD), chemical vapour deposition (CVD) or ald mode deposition of insulative material can be utilized, such as: silica, silicon nitride, silicon oxynitride or fluorine silex glass, to form insulation system 120, and insulation system 120 is around the basic unit 110 and the first hard cover screen 310 that are positioned at central area 110a.But in deposition process, the insulating material of part can be covered on the first hard cover screen 310, in this situation, then more grinding insulation system 120 and the first hard cover screen 310, to remove these residual insulating material, make a upper surface of a upper surface of insulation system 120 and the first hard cover screen 310 be copline further.In section Example of the present invention, be grind insulation system 120 and the first hard cover screen 310 with chemical mechanical milling method (chemicalmechanicalpolishing, CMP).
Continue to consult Fig. 5 A to Fig. 5 C, remove the first hard cover screen 310, to make insulation system 120 and between the basic unit 110 of central area 110a, to there is a height difference H 1.As previously mentioned, grinding makes the upper surface of insulation system 120 and the first hard cover screen 310 be copline, therefore after removing the first hard cover screen 310, understand height of formation difference H1 between insulation system 120 and the basic unit 110 of central area 110a, and this height difference H 1 is roughly identical with the thickness T1 of the first hard cover screen 310.
Then consult Fig. 6 A to Fig. 6 C, form one second hard cover screen 330 and conformally cover insulation system 120 and basic unit 110.In this embodiment, the basic unit 110 of central area 110a has more oxide layer 150, can form a height difference H 1 (referring to Fig. 5 B) between the upper surface and oxide layer 150 of insulation system 120 after removing the first hard cover screen 310, and the second hard cover screen 330 conformally covers insulation system 120 and oxide layer 150.Specifically, the second hard cover screen 330 is the upper surface and the sidewall that conformably cover insulation system 120, and the basic unit 110 of central area 110a.And the second hard cover screen 330 is greater than the thickness T3 in its upper surface at insulation system 120 and basic unit 110 at the thickness T2 of the side-walls of insulation system 120.Should be noted that, thickness T2 and T3 described herein is and basic unit 110 thickness in vertical direction.In section Example of the present invention, the first hard cover screen 310 and the second hard cover screen 330 can select identical or different material.In this embodiment, be unfavorable for forming the second conformal hard cover screen 330 if this height difference H 1 crosses young pathbreaker, therefore the first hard cover screen 310 need have enough thick thickness T1, to form enough height difference H 1 in insulation system 120 and between the basic unit 110 of central area 110a after removing the first hard cover screen 310.In section Example of the present invention, the thickness T1 of the first hard cover screen 310 is between 900 to 1100 nanometers.Moreover, be form the second hard cover screen 330 to reach good step coverage with physical vaporous deposition (PVD), chemical vapour deposition technique (CVD), atomic layer deposition method (ALD) mode, make the second hard cover screen 330 cover the sidewall of insulation system 120 uniformly whereby.
Then consult Fig. 7 A to Fig. 7 C, remove part second hard cover screen 330, to be formed annular hard cover screen 140 by this difference in height in basic unit 110.As previously mentioned, because having difference in height between basic unit 110 and insulation system 120, the second hard cover screen 330 of conformal formation is made to have different thickness T2 and T3.In anisotropic etching processing procedure, the second hard cover screen 330 and basic unit 110 thickness in vertical direction can be cut down gradually, with remove be positioned at insulation system 120 upper surface and basic unit 110 on the second hard cover screen 330.But the second hard cover screen 330 being positioned at the sidewall of insulation system 120 can not be completely removed because having larger thickness T2, it still to be stayed in basic unit 110 and has loop configuration.As shown in Fig. 7 B and Fig. 7 C, the anisotropic etching processing procedure thickness T2 that cuts down the second hard cover screen 330 is to expose the oxide layer 150 of the insulation system 120 under it and part, and remaining annular hard cover screen 140 is in the side-walls of insulation system 120.This annular hard cover screen 140 is substantially equal to thickness T2 with basic unit 110 thickness T4 in vertical direction and deducts thickness T3.
Continue to consult Fig. 8 A to Fig. 8 C, with annular hard cover screen 140 for shade, carry out etch process with insulation system 120 and the basic unit 110 of caving in, to make basic unit 110, there is annular fin structure.Basic unit 110 under annular hard cover screen 140 and oxide layer 150 are protected and can not be removed in etch process; and the basic unit 110 of insulation system 120 and part and oxide layer 150 be not because being covered by annular hard cover screen 140; it will cave in gradually in etch process, make annular fin structure protrude from basic unit 110.In section Example of the present invention, also can remove annular hard cover screen 140 partly while depression insulation system 120 and basic unit 110, its thickness is reduced.In other section Example of the present invention, the condition of etch process can be controlled, to remove annular hard cover screen 140 completely, only remaining outstanding annular fin structure while depression insulation system 120 with basic unit 110.This ring-type fin structure has the two first fin portion 112a in almost parallel arrangement, and the second fin portion 112b then lays respectively at the both sides of the first fin portion 112a to connect the first fin portion 112a.
Take a broad view of, the height difference H 1 of the first hard cover screen 310 makes the second hard cover screen 330 of formation have different thickness T2 and T3 in vertical substrate 110 direction, thus directly can cut down the thickness of the second hard cover screen 330 to prepare annular hard cover screen with anisotropic etching processing procedure, not need to use extra photoresist layer patterning second hard cover screen 330.In addition, the annular hard cover screen of formation has less critical size, and it can be used for preparing the annular fin structure with less critical size.
In section Example of the present invention, be use one dry ecthing procedure, with cave in while removing part second hard cover screen 330 insulation system 120 and basic unit 110, and form annular fin structure in basic unit 110.In other section Example of the present invention, the etching gas that dry ecthing procedure uses can comprise sulphur hexafluoride, helium, carbon tetrafluoride, fluoroform, hydrogen bromide, chlorine, oxygen, nitrogen or its combination, but the present invention is not as limit.
Finally, form a grid structure 130 on annular fin structure, and across annular fin structure partly.Consult Fig. 9 A to Fig. 9 C, in this step, it is the sidewall that first gate dielectric layer 132 covers ring-type fin structure, and the basic unit 110 between two first fin portion 112a, then again gate electrode 134 on gate dielectric 132, last patterning gate electrode 134 again to form grid structure 130, and completes the preparation of fin field-effect transistor 100 as shown in figs. 1 a to 1 c.As previously mentioned, annular fin structure can be subdivided into the first fin portion 112a and the second fin portion 112b.In this embodiment, the gate electrode 134 formed by patterning process is vertical across these first fin portion 112a, and the first fin portion 112a of doping grid electrode 134 both sides is to form source region and drain region.It should be noted that do not have any insulation system 120 between the first fin portion 112a, the lock level structure therefore formed directly can contact the basic unit 110 between the first fin portion 112a.In addition, gate electrode 134 other with its sidewall on the second fin portion 112b is completely removed in patterning process, and the second fin portion 112b is not had any functional (functionality) in fin field-effect transistor 100.In section Example of the present invention, forming gate dielectric 132 with gate electrode 134 can be such as physical vapour deposition (PVD), chemical vapour deposition (CVD) or ald.
It should be noted that after the step of Fig. 8 A to Fig. 8 C, the second fin portion 112b of removable non-functional.Such as, a patterning photoresist layer can be used to cover the first fin portion 112a of annular fin structure, and utilize dry ecthing procedure or wet etching processing procedure to remove the second fin portion 112b of exposure, remove patterning photoresist layer more afterwards, separative two the first fin portion 112a of basic unit 110 tool can be made whereby.Then, gate dielectric layer 132 covers the sidewall of structure first fin portion 112a, and the basic unit 110 between these first fin portion 112a, then again gate electrode 134 on gate dielectric 132, last patterning gate electrode 134 again to form grid structure 130, and completes the preparation of the fin field-effect transistor 200 as shown in Fig. 2 A ~ 2C.
Although the present invention discloses as above with execution mode; so itself and be not used to limit the present invention; anyly be familiar with this those skilled in the art; without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, the scope that therefore protection scope of the present invention ought define depending on appending claims is as the criterion.

Claims (10)

1. a fin field-effect transistor, is characterized in that, comprises:
One basic unit, has two first fin portion, and described first fin portion is almost parallel arrangement; And
One grid structure, to be positioned on described first fin portion and vertical across described first fin portion, and this basic unit between described first fin portion of this grid structure contact.
2. fin field-effect transistor according to claim 1, is characterized in that, this grid structure comprises:
One gate dielectric, covers this basic unit between the sidewall of described first fin portion and described first fin portion; And
One gate electrode, to be positioned on this gate dielectric and vertical across described first fin portion.
3. fin field-effect transistor according to claim 2, is characterized in that, this basic unit also comprises two second fin portion and connects described first fin portion, and to form an annular fin structure, and this gate electrode is without across described second fin portion.
4. a preparation method for fin field-effect transistor, is characterized in that, comprises:
Form one first hard cover screen in a basic unit, this basic unit has a central area and a surrounding zone around this central area;
Remove this first hard cover screen and this basic unit of part of being positioned at this surrounding zone;
Form an insulation system in this basic unit of this surrounding zone;
Remove this first hard cover screen, to make this insulation system and between this basic unit of this central area, to there is a difference in height;
Form one second hard cover screen and conformally cover this insulation system and this basic unit;
Remove this second hard cover screen of part, to be formed an annular hard cover screen by this difference in height in this basic unit; And
With this annular hard cover screen for shade, cave in this insulation system and this basic unit, have an annular fin structure to make this basic unit.
5. the preparation method of fin field-effect transistor according to claim 4, is characterized in that, also comprise:
Form the sidewall that a gate dielectric covers this annular fin structure, with this basic unit being arranged in this annular fin structure;
Form a gate electrode on this gate dielectric; And
This gate electrode of patterning is to form a grid structure.
6. the preparation method of fin field-effect transistor according to claim 4, is characterized in that, after on formation this insulation system to this basic unit of this surrounding zone, also comprises:
Grind this insulation system and this first hard cover screen, with a upper surface of the upper surface and this first hard cover screen that make this insulation system for copline.
7. the preparation method of fin field-effect transistor according to claim 4, is characterized in that, the thickness of this first hard cover screen is between 900 to 1100 nanometers.
8. the preparation method of fin field-effect transistor according to claim 4, is characterized in that, is to remove this second hard cover screen of part and cave in this insulation system and this basic unit with a dry ecthing procedure simultaneously, has this ring-type fin structure to make this basic unit.
9. the preparation method of fin field-effect transistor according to claim 4, is characterized in that, also comprise:
Form an oxide layer between this basic unit and this first hard cover screen.
10. the preparation method of fin field-effect transistor according to claim 4, is characterized in that, is to form this second hard cover screen conformally cover this insulation system and this basic unit with physical vaporous deposition, chemical vapour deposition technique, atomic layer deposition method mode.
CN201510323753.0A 2015-06-12 2015-06-12 Fin type field effect transistor and manufacturing method thereof Pending CN105185828A (en)

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CN105788632A (en) * 2016-02-26 2016-07-20 宁波时代全芯科技有限公司 Memory structure and memory circuit
CN107026175A (en) * 2015-12-28 2017-08-08 瑞萨电子株式会社 Semiconductor devices and its manufacture method
CN107492571A (en) * 2016-06-13 2017-12-19 格科微电子（上海）有限公司 Double fin-shaped field effect transistors of cmos image sensor

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CN101097952A (en) * 2006-06-26 2008-01-02 茂德科技股份有限公司 Multiple fin-shaped field effect transistors and manufacture thereof
US20130168819A1 (en) * 2011-12-28 2013-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like BJT
CN203277389U (en) * 2013-05-29 2013-11-06 联华电子股份有限公司 Semiconductor device

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CN101097952A (en) * 2006-06-26 2008-01-02 茂德科技股份有限公司 Multiple fin-shaped field effect transistors and manufacture thereof
US20130168819A1 (en) * 2011-12-28 2013-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like BJT
CN203277389U (en) * 2013-05-29 2013-11-06 联华电子股份有限公司 Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107026175A (en) * 2015-12-28 2017-08-08 瑞萨电子株式会社 Semiconductor devices and its manufacture method
CN107026175B (en) * 2015-12-28 2022-02-18 瑞萨电子株式会社 Semiconductor device and method for manufacturing the same
CN105788632A (en) * 2016-02-26 2016-07-20 宁波时代全芯科技有限公司 Memory structure and memory circuit
CN105788632B (en) * 2016-02-26 2019-04-02 江苏时代全芯存储科技有限公司 Memory circuit
CN107492571A (en) * 2016-06-13 2017-12-19 格科微电子（上海）有限公司 Double fin-shaped field effect transistors of cmos image sensor

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