CN105788632A - Memory structure and memory circuit - Google Patents

Memory structure and memory circuit Download PDF

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Publication number
CN105788632A
CN105788632A CN201610107337.1A CN201610107337A CN105788632A CN 105788632 A CN105788632 A CN 105788632A CN 201610107337 A CN201610107337 A CN 201610107337A CN 105788632 A CN105788632 A CN 105788632A
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layer
mnemon
memory
switch
metal
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CN105788632B (en
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吴孝哲
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Beijing Times Full Core Storage Technology Co ltd
Being Advanced Memory Taiwan Ltd
Jiangsu Advanced Memory Semiconductor Co Ltd
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British Vigin Islands Manufacturer Epoch Quan Xin Science And Technology Ltd
Ningbo Epoch Quan Xin Science And Technology Ltd
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Priority to CN201610107337.1A priority Critical patent/CN105788632B/en
Priority to CN201910048257.7A priority patent/CN109859787B/en
Publication of CN105788632A publication Critical patent/CN105788632A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention discloses a memory structure and a memory circuit.The memory structure comprises a transistor switch, an insulation structure covering the upper portion and the surrounding of the transistor switch, a plurality of memory unit layers arranged on the insulation structure and vertically piled, and a metal layer structure.The transistor switch comprises a gate structure, a source electrode and a drain electrode.Each memory unit layer comprises a conductive substrate electrically connected with the source electrode of the transistor switch through a source electrode contact hole, a plurality of diode structures located on the conductive substrate, a plurality of memory units located on the diode structures respectively, and a plurality of conductive layers located on the memory units respectively and arrayed roughly perpendicular to the conductive substrate.The metal layer structure is electrically connected with the drain electrode of the transistor switch through a drain electrode contact hole.In this way, a plurality of memory units in the memory unit layer can be controlled through one control switch, the memory capacity of unit area is improved, the processing steps of the three-dimensional memory circuit is simplified, and the processing cost is reduced.

Description

Memory structure and memory circuit
Technical field
The present invention is about a kind of memory circuit, and especially with regard to a kind of Three Dimensional Memory body circuit.
Background technology
Recently, face the physics limit on yardstick along with existing memory technologies, develop new memory technologies and become the research and development problem that presently relevant field is important.
Due in existing two dimension memory array, conventional basic structure is to be controlled with one mnemon of a transistor collocation, in order to reduce cost and improve the memory capacity of memory array in unit are, how framework Three Dimensional Memory body (3Dmemory) array, and be controlled with the multiple mnemons of transistor collocation, the target that actually pole, currently associated field need to be improved.
Summary of the invention
For solving problem above, a technical scheme of the present invention is a kind of memory structure.Memory structure comprises: a transistor switch, and it comprises a grid structure, and a source electrode and drains；One insulation system, covers this transistor switch over and around；Multiple mnemon layers, described mnemon layer is arranged at above this insulation system and perpendicular stacking, and each of which mnemon layer comprises: a conductive soleplate, and is electrically connected with a source contact openings between this source electrode of this transistor switch；Multiple diode structures, are positioned on this conductive soleplate；Multiple mnemons, lay respectively on described diode structure；And multiple conductive layer, substantially become arranged vertically with this conductive soleplate, lay respectively in described mnemon；And a metal-layer structure, and it is electrically connected with a drain contact hole between this drain electrode of this transistor switch.
In the section Example of the present invention, this metal-layer structure, it is positioned at above described mnemon layer.
In the section Example of the present invention, this metal-layer structure, be arranged at below described mnemon layer with in this insulation system.
In the section Example of the present invention, this metal-layer structure comprises: a first metal layer, overlooks and is rectangle shape, and one first end of this first metal layer is connected with this drain contact hole；One second metal level, overlooks in strip and substantially vertical with this first metal layer, and this second metal level is arranged on this first metal layer, and is connected with one second end of this first metal layer.
In the section Example of the present invention, this transistor switch comprises a field-effect transistor or a fin-shaped field-effect transistor.
In the section Example of the present invention, this grid structure comprises: a gate dielectric；One gate electrode, is positioned on this gate dielectric；And a sealing coat, it being positioned at the top of this gate electrode, this sealing coat is coated with this gate electrode.
In the section Example of the present invention, described memory cell comprises a phase-change memory or a resistance-type memory body；Described diode structure comprises respectively: a n type semiconductor layer, is positioned on this base plate；One p type semiconductor layer, is positioned on this n type semiconductor layer, contacts with corresponding mnemon layer.
The another kind of technical scheme of the present invention is a kind of memory circuit, comprises: one controls switch, comprises: a gate terminal, is coupled to a corresponding character line；One drain electrode end, is coupled to a corresponding bit line；And source-side；And multiple mnemon layer, described mnemon layer each is each self-contained: multiple diodes, and one first end of described diode is coupled to this source terminal of this control switch；Multiple mnemons, one first end of described mnemon is coupled to one second end of corresponding diode, one second end of described mnemon, is coupled to one and selects switch accordingly.
In the section Example of the present invention, memory circuit also comprises: multiple selection lines, the one of wherein said selection switch controls end and is coupled to corresponding selection line in order to receive a selection signal to determine whether described selection switch turns on, described one first end selecting switch is coupled to corresponding mnemon, and one second end of described selection switch is coupled to an earth terminal.
In the section Example of the present invention, described mnemon is resistance-type memory body or phase-change memory.
In sum, technical scheme compared with prior art has clear advantage and beneficial effect.By technique scheme, suitable technological progress can be reached, and there is the extensive value in industry.The present invention passes through by the mnemon controlled in the multiple mnemon layer of on-off control, the memory capacity in raising unit are, and simplifies the fabrication steps of Three Dimensional Memory body circuit, reduces processing procedure cost.
Accompanying drawing explanation
Fig. 1 is the memory circuit schematic diagram according to one embodiment of the invention depicted；
Fig. 2 A, 3A, 4A, 5A, 6A, 7A, 8A and 9A illustrate in one embodiment of the invention Three Dimensional Memory body structure respectively at the top view in each stage of processing procedure；
Fig. 2 B, 3B, 4B, 5B, 6B, 7B, 8B and 9B respectively Fig. 2 A, 3A, 4A, 5A, 6A, 7A, 8A and 9A is along the profile of AA ' hatching line；
Fig. 6 C, 7C, 8C and 9C respectively Fig. 6 A, 7A, 8A and 9A is along the profile of BB ' hatching line；
Figure 10 A, 11A, 12A, 13A, 14A, 15A, 16A, 17A and 18A illustrate in one embodiment of the invention Three Dimensional Memory body structure respectively at the top view in each stage of processing procedure；
Figure 10 B, 11B, 12B, 13B, 14B, 15B, 16B, 17B and 18B respectively Figure 10 A, 11A, 12A, 13A, 14A, 15A, 16A, 17A and 18A is along the profile of AA ' hatching line；
Figure 14 C, 15C, 16C, 17C and 18C respectively Figure 14 A, 15A, 16A, 17A and 18A is along the profile of BB ' hatching line.
Detailed description of the invention
It is hereafter coordinate appended accompanying drawing to elaborate for embodiment, to be more fully understood that the aspect of the present invention, but the embodiment provided also is not used to limit the scope that this exposure is contained, and the description of structure operation is not used to limit the order of its execution, any structure reconfigured by element, produced the device with impartial effect, be all the scope that this exposure is contained.Additionally, according to the standard of industry and practice, accompanying drawing is only for the purpose of aiding in illustrating, and maps not according to life size, the size of actually various features can at random increase or reduce so that explanation.In the description below, similar elements will illustrate so that understanding with identical symbology.
In the word (terms) that full section description and claims use, except having and indicating especially, be generally of each word use in this area, in the content of this exposure with the usual meaning in special content.Some is in order to describe the word of this exposure by lower or discuss in the other places of this description, to provide those skilled in the art about guiding extra in the description of this exposure.
Additionally, the word used in this article " comprising ", " including ", " having ", " containing " etc., it is the term of opening, namely mean " including but not limited to ".Additionally, used herein " and/or ", comprise any one and its all combinations of one or more project in associated listed items.
In herein, when an element is referred to as " connection " or " coupling ", " electric connection " or " electric property coupling " can be referred to." connection " or " coupling " also may be used to expression two or multiple interelement is collocated with each other operation or interactive.Additionally, " first " although used herein, " second " ... wait term to describe different elements, this term is only distinguish the element or operation that describe with constructed term.Indicating unless context is clear, otherwise this term is not censured especially or implies order or cis-position, is also not used to limit the present invention.
Refer to Fig. 1.Fig. 1 is memory circuit 100 schematic diagram according to one embodiment of the invention depicted.As it is shown in figure 1, in one embodiment of the invention, memory circuit 100 comprises the memory array formed by a plurality of character line WL1, WL2～WLx and multiple bit lines BL1, BL2～BLx.
In this memory array, the gate terminal controlling switch SW1 is coupled to corresponding character line WL1, and the drain electrode end controlling switch SW1 is coupled to corresponding bit line BL1.The source terminal controlling switch SW1 is coupled to multiple mnemon layer S1～Sx.In an embodiment of the present invention, controlling switch SW1 can by field-effect transistor (field-effecttransistor, FET), or fin-shaped field-effect transistor (FinFET) implementation.
Mnemon layer S1 comprises multiple diode D1, multiple mnemon M1, multiple selection switch Q111～Q11x and a plurality of selection line SL111～SL11x.Structurally, first end of diode D1 (such as anode tap) is coupled to the source terminal controlling switch SW1, and second end of diode D1 (such as cathode terminal) is coupled to first end of corresponding mnemon M1.Second end of mnemon M1 is coupled to corresponding the first end selecting switch Q111～Q11x.
Similarly, as it is shown in figure 1, mnemon layer Sx also comprises multiple diode Dx, multiple mnemon Mx, multiple selection switch Q1x1～Q1xx and a plurality of selection line SL1x1～SL1xx.Structurally, in mnemon layer Sx, the annexation between diode Dx, mnemon Mx and selection line SL1x1～SL1xx is similar with corresponding element in mnemon layer S1, therefore repeats no more in this.In addition, controlling switch SW2 is that the control being coupled to character line WL1 and bit line BL2 switchs, control switch SW3, SW4 to be respectively coupled to the control of character line WL2 and bit line BL1, BL2 and switch, the connected mode of its corresponding mnemon is similar to corresponding to the mnemon controlling switch SW1, therefore repeats no more in this.
It should be noted that in Fig. 1, the circuit of depicted is only the use releasing example, in some embodiments, memory circuit 100 can be the structure of multilamellar multiple spot.Illustrating, the y-th mnemon of xth layer mnemon layer Sx is electrically connected at selection switch Qxy, selects switch Qxy according to the corresponding signal conduction selecting line SLxy or shutoff, and wherein x, y are any positive integer.
Line SL111～SL1xx is selected to be respectively coupled to the corresponding control end selecting switch Q111～Q1xx, respectively in order to receive selection signal to determine to select whether switch Q111～Q1xx turns on, and character line WL1, WL2 and bit line BL1, BL2 is coordinated to choose mnemon M1～Mx corresponding in memory array.In section Example of the present invention, mnemon M1～Mx can be resistance-type memory body or phase-change memory, but is not limited thereto.
Through above memory circuit, only need one to control switch SW1 and just can control the multiple mnemon M1～Mx in multiple mnemon layer S1～Sx, through the setting of Three Dimensional Memory body circuit, it is possible to save space, improve the memory capacity in unit are, and reduce processing procedure cost.
The concrete processing procedure mode of above-mentioned memory circuit and memory structure accompanying drawing of arranging in pairs or groups in the following paragraphs illustrates, and is described separately mnemon and is arranged in different fabrication steps and the memory structure of first layer metal layer below or above.Only for being easier to understand the manufacturing process of Three Dimensional Memory body circuit of the present invention, drawings below does not illustrate selection switch Qxxx especially, selecting switch Qxxx is transistor, and it can simultaneously complete when making and controlling switch SWx, and is also known semiconductor technology with the connected mode of mnemon Mx.
Refer to Fig. 2 A, 3A, 4A, 5A, 6A, 7A, 8A and 9A, Fig. 2 B, 3B, 4B, 5B, 6B, 7B, 8B and 9B, with Fig. 6 C, 7C, 8C and 9C to understand the preparation method being configured at the mnemon below first layer metal layer in the Three Dimensional Memory body circuit of the present invention.Fig. 2 A, 3A, 4A, 5A, 6A, 7A, 8A and 9A illustrate the Three Dimensional Memory body structure top view in each stage of processing procedure respectively, and Fig. 2 B, 3B, 4B, 5B, 6B, 7B, 8B and 9B respectively Fig. 2 A, 3A, 4A, 5A, 6A, 7A, 8A and 9A are along the profile of AA ' hatching line.Fig. 6 C, 7C, 8C and 9C respectively Fig. 6 A, 7A, 8A and 9A are along the profile of BB ' hatching line.For convenience, following example are that memory circuit shown in collocation Fig. 1 illustrates, but and are not used to the restriction present invention.
First, as shown in Fig. 2 A to Fig. 2 B, it is initially formed an active layers 120 (Activearea) and insulating barrier 125 in a basic unit 110.Action zone (Activearea) 120 and insulating barrier 125 can by light shield, light shield etchings, or even the various ways such as STI shallow trench isolation technology (ShallowTrenchIsolation, STI) is formed.
With continued reference to Fig. 3 A to Fig. 3 B, formed in grid structure 130 a to active layers 120.In this step, be first gate dielectric layer 132 in active layers 120, then again gate electrode on gate dielectric 132.In some embodiments, the material of gate dielectric 132 comprises silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, tantalum hafnium oxide, titanium oxide hafnium, tantalum hafnium oxide or its combination.The material of gate electrode can comprise polysilicon, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, copper, nickel or its combination.For example, in some embodiments, gate electrode can comprise polysilicon layer 134 and the silicide layer 136 being positioned on polysilicon layer 134, and the material of silicide layer 136 can be that metal silicide is to reduce the resistance value of gate electrode.
Then, forming sealing coat 138 and be positioned at the top of gate electrode 134 and contact active layers 120, sealing coat 138 and gate dielectric 132 form a closing space to be coated with gate electrode.Consequently, it is possible to grid structure 130 just can be formed in active layers 120.It should be noted that sealing coat 138 and insulating barrier 125 can identical or different material be formed, when sealing coat 138 and insulating barrier 125 with different material formed time, will have an interface between the two.In some embodiments, the material of insulating barrier 125 is the oxide of the material of active layers 120, and the material of sealing coat 138 can comprise silicon oxide, silicon nitride, aluminium oxide and aluminium nitride, but is not limited.In some embodiments, the mode forming gate dielectric 132 and gate electrode can be such as physical vapour deposition (PVD), chemical vapour deposition (CVD) or ald, but is not limited.
With continued reference to Fig. 4 A to Fig. 4 B, in depositing insulating layer 140 to basic unit 110, cover sealing coat 138.Then, the insulating barrier 140 of part is removed, to form the active layers 120 of a source contact openings 145 expose portion.In section Example, in this step, it is that the pattern of a light shield (not illustrating) is transferred on photoresist layer by recycling exposure imaging, with the insulating barrier 140 of expose portion first by photoresist layer (not illustrating) rotary coating to insulating barrier 140.Finally use dry ecthing or wet etching processing procedure, to be removed the insulating barrier 140 of part by photoresist layer, and form source contact openings 145.In the section Example of the present invention, after forming source contact openings 145, namely remove photoresist layer.
With continued reference to Fig. 5 A to Fig. 5 B, conducting medium 152 is filled in source contact openings 145, and on insulating barrier 140, forms base plate 150.In the section Example of the present invention, the mode forming base plate 150 can such as physical vapour deposition (PVD), chemical vapour deposition (CVD) or ald.
With continued reference to Fig. 6 A to Fig. 6 C, form insulating barrier 160 on insulating barrier 140 and base plate 150.Afterwards, grind insulating barrier 160, make a upper surface of insulating barrier 160 upper surface with base plate 150 for copline with order.In the section Example of the present invention, it is grind insulating barrier 160 with chemical mechanical milling method (chemicalmechanicalpolishing, CMP).Then, on the upper surface of insulating barrier 160 and base plate 150, sequentially form n type semiconductor layer 172, p type semiconductor layer 174 to form diode structure 170, and on diode structure 170, form mnemon 180.
Mnemon 180 can by phase-change memory (Phase-ChangeMemory, PCM/PhaseChangeRandomAccessMemory, or resistance-type memory body (Resistiverandom-accessmemory, RRAM/ReRAM) etc. implementation PCRAM).For example, pair of metal-Insulator-Metal (MIM) structure can be formed in some embodiments on diode structure 170 and form resistance-type memory body, as mnemon 180.
In some embodiments, the material of the n type semiconductor layer 172 in diode structure 170 may be included in adulterate in tetrels such as silicon crystal or germanium crystal a small amount of foreign matter of phosphor element or arsenic element.The material of p type semiconductor layer 174 may be included in adulterate in tetrels such as silicon crystal or germanium crystal a small amount of boron impurities element or aluminium element.
In some embodiments, the material of diode structure 170 also can comprise III-V quasiconductor such as aluminum phosphate, aluminium arsenide, GaAs, gallium nitride, adulterate a small amount of impurity such as selenium, tellurium, silicon, germanium, beryllium, zinc, cadmium, or form n type semiconductor layer 172 and p type semiconductor layer 174 respectively with the ternary known by the stakeholder of other this areas or quaternary compound.
Then, the mnemon 180 of part, p type semiconductor layer 174 and n type semiconductor layer 172 are removed with light shield etching.In this step, it is that the pattern of a light shield (not illustrating) is transferred on photoresist layer by recycling exposure imaging first by photoresist layer (not illustrating) rotary coating to mnemon 180.Finally use dry ecthing or wet etching processing procedure, to remove the n type semiconductor layer 172 of part, p type semiconductor layer 174 and mnemon 180 by photoresist layer.
After removing the mnemon 180 of part, p type semiconductor layer 174 and n type semiconductor layer 172, form insulating barrier 190, and grind insulating barrier 190, make a upper surface of insulating barrier 190 upper surface with mnemon 180 for copline with order.Consequently, it is possible to the structure that multiple diode structure is one another in series just can be formed with mnemon.Finally, conductive layer 185 is formed with tungsten (W) or other conductors, and the conductive layer 185 of part is removed equally with light shield etching mode, thus, just can be mutually arranged as, between vertical base plate 150 and conductive layer 185, arranging multiple memory cell connected by diode structure 170 and mnemon 180.
With continued reference to Fig. 7 A to Fig. 7 C, repeatedly repeat the step as shown in Fig. 6 A to Fig. 6 C, the stepped construction of multilayer bottom plate 150, diode structure 170, mnemon 180 and conductive layer 185 can be formed.Although it should be noted that and depicting two-layer mnemon layer in Fig. 7 A to Fig. 7 B, but actually the mnemon number in the number of plies of mnemon layer and each layer all can be adjusted according to actual demand.
Finally, refer to Fig. 8 A to Fig. 8 C and Fig. 9 A to Fig. 9 C, remove the insulating barrier of part, to form the active layers 120 of a drain contact hole 195 expose portion, and conducting medium 192 is filled in drain contact hole 195, first layer metal layer M1 is finally formed in surface.Consequently, it is possible to just can in the mnemon M1 of first layer metal layer M1 Three Dimensional Memory body circuit formed below.In some embodiments, first layer metal layer M1 and described conductive layer 185 are arranged to be generally parallel to each other.
Refer to Figure 10 A, 11A, 12A, 13A, 14A, 15A, 16A, 17A and 18A, Figure 10 B, 11B, 12B, 13B, 14B, 15B, 16B, 17B and 18B, and Figure 14 C, 15C, 16C, 17C and 18C are to understand the preparation method being configured at the mnemon above first layer metal layer in the Three Dimensional Memory body circuit of the present invention.Figure 10 A, 11A, 12A, 13A, 14A, 15A, 16A, 17A and 18A illustrate the Three Dimensional Memory body structure top view in each stage of processing procedure respectively, and Figure 10 B, 11B, 12B, 13B, 14B, 15B, 16B, 17B and 18B respectively Figure 10 A, 11A, 12A, 13A, 14A, 15A, 16A, 17A and 18A is along the profile of AA ' hatching line.Figure 14 C, 15C, 16C, 17C and 18C respectively Figure 14 A, 15A, 16A, 17A and 18A is along the profile of BB ' hatching line.Similar to preceding embodiment, for convenience, following example are that memory circuit shown in collocation Fig. 1 illustrates, but and are not used to the restriction present invention.
First, as shown in Figure 10 A to Figure 10 B, it is initially formed multiple active layers 220 (Activearea) and insulating barrier 225 in a basic unit 210.As shown in Figure 11 A to Figure 11 B, formed in grid structure 230 a to active layers 220.In this step, be first gate dielectric layer 232 in active layers 220, then again gate electrode on gate dielectric 232.For example, in some embodiments, gate electrode can comprise polysilicon layer 234 and the silicide layer 236 being positioned on polysilicon layer 234.Then, form sealing coat 238 be positioned at the top of gate electrode 234 and contact active layers 220.Consequently, it is possible to grid structure 230 just can be formed in active layers 220.
Then, such as Figure 12 A to Figure 12 B, after depositing insulating layer 240, the insulating barrier 240 of part is removed, to form the active layers 220 of a drain contact hole 245 expose portion.The detail of above-mentioned steps describes in detail in preceding embodiment, therefore repeats no more in this.
With continued reference to Figure 13 A to Figure 13 B, conducting medium 252 is filled in drain contact hole 245, and in the way of light shield etching, forms metal level base plate 250 on insulating barrier 240.
With continued reference to Figure 14 A to Figure 14 C, metal level base plate 250 and insulating barrier form first layer metal layer M1.As shown in Figure 14 A, observe from top view angle, be staggered between first layer metal layer M1 and active layers 220.Active layers 220 (as shown in Figure 14B) be can be observed along AA hatching line, first layer metal layer M1 (as shown in Figure 14 C) be can be observed along BB hatching line.
In other words, as shown in Figure 13 A to Figure 13 B and Figure 14 A to Figure 14 B, in some embodiments, metal level base plate 250 and first layer metal layer M1 in the metal-layer structure formed, metal level base plate 250 is overlooked and is rectangle shape, and the first end through metal level base plate 250 is connected with drain contact hole.First layer metal layer M1 overlooks in strip and substantially vertical with metal level base plate 250, and first layer metal layer M1 is arranged on metal level base plate 250, and is connected with the second end of metal level base plate 250.
With continued reference to Figure 15 A to Figure 15 C, continuously form insulating barrier 255, and remove insulating barrier partly, to form the active layers 220 of a contact hole 260 expose portion.Then, conducting medium 262 is filled in contact hole 260.With continued reference to Figure 16 A to Figure 16 C, in the way of light shield etching, form base plate 265 so that base plate 265 is connected with contact hole 260 respectively.In some embodiments, base plate 265 is arranged to substantially vertical with first layer metal layer M1.
After forming base plate 265, form insulating barrier 290 in becoming on base plate 265 to cover base plate 265, back plane grinds insulating barrier 290 to expose base plate 265, as shown in Figure 17 A to Figure 17 C, just n type semiconductor layer 272, p type semiconductor layer 274 be can sequentially form on base plate 265 to form diode structure 270, and on diode structure 270, mnemon 280 and conductive layer 285 formed.It is formed with diode structure 270, mnemon 280 and the detail of conductive layer 285 similar to previously described embodiment, therefore repeats no more in this.
Finally refer to Figure 18 A to Figure 18 C, repeatedly repeat the step as shown in Figure 17 A to Figure 17 C, the stepped construction of multilayer bottom plate 265, diode structure 270, mnemon 280 and conductive layer 285 can be formed.Although it should be noted that and depicting two-layer mnemon layer in Figure 18 A to Figure 18 C, but actually the mnemon number in the number of plies of mnemon layer and each layer all can be adjusted according to actual demand.Consequently, it is possible to just can be formed over the mnemon of Three Dimensional Memory body circuit in first layer metal layer M1.
First make the processing procedure mode of (gate-first) through above-mentioned grid, just can form the memory structure comprising active layers, grid structure, metal level M1 and multiple mnemon layer.
In some embodiments, the memory structure of the present invention comprises transistor switch, insulation system, multiple mnemon layer and metal-layer structure.Transistor switch its comprise grid structure, source electrode and drain electrode.Insulation system covering transistor switchs over and around.It is electrically connected with drain contact hole between metal-layer structure and the drain electrode of transistor switch.Mnemon layer is arranged at above insulation system, and it is perpendicular stacking, the conductive soleplate that each of which mnemon layer is each self-contained and is electrically connected with source contact openings between this source electrode of this transistor switch, the multiple diode structures being positioned on base plate, the multiple mnemons laid respectively on described diode structure, and lay respectively in mnemon, multiple conductive layers arranged vertically are substantially become with conductive soleplate.
Structurally, grid structure is positioned in active layers.It is electrically connected with contact hole between metal level M1 and active layers.Mnemon layer S1～Sx is perpendicular stacking each other, is each contained on base plate and is formed and multiple diode structure D1 of connecting and multiple mnemon M1, and be electrically connected with active layers through contact hole in each mnemon layer S1～Sx.According to different preparation methods and memory structure, mnemon layer S1～Sx can be located at the below or above of metal level M1.
Thus, just Three Dimensional Memory body circuit as shown in Figure 1 can be formed by above-mentioned memory structure, multiple mnemons that switch just can control in multiple mnemon layer are controlled through one, save space, improve the memory capacity in unit are, and simplify the fabrication steps of Three Dimensional Memory body circuit, reduce processing procedure cost.
Although the present invention is disclosed above with embodiment; so it is not limited to the present invention, any is familiar with this those skilled in the art, without departing from the spirit and scope of the present invention; when doing various change and retouching, therefore protection scope of the present invention ought be as the criterion depending on the scope that appending claims defines.

Claims (10)

1. a memory structure, it is characterised in that comprise:
One transistor switch, it comprises a grid structure, and a source electrode and drains；
One insulation system, covers this transistor switch over and around；
Multiple mnemon layers, described mnemon layer is arranged at above this insulation system and perpendicular stacking, and each of which mnemon layer comprises: a conductive soleplate, and is electrically connected with a source contact openings between this source electrode of this transistor switch；Multiple diode structures, are positioned on this conductive soleplate；Multiple mnemons, lay respectively on described diode structure；And multiple conductive layer, become arranged vertically with this conductive soleplate, lay respectively in described mnemon；And
One metal-layer structure, and be electrically connected with a drain contact hole between this drain electrode of this transistor switch.
2. memory structure according to claim 1, it is characterised in that this metal-layer structure, is positioned at above described mnemon layer.
3. memory structure according to claim 1, it is characterised in that this metal-layer structure, be arranged at below described mnemon layer with in this insulation system.
4. memory structure according to claim 3, it is characterised in that this metal-layer structure comprises:
One the first metal layer, overlooks and is rectangle shape, and one first end of this first metal layer is connected with this drain contact hole；
One second metal level, overlooks in strip and vertical with this first metal layer, and this second metal level is arranged on this first metal layer, and is connected with one second end of this first metal layer.
5. memory structure according to claim 1, it is characterised in that this transistor switch comprises a field-effect transistor or a fin-shaped field-effect transistor.
6. memory structure according to claim 1, it is characterised in that this grid structure comprises:
One gate dielectric；
One gate electrode, is positioned on this gate dielectric；And
One sealing coat, is positioned at the top of this gate electrode, and this sealing coat is coated with this gate electrode.
7. memory structure according to claim 1, it is characterised in that
Described memory cell comprises a phase-change memory or a resistance-type memory body；
Described diode structure comprises respectively:
One n type semiconductor layer, is positioned on this base plate；
One p type semiconductor layer, is positioned on this n type semiconductor layer, contacts with corresponding mnemon layer.
8. a memory circuit, it is characterised in that comprise:
One controls switch, comprises: a gate terminal, is coupled to a corresponding character line；One drain electrode end, is coupled to a corresponding bit line；And source-side；And
Multiple mnemon layers, described mnemon layer each is each self-contained: multiple diodes, and one first end of described diode is coupled to this source terminal of this control switch；Multiple mnemons, one first end of described mnemon is coupled to one second end of corresponding diode, one second end of described mnemon, is coupled to one and selects switch accordingly.
9. memory circuit according to claim 8, it is characterised in that also comprise:
Multiple selection lines, the one of wherein said selection switch controls end and is coupled to corresponding selection line in order to receive a selection signal to determine whether described selection switch turns on, described one first end selecting switch is coupled to corresponding mnemon, and one second end of described selection switch is coupled to an earth terminal.
10. memory circuit according to claim 8, it is characterised in that described mnemon is resistance-type memory body or phase-change memory.
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