CN105788632B - Memory circuit - Google Patents

Memory circuit Download PDF

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Publication number
CN105788632B
CN105788632B CN201610107337.1A CN201610107337A CN105788632B CN 105788632 B CN105788632 B CN 105788632B CN 201610107337 A CN201610107337 A CN 201610107337A CN 105788632 B CN105788632 B CN 105788632B
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China
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layer
memory
memory unit
metal
transistor switch
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CN105788632A (en
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吴孝哲
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Beijing Times Full Core Storage Technology Co ltd
Being Advanced Memory Taiwan Ltd
Jiangsu Advanced Memory Semiconductor Co Ltd
Original Assignee
British Vigin Islands Manufacturer Epoch Quan Xin Science And Technology Ltd
Jiangsu Advanced Memory Technology Co Ltd
Jiangsu Advanced Memory Semiconductor Co Ltd
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Application filed by British Vigin Islands Manufacturer Epoch Quan Xin Science And Technology Ltd, Jiangsu Advanced Memory Technology Co Ltd, Jiangsu Advanced Memory Semiconductor Co Ltd filed Critical British Vigin Islands Manufacturer Epoch Quan Xin Science And Technology Ltd
Priority to CN201610107337.1A priority Critical patent/CN105788632B/en
Priority to CN201910048257.7A priority patent/CN109859787B/en
Publication of CN105788632A publication Critical patent/CN105788632A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

A kind of memory circuit is in this exposure.Memory circuit includes the insulation system of the over and around of transistor switch, covering transistor switch, multiple memory unit layers and metal-layer structure for being set to insulation system top and perpendicular stacking.Transistor switch includes gate structure, source electrode and drain electrode.Each memory unit layer is included the conductive soleplate being electrically connected between the source electrode of transistor switch with source contact openings, multiple diode structures on conductive soleplate, the multiple memory units being located on diode structure and is located in memory unit, with conductive soleplate substantially at multiple conductive layers of vertical arrangement.It is electrically connected between metal-layer structure and the drain electrode of transistor switch with drain contact hole.In this way, which multiple memory units in multiple memory unit layers can be controlled through a control switch, the memory capacity in unit area is improved, and simplify the fabrication steps of Three Dimensional Memory body circuit, reduce processing procedure cost.

Description

Memory circuit
Technical field
The present invention relates to a kind of memory circuits, and especially with regard to a kind of Three Dimensional Memory body circuit.
Background technique
Recently, as existing memory technologies face the physics limit on scale, develop new memory technologies at For the important research and development project in presently relevant field.
Since in existing two-dimentional memory array, common basic structure is memory list of being arranged in pairs or groups with a transistor Member is controlled, in order to reduce cost and improve the memory capacity of memory array on unit area, how framework Three Dimensional Memory Body (3D memory) array, and controlled with the multiple memory units of transistor collocation, actually currently associated field pole needs Improved target.
Summary of the invention
In order to solve the above problem, a technical solution of the invention is a kind of memory structure.Memory structure includes: one is brilliant Body Guan Kaiguan, it includes a gate structure, a source electrode and a drain electrode；One insulation system, cover the transistor switch top and Around；Multiple memory unit layers, the memory unit layer is set to above the insulation system and perpendicular stacking, wherein each note Recalling elementary layer includes: with source contact openings electric connection between a conductive soleplate, and the source electrode of the transistor switch；It is multiple Diode structure is located on the conductive soleplate；Multiple memory units are located on the diode structure；And it multiple leads Electric layer is located in the memory unit with the conductive soleplate substantially at vertical arrangement；And a metal-layer structure, with this With drain contact hole electric connection between the drain electrode of transistor switch.
In section Example of the invention, which is located above the memory unit layer.
In section Example of the invention, which is set to below the memory unit layer and the insulation In structure.
In section Example of the invention, which includes: a first metal layer, and vertical view is in rectangular shape, One first end of the first metal layer is connect with the drain contact hole；One second metal layer, overlook it is in long strip and with this first Metal layer is substantially vertical, which is set on the first metal layer, and connects with a second end of the first metal layer It connects.
In section Example of the invention, which includes a field-effect transistor or a fin-shaped field-effect crystal Pipe.
In section Example of the invention, which includes: a gate dielectric；One gate electrode, being located at should On gate dielectric；And a separation layer, positioned at the top of the gate electrode, which coats the gate electrode.
In section Example of the invention, the memory cell includes that a phase-change memory or a resistance-type are remembered Body；The diode structure separately includes: a n type semiconductor layer, is located on the bottom plate；One p type semiconductor layer is located at the N-type On semiconductor layer, contacted with corresponding memory unit layer.
Another technical solution of the invention is a kind of memory circuit, and include: a control switch includes: a gate terminal, It is coupled to a corresponding character line；One drain electrode end is coupled to a corresponding bit line；And source-side；And multiple memories are single First layer, described memory unit layer each respectively contain: a first end of multiple diodes, the diode is coupled to the control The source terminal of switch；Multiple memory units, a first end of the memory unit are coupled to the one second of corresponding diode End, a second end of the memory unit are coupled to a corresponding selection switch.
In section Example of the invention, memory circuit also includes: multiple selection lines, wherein the selection switch Whether one control terminal is coupled to corresponding selection line and is connected to receive a selection signal with determining that the selection switchs, the choosing The first end for selecting switch is coupled to corresponding memory unit, and a second end of the selection switch is coupled to a ground terminal.
In section Example of the invention, the memory unit is resistance-type memory body or phase-change memory.
In conclusion technical solution of the present invention has clear advantage and beneficial effect compared with prior art.Pass through Above-mentioned technical proposal can reach comparable technological progress, and with the extensive utility value in industry.The present invention is penetrated by one Control switch controls the memory unit in multiple memory unit layers, improves the memory capacity in unit area, and simplifies three-dimensional note Recall the fabrication steps of body circuit, reduces processing procedure cost.
Detailed description of the invention
Fig. 1 is the memory circuit schematic diagram according to depicted in one embodiment of the invention；
Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A and 9A are painted Three Dimensional Memory body structure in one embodiment of the invention respectively and are making The top view in journey each stage；
Fig. 2 B, 3B, 4B, 5B, 6B, 7B, 8B and 9B are respectively Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A and 9A along AA ' hatching line Sectional view；
Fig. 6 C, 7C, 8C and 9C be respectively Fig. 6 A, 7A, 8A and 9A along BB ' hatching line sectional view；
Figure 10 A, 11A, 12A, 13A, 14A, 15A, 16A, 17A and 18A are painted in one embodiment of the invention three-dimensional note respectively Body structure is recalled in the top view in processing procedure each stage；
Figure 10 B, 11B, 12B, 13B, 14B, 15B, 16B, 17B and 18B be respectively Figure 10 A, 11A, 12A, 13A, 14A, 15A, 16A, 17A and 18A along AA ' hatching line sectional view；
Figure 14 C, 15C, 16C, 17C and 18C be respectively Figure 14 A, 15A, 16A, 17A and 18A along BB ' hatching line section Figure.
Specific embodiment
It is hereafter that appended attached drawing is cooperated to elaborate for embodiment, aspect to better understand the invention, but mentioned The embodiment of confession is not the range covered to limit this exposure, and the description of structure operation is non-to limit the suitable of its execution Sequence, it is all the range that this exposure is covered that any structure reconfigured by element is produced to have equal and other effects device. In addition, attached drawing is only mapped for the purpose of aiding in illustrating, and not according to full size, practical according to the standard and practice of industry The size of upper various features can be increased or decreased arbitrarily in order to illustrate.Similar elements will be with identical symbol in following the description Mark is illustrated in order to understanding.
The word (terms) used in full piece specification and claims usually has every in addition to having and especially indicating A word using in the content disclosed in this area, herein with the usual meaning in special content.It is certain to describe originally to take off The word of dew by it is lower or this specification other places discuss, to provide those skilled in the art in the description in relation to this exposure Additional guidance.
In addition, word "comprising", " comprising ", " having ", " containing " etc. used in herein, are open Term means " including but not limited to ".In addition, used herein " and/or ", comprising one or more in associated listed items Any one and its all combination of a project.
In this article, it when an element referred to as " connects " or " coupling ", can refer to " to be electrically connected " or " electric property coupling ". " connection " or " coupling " also can be used to indicate to be collocated with each other operation or interaction between two or multiple element.Although in addition, making herein With " first ", " second " ... wait terms to describe different elements, the term be only to distinguish with same technique term describe member Part or operation.It is indicated unless context understands, otherwise order or cis-position are not especially censured or implied to the term, also non-to limit The fixed present invention.
Please refer to Fig. 1.Fig. 1 is 100 schematic diagram of memory circuit according to depicted in one embodiment of the invention.Such as Fig. 1 institute Show, in one embodiment of the invention, memory circuit 100 include by a plurality of character line WL1, WL2~WLx and multiple bit lines BL1, BL2~BLx is formed by memory array.
In this memory array, the gate terminal of control switch SW1 is coupled to corresponding character line WL1, control switch SW1 Drain electrode end be coupled to corresponding bit line BL1.The source terminal of control switch SW1 is coupled to multiple memory unit layer S1~Sx.? In one embodiment of the invention, control switch SW1 can be by field-effect transistor (field-effect transistor, FET) or fin Shape field-effect transistor (FinFET) implementation.
It include multiple diode D1, multiple memory unit M1, multiple selection switch Q111~Q11x in memory unit layer S1 And a plurality of selection line SL111~SL11x.In structure, the first end (such as: anode tap) of diode D1 is coupled to control switch The source terminal of SW1, the second end (such as: cathode terminal) of diode D1 are coupled to the first end of corresponding memory unit M1.Memory is single The second end of first M1 is coupled to the first end of corresponding selection switch Q111~Q11x.
Similarly, as shown in Figure 1, also comprising multiple diode Dx, multiple memory unit Mx, multiple in memory unit layer Sx Select switch Q1x1~Q1xx and a plurality of selection line SL1x1~SL1xx.In structure, diode Dx in memory unit layer Sx, Connection relationship between memory unit Mx and selection line SL1x1~SL1xx is similar with corresponding element in memory unit layer S1, Therefore it is repeated no more in this.In addition, control switch SW2 is the control switch for being coupled to character line WL1 Yu bit line BL2, control switch SW3, SW4 are respectively the control switch for being coupled to character line WL2 Yu bit line BL1, BL2, the connection of corresponding memory unit Mode is similar to corresponding to the memory unit of control switch SW1, therefore repeats no more in this.
It is worth noting that, circuit depicted in Fig. 1 is only to release example to be used, and in some embodiments, memory circuit 100 can be the structure of multilayer multiple spot.It illustrates, y-th of the memory unit of xth layer memory unit layer Sx is electrically connected at selection and opens Qxy is closed, signal conduction or shutdown of the switch Qxy according to corresponding selection line SLxy are selected, wherein x, y are any positive integer.
Selection line SL111~SL1xx be respectively coupled to accordingly select switch Q111~Q1xx control terminal, respectively to Selection signal is received to determine whether selection switch Q111~Q1xx is connected, and cooperation character line WL1, WL2 and bit line BL1, BL2 chooses corresponding memory unit M1~Mx in memory array.In section Example of the present invention, memory unit M1~Mx It can be resistance-type memory body or phase-change memory, but be not limited thereto.
Memory circuit through more than, it is only necessary to which a control switch SW1 can control multiple memory unit layer S1~Sx In multiple memory unit M1~Mx can save space through the setting of Three Dimensional Memory body circuit, improve in unit area Memory capacity, and reduce processing procedure cost.
The specific processing procedure mode and memory structure of above-mentioned the memory circuit attached drawing that will arrange in pairs or groups in the following paragraphs are said It is bright, and illustrate that memory unit is arranged in the different fabrication steps and memory body knot of first layer metal layer below or above respectively Structure.Only it is the manufacturing process for being easier to understand Three Dimensional Memory body circuit of the present invention, is not painted selection switch in following drawings especially Qxxx selects switch Qxxx for transistor, can be completed at the same time when making control switch SWx, and the company with memory unit Mx Connecing mode also is known semiconductor technology.
Please refer to Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A and 9A, Fig. 2 B, 3B, 4B, 5B, 6B, 7B, 8B and 9B, with Fig. 6 C, 7C, 8C and 9C are to understand the preparation of the memory unit being configured at below first layer metal layer in Three Dimensional Memory body circuit of the invention Method.Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A and 9A are painted Three Dimensional Memory body structure in the top view in processing procedure each stage respectively, Fig. 2 B, 3B, 4B, 5B, 6B, 7B, 8B and 9B are respectively the section of Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A and 9A along AA ' hatching line Figure.Fig. 6 C, 7C, 8C and 9C be respectively Fig. 6 A, 7A, 8A and 9A along BB ' hatching line sectional view.For convenience, implement below Example is that memory circuit shown in collocation Fig. 1 is illustrated, but is not intended to limit the invention.
Firstly, being initially formed an active layers 120 (Active area) and 125 Yu Yiji of insulating layer as shown in Fig. 2A to Fig. 2 B On layer 110.Active region (Active area) 120 and insulating layer 125 can by light shield, light shield etching or even STI shallow trench every It is formed from various ways such as technologies (Shallow Trench Isolation, STI).
With continued reference to Fig. 3 A to Fig. 3 B, formed on a gate structure 130 to active layers 120.It in this step, is first to deposit Gate dielectric 132 is in active layers 120, and then redeposited gate electrode is on gate dielectric 132.In section Example In, the material of gate dielectric 132 includes silica, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, tantalum hafnium oxide, titanium oxide Hafnium, tantalum hafnium oxide, or combinations thereof.The material of gate electrode may include polysilicon, tungsten, aluminium, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, Copper, nickel, or combinations thereof.For example, in some embodiments, gate electrode may include polysilicon layer 134 and be located at polysilicon Silicide layer 136 on layer 134, the material of silicide layer 136 can be resistance value of the metal silicide to reduce gate electrode.
Then, it forms separation layer 138 to be located at the top of gate electrode and contact active layers 120, separation layer 138 and grid are situated between Electric layer 132 forms an enclosure space to coat gate electrode.In this way, gate structure can be formed in active layers 120 130.It is worth noting that, separation layer 138 and insulating layer 125 can identical or different material formed, when separation layer 138 with When insulating layer 125 is formed with different materials, there will be an interface between the two.In some embodiments, the material of insulating layer 125 Matter is the oxide of the material of active layers 120, and the material of separation layer 138 may include silica, silicon nitride, aluminium oxide and nitridation Aluminium, but not limited to this.In some embodiments, forming gate dielectric 132 and the mode of gate electrode may be, for example, physics Vapor deposition, chemical vapor deposition or atomic layer deposition, but not limited to this.
With continued reference to Fig. 4 A to Fig. 4 B, on depositing insulating layer 140 to base 110, separation layer 138 is covered.Then, removal portion The insulating layer 140 divided, to form the active layers 120 of a source contact openings 145 and expose portion.In section Example, herein It is that first photoresist layer (is not painted) on rotary coating to insulating layer 140 in step, exposure development is recycled (not draw a light shield Show) pattern be transferred on photoresist layer, with the insulating layer 140 of expose portion.Dry ecthing or wet etching processing procedure are used, finally with logical It crosses photoresist layer and removes the insulating layer 140 of part, and form source contact openings 145.In section Example of the invention, formed Photoresist layer is removed after source contact openings 145.
With continued reference to Fig. 5 A to Fig. 5 B, conducting medium 152 is filled in source contact openings 145, and on insulating layer 140 Form bottom plate 150.In section Example of the invention, the mode for forming bottom plate 150 may be, for example, physical vapour deposition (PVD), chemistry Vapor deposition or atomic layer deposition.
With continued reference to Fig. 6 A to Fig. 6 C, insulating layer 160 is formed on insulating layer 140 and bottom plate 150.Later, grinding insulation Layer 160 keeps a upper surface of insulating layer 160 and a upper surface of bottom plate 150 coplanar to enable.Implement in part of the invention It is that insulating layer 160 is ground with chemical mechanical milling method (chemical mechanical polishing, CMP) in example.Then, N type semiconductor layer 172, p type semiconductor layer 174 are formed on the upper surface of insulating layer 160 and bottom plate 150 sequentially to form two Pole pipe structure 170, and memory unit 180 is formed on diode structure 170.
Memory unit 180 can be by phase-change memory (Phase-Change Memory, PCM/Phase Change Random Access Memory, PCRAM) or resistance-type memory body (Resistive random-access memory, ) etc. RRAM/ReRAM implementation.For example, a pair of of metal-can be formed on diode structure 170 in some embodiments Insulator-Metal (MIM) structure forms resistance-type memory body, as memory unit 180.
In some embodiments, the material of the n type semiconductor layer 172 in diode structure 170 may be included in the 4th race member Element is as adulterated a small amount of impurity P elements or arsenic element in silicon crystal or germanium crystal.The material of p type semiconductor layer 174 may be included in A small amount of impurity boron element or aluminium element are adulterated in column IV element such as silicon crystal or germanium crystal.
In some embodiments, the material of diode structure 170 also may include three-five semiconductor such as aluminum phosphate, arsenic Aluminium, GaAs, gallium nitride adulterate a small amount of impurity such as selenium, tellurium, silicon, germanium, beryllium, zinc, cadmium, or with other this fields stakeholder institute Well known ternary or quaternary compound are respectively formed n type semiconductor layer 172 and p type semiconductor layer 174.
Then, memory unit 180, p type semiconductor layer 174 and the n type semiconductor layer for removing part are etched with light shield 172.In this step, it is that first photoresist layer (is not painted) on rotary coating to memory unit 180, recycles exposure development by one The pattern of light shield (not being painted) is transferred on photoresist layer.Dry ecthing or wet etching processing procedure are used, finally to remove by photoresist layer Partial n type semiconductor layer 172, p type semiconductor layer 174 and memory unit 180.
After the memory unit 180, p type semiconductor layer 174 and the n type semiconductor layer 172 that remove part, insulating layer is formed 190, and insulating layer 190 is ground, keep a upper surface of insulating layer 190 and a upper surface of memory unit 180 coplanar to enable. In this way, which the structure that multiple diode structures are one another in series with memory unit can be formed.Finally, with tungsten (W) or other Conductor forms conductive layer 185, and the conductive layer 185 of part is equally removed with light shield etching mode, in this way, can be mutual It is configured between vertical bottom plate 150 and conductive layer 185, is arranged multiple concatenated by diode structure 170 and memory unit 180 Memory cell.
With continued reference to Fig. 7 A to Fig. 7 C, it is iteratively repeated the step as shown in Fig. 6 A to Fig. 6 C, multilayer bottom plate can be formed 150, diode structure 170, memory unit 180 and conductive layer 185 stepped construction.Although it is worth noting that, Fig. 7 A extremely Two layers of memory unit layer, but the memory unit number in the number of plies of actually memory unit layer and each layer are depicted in Fig. 7 B It can be all adjusted according to actual demand.
Finally, please referring to Fig. 8 A to Fig. 8 C and Fig. 9 A to Fig. 9 C, the insulating layer of part is removed, to form a drain contact The active layers 120 of hole 195 and expose portion, and conducting medium 192 is filled in drain contact hole 195, finally in surface shape At first layer metal layer ML.In this way, which the memory list of Three Dimensional Memory body circuit can be formed below first layer metal layer ML First M1.In some embodiments, first layer metal layer ML is arranged to be generally parallel to each other with the conductive layer 185.
Please refer to Figure 10 A, 11A, 12A, 13A, 14A, 15A, 16A, 17A and 18A, Figure 10 B, 11B, 12B, 13B, 14B, 15B, 16B, 17B and 18B and Figure 14 C, 15C, 16C, 17C and 18C are configured with understanding in Three Dimensional Memory body circuit of the invention The preparation method of memory unit above first layer metal layer.Figure 10 A, 11A, 12A, 13A, 14A, 15A, 16A, 17A and 18A Three Dimensional Memory body structure is painted respectively in the top view in processing procedure each stage, Figure 10 B, 11B, 12B, 13B, 14B, 15B, 16B, 17B and 18B be respectively Figure 10 A, 11A, 12A, 13A, 14A, 15A, 16A, 17A and 18A along AA ' hatching line sectional view.Figure 14C, 15C, 16C, 17C and 18C be respectively Figure 14 A, 15A, 16A, 17A and 18A along BB ' hatching line sectional view.With previous reality It is similar to apply example, for convenience, following embodiment be collocation Fig. 1 shown in memory circuit be illustrated, but not to limit The present invention.
Firstly, as shown in Figure 10 A to Figure 10 B, be initially formed multiple active layers 220 (Active area) and insulating layer 225 in In one base 210.As shown in Figure 11 A to Figure 11 B, formed on a gate structure 230 to active layers 220.It in this step, is first Gate dielectric layer 232 is in active layers 220, and then redeposited gate electrode is on gate dielectric 232.For example, In some embodiments, gate electrode may include polysilicon layer 234 and the silicide layer 236 on polysilicon layer 234.It connects , it forms separation layer 238 and is located at the top of gate electrode and contacts active layers 220.In this way, can be in active layers 220 Form gate structure 230.
Then, such as Figure 12 A to Figure 12 B, after depositing insulating layer 240, the insulating layer 240 of part is removed, to form a drain electrode The active layers 220 of contact hole 245 and expose portion.The detail of above-mentioned steps is described in detail in preceding embodiment, therefore It is repeated no more in this.
With continued reference to Figure 13 A to Figure 13 B, conducting medium 252 is filled in drain contact hole 245, and in insulating layer 240 On by light shield etching in a manner of form metal layer bottom plate 250.
With continued reference to Figure 14 A to Figure 14 C, first layer metal layer ML is formed on metal layer bottom plate 250 and insulating layer.Such as figure Shown in 14A, from top view angle, it is staggered between first layer metal layer ML and active layers 220.It is considerable along AA hatching line Active layers 220 (as shown in Figure 14B) is observed, first layer metal layer ML (as shown in Figure 14 C) can be observed along BB hatching line.
In other words, as shown in Figure 13 A to Figure 13 B and Figure 14 A to Figure 14 B, in some embodiments, by metal layer bottom plate 250 with first layer metal layer ML formed metal-layer structures in, metal layer bottom plate 250 overlook it is in rectangular shape, through metal layer The first end of bottom plate 250 is connect with drain contact hole.First layer metal layer ML overlooks in long strip and big with metal layer bottom plate 250 It causes vertically, first layer metal layer ML is set on metal layer bottom plate 250, and is connect with the second end of metal layer bottom plate 250.
With continued reference to Figure 15 A to Figure 15 C, insulating layer 255 is continuously formed, and removes the insulating layer of part, is connect with forming one The active layers 220 of contact hole 260 and expose portion.Then, conducting medium 262 is filled in contact hole 260.With continued reference to figure 16A to Figure 16 C forms bottom plate 265 in a manner of light shield etching, so that bottom plate 265 is connect with contact hole 260 respectively.In part In embodiment, bottom plate 265 is arranged to substantially vertical with first layer metal layer ML.
After forming bottom plate 265, forms insulating layer 290 and cover bottom plate 265 at bottom plate 265, rear plane lapping is exhausted Edge layer 290 is to expose bottom plate 265, as shown in Figure 17 A to Figure 17 C, can sequentially form n type semiconductor layer on bottom plate 265 272, p type semiconductor layer 274 is to form diode structure 270, and 280 He of memory unit is formed on diode structure 270 Conductive layer 285.Wherein form the detail and previously described reality of diode structure 270, memory unit 280 and conductive layer 285 It applies similar in example, therefore is repeated no more in this.
Figure 18 A to Figure 18 C is finally please referred to, the step as shown in Figure 17 A to Figure 17 C is iteratively repeated, multilayer can be formed Bottom plate 265, diode structure 270, memory unit 280 and conductive layer 285 stepped construction.Although it is worth noting that, scheming Two layers of memory unit layer, but the memory list in the number of plies of actually memory unit layer and each layer are depicted in 18A to Figure 18 C First number can be all adjusted according to actual demand.In this way, which Three Dimensional Memory body can be formed above first layer metal layer ML The memory unit of circuit.
The processing procedure mode that (gate-first) is first made through above-mentioned grid, can form comprising active layers, gate structure, gold Belong to the memory structure of layer ML and multiple memory unit layers.
In some embodiments, memory structure of the invention includes transistor switch, insulation system, multiple memory units Layer and metal-layer structure.It includes gate structure, source electrode and drain electrodes for transistor switch.Insulation system covering transistor switch Over and around.It is electrically connected between metal-layer structure and the drain electrode of transistor switch with drain contact hole.Memory unit layer is set It is placed in above insulation system, and perpendicular stacking, wherein each memory unit layer respectively contains the source with the transistor switch The conductive soleplate that is electrically connected between pole with source contact openings, multiple diode structures on bottom plate, be located at it is described Multiple memory units on diode structure, and be located in memory unit, with conductive soleplate substantially at vertical arrangement Multiple conductive layers.
In structure, gate structure is located in active layers.It is electrically connected between metal layer ML and active layers with contact hole.Note Recall elementary layer S1~Sx perpendicular stacking each other, is respectively contained in each memory unit layer S1~Sx in being formed and connected on bottom plate Multiple diode structure D1 and multiple memory unit M1, and be electrically connected through contact hole and active layers.According to different systems Standby mode and memory structure, memory unit layer S1~Sx can be located at the below or above of metal layer ML.
In this way, Three Dimensional Memory body circuit as shown in Figure 1 can be formed by above-mentioned memory structure, through one Control switch can control multiple memory units in multiple memory unit layers, save space, improve the memory in unit area Capacity, and simplify the fabrication steps of Three Dimensional Memory body circuit, reduce processing procedure cost.
Although the present invention is disclosed above with embodiment, however, it is not to limit the invention, any to be familiar with this skill Person, without departing from the spirit and scope of the present invention, when can make it is various change and retouch, therefore protection scope of the present invention when view Subject to the scope of which is defined in the appended claims.

Claims (7)

1. a kind of memory circuit, characterized by comprising:
One transistor switch, it includes a gate structure, a source electrode and a drain electrode；
One insulation system covers the over and around of the transistor switch；
Multiple memory unit layers, the multiple memory unit layer is set to above the insulation system and perpendicular stacking, wherein institute Stating multiple memory unit layers each includes: with a source contact between a conductive soleplate, and the source electrode of the transistor switch Hole is electrically connected；Multiple diode structures are located on the conductive soleplate；Multiple memory units are located at the multiple two pole In pipe structure, the multiple memory unit connects one to one with the multiple diode structure；And multiple conductive layers, with this Conductive soleplate is corresponded and is set in the multiple memory unit at vertical arrangement；And
With drain contact hole electric connection between one metal-layer structure, and the drain electrode of the transistor switch.
2. memory circuit according to claim 1, which is characterized in that the metal-layer structure is located at the multiple memory Above elementary layer.
3. memory circuit according to claim 1, which is characterized in that the metal-layer structure is set to the multiple note Recall in the insulation system below elementary layer.
4. memory circuit according to claim 3, which is characterized in that the metal-layer structure includes:
One the first metal layer, vertical view is in rectangular shape, and a first end of the first metal layer is connect with the drain contact hole；
One second metal layer, vertical view is in long strip and vertical with the first metal layer, which is set to first gold medal Belong on layer, and is connect with a second end of the first metal layer.
5. memory circuit according to claim 1, which is characterized in that the transistor switch include a field-effect transistor or One fin-shaped field-effect transistor.
6. memory circuit according to claim 1, which is characterized in that the gate structure includes:
One gate dielectric；
One gate electrode is located on the gate dielectric；And
One separation layer, positioned at the top of the gate electrode, which coats the gate electrode.
7. memory circuit according to claim 1, which is characterized in that
The multiple memory unit each includes a phase-change memory or a resistance-type memory body；
The multiple diode structure each separately includes:
One n type semiconductor layer is located on the bottom plate；
One p type semiconductor layer is located on the n type semiconductor layer, contacts with corresponding memory unit layer.
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