CN106206310A - The manufacture method of rf-ldmos semiconductor device - Google Patents
The manufacture method of rf-ldmos semiconductor device Download PDFInfo
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- CN106206310A CN106206310A CN201510229694.0A CN201510229694A CN106206310A CN 106206310 A CN106206310 A CN 106206310A CN 201510229694 A CN201510229694 A CN 201510229694A CN 106206310 A CN106206310 A CN 106206310A
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Abstract
The invention provides the manufacture method of a kind of rf-ldmos semiconductor device, wherein manufacture method is included in the surface formation thick oxide layer of suprabasil gate surface and substrate；Etching thick oxide layer, forms field oxide, forms field plate material layer on field oxide, and field plate material layer includes the 3rd ramp, the 4th ramp and is connected to the 3rd ramp and the second connecting portion of the 4th ramp；Etch described field plate material layer.Rf-ldmos semiconductor device that the present invention provides and preparation method thereof includes the field plate material layer of the 3rd ramp, the 4th ramp by formation, the vertical dimension making the 3rd ramp and the 4th ramp distance field oxide layer is reduced, therefore, the follow-up etching to field plate material layer is more prone to, field plate in prior art can be avoided to etch the residual caused, thus the problem that threshold voltage shift occurs can be reduced.
Description
Technical field
The present invention relates to a kind of semiconductor device art, particularly relate to the oxidation of radio frequency lateral double diffused metal
The manufacture method of thing semiconductor device.
Background technology
In the design of rf-ldmos semiconductor device, in order to improve device
Breakdown voltage, the design of field plate is requisite.Field plate techniques is to improve pressure normal of device surface
By terminal technology, it can effectively reduce the surface field of reverse PN junction, improve the resistance to pressure energy of PN junction
Power.I.e. when the PN junction that surface is coated with field plate adds reverse biased, the some electrical power line of horizontal direction
The field plate of vertical direction will be terminated at, thus reduce the electric field intensity of horizontal direction, improve device
Breakdown characteristics.
Figure 1A-1B is the field of rf-ldmos semiconductor device of the prior art
Plate structure schematic diagram, as shown in Figure 1A, this device includes supporting substrate 101, grid 102, oxidation
Layer 103, in the prior art, in addition it is also necessary to form one layer of field on the surface of substrate 101 and grid 102
Plate 104, wherein, field plate 104 includes horizontal part 1041 and vertical component effect 1042, horizontal part 1041 He
Vertical component effect 1042 is mutually perpendicular to.Further, as shown in Figure 1B, field plate 104 be performed etching.
But, in the etching process of follow-up field plate 104, due to the thickness of the vertical component effect 1042 of field plate
Spend, namely vertical dimension H1 of the upper surface distance oxide layer 103 of field plate vertical component effect 1042 compares level
The thickness in portion 1041 is thick, therefore, during etching when horizontal part 1041 etch complete after,
But vertical component effect 1042 has not etched, therefore, it is easily created residual region 1043, residual
Region 1043 can cause the problems such as threshold voltage shift.
Summary of the invention
It is an object of the invention to provide the making side of rf-ldmos semiconductor device
Method, in order to easily to leave residual region on field plate during solving prior art etching field plate, causes
The problem of threshold voltage shift.
The invention provides the manufacture method of a kind of rf-ldmos semiconductor device,
Including: thick oxide layer is formed on the surface of suprabasil gate surface and described substrate；Etch described thickness
Oxide layer, forms field oxide, and described field oxide includes the first ramp, the second ramp and connection
In described first ramp and the connecting portion of described second ramp, described connecting portion is in described grid
Surface, described first ramp and described second ramp lay respectively at the both sides of described grid；Described
Field plate is formed on field oxide.
The manufacture method of the rf-ldmos semiconductor device that the present invention provides, passes through
Formed and include the first ramp, the field oxide of the second ramp, and further on the surface of field oxide
Formed and include the field plate material layer of the 3rd ramp, the 4th ramp so that the 3rd ramp and the 4th oblique
The vertical dimension of slope portion distance field oxide layer is reduced, and therefore, the follow-up etching to field plate material layer is more
Easily, field plate in prior art can be avoided to etch the residual caused, thus can reduce and threshold value electricity occurs
The problem of pressure drift.
Accompanying drawing explanation
Fig. 1 is the rf-ldmos quasiconductor in prior art with partial-pressure structure
The structural representation of device；
Fig. 2 is the making side of the rf-ldmos semiconductor device of the embodiment of the present invention
The flow chart of method；
The making rf-ldmos semiconductor device that Fig. 3 A-3E provides for the embodiment of the present invention two
The structural representation of each step of part.
Detailed description of the invention
Embodiment one
The present embodiment provides the manufacture method of a kind of rf-ldmos semiconductor device,
As in figure 2 it is shown, the rf-ldmos quasiconductor that Fig. 2 provides for the embodiment of the present invention
The flow chart of the manufacture method of device, the making of this rf-ldmos semiconductor device
Method, including:
Step 201, forms thick oxide layer on the surface of suprabasil gate surface and substrate.
Wherein, grid is chosen as polysilicon.
The generation type of thick oxide layer can be chemical gaseous phase deposition, specifically can use low pressure, normal pressure or
Person's plasma activated chemical vapour deposition.In order to form comparatively dense thick oxide layer, preferably low pressure chemical
Vapour deposition thick oxide layer.
Step 202, etches thick oxide layer, forms field oxide.
Wherein, field oxide includes the first ramp, the second ramp and is connected to the first ramp and
First connecting portion of two ramp, the first connecting portion in the surface of grid, the first ramp and second oblique
Slope portion lays respectively at the both sides of grid.
Step 203, forms field plate material layer on field oxide.
Concrete, the surface that chemical gaseous phase can be used to be deposited on field oxide forms field plate material layer, because of
The shape of this field plate material layer is similar to the shape of field oxide, on the spot the sheet material bed of material include the 3rd ramp,
4th ramp and be connected to the 3rd ramp and the second connecting portion of the 4th ramp, wherein, the 3rd is oblique
Slope portion is positioned at the first ramp surface of field oxide, and the 4th ramp is positioned at the second slope of field oxide
Surface, portion, the second connection portion is positioned at the first connecting portion surface of field oxide.
Step 204, etches field plate material layer, forms field plate.
In the manufacture method of the rf-ldmos semiconductor device of the present embodiment, pass through
Formed and include the first ramp, the field oxide of the second ramp, and further on the surface of field oxide
Formed and include the field plate material layer of the 3rd ramp, the 4th ramp so that the 3rd ramp and the 4th oblique
The vertical dimension of slope portion distance field oxide layer is reduced, wherein it should be noted that vertical dimension refers to
The upper surface of three ramp or the 4th ramp is to the vertical dimension of field oxide upper surface, therefore, follow-up
The etching of field plate material layer is more prone to, field plate in prior art can be avoided to etch the residual caused,
Thus the problem that threshold voltage shift occurs can be reduced.
Embodiment two
As shown in Fig. 3 A to 3E, Fig. 3 A-3E is for making rf-ldmos quasiconductor
The structural representation of each step of device, the present embodiment is also the further supplementary notes to above-described embodiment.
As shown in Figure 3A, grid 2 surface on the base 1 and the surface formation thick oxide layer of substrate 1
3。
Wherein, substrate 1 includes substrate 11, body district 12, source region 13, drift region 14, drain region 15, grid
Oxide layer 16, wherein substrate 11 is silicon substrate, doped with impurity in silicon substrate, impurity can be antimony or
Arsenic.Substrate 11, body district 12, source region 13, drift region 14, drain region 15, the formation of gate oxide 16
Mode is prior art, does not repeats them here.Thick oxide layer 3 is to be existed by chemical gaseous phase formation of deposits
In substrate 1, optionally, compared with prior art, the thickness of the thick oxide layer of such as prior art is
1500 angstroms, then the thick oxygen of the rf-ldmos semiconductor device provided in the present embodiment
The thickness changing layer 3 is 3000 angstroms-5000 angstroms, but thickness is not limited to this, and concrete thickness can basis
Actual device requirement and make change, as long as ensureing the 2-3 that thickness is prior art of this thick oxide layer 3
Times can be in order to after thick oxide layer 3 performs etching by next step, it is ensured that by the thick oxygen of etching
Change the thickness of the field oxide that layer is formed.
Further, as shown in Figure 3 B, etch thick oxide layer 3, form field oxide 4.
Wherein, the concrete mode of field oxide 4 is formed for being 100-300 millitorr in vacuum, magnetic field 20-40
Thick oxide layer 3 is etched under conditions of Gauss.Concrete, etching thick oxide layer 3 also needs to add etching gas
Body and noble gas, concrete etching gas can select according to the material of thick oxide layer 3, such as,
If thick oxide layer 3 is silicon oxide, then etching gas can use fluoroform, carbon tetrafluoride etc., wherein
The flow of etching gas is chosen as 30-80 ml/min, and the amount of etching gas is not suitable for excessive, otherwise holds
Easily the oxide layer on substrate 1 surface being etched away, the etch period of etching thick oxide layer 3 is 20 seconds-80 seconds.
Noble gas is chosen as argon, and flow is 40-150 ml/min.
Field oxide 4 includes first ramp the 41, second ramp 42 and is connected to the first ramp
41 and second first connecting portion 43 of ramp 42, the first connecting portion 43 is positioned at the surface of grid 2, and
One ramp 41 and the second ramp 42 lay respectively at the both sides of grid 2.Wherein, the first ramp 41,
First connecting portion 43 and the second ramp 42 length in the horizontal direction are equal with the length of substrate 1.
As shown in Figure 3 B, the first ramp 41 includes the first horizontal part 410 and the first vertical portion 411, the
Two ramp 42 include the second vertical portion 421 and the second horizontal part 422.First horizontal part 410 and
Two horizontal parts 422 are the part parallel with substrate 1, and the first vertical portion 411 is connected to the first horizontal part 410
With first between connecting portion 43, the second vertical portion 421 is connected to the second horizontal part 422 and the second connecting portion
Between 43.More specifically, the first vertical portion 411 away from grid 2 side be shaped as arc, arc
The direction of shape bending is the direction away from grid 2, and equally, the second vertical portion 422 is away from the one of grid 2
The shape of side is also arc, and the direction of arc-shaped bend is also the direction away from grid 2.
As shown in Figure 3 C, chemical gaseous phase is used to be deposited on field oxide 4 formation field plate material layer 5, can
Selection of land, field plate material layer 5 be polysilicon, tungsten silicide, titanium any one, thickness is at 800 angstroms to 3000
Between angstrom, field plate material layer 5 includes the 3rd ramp the 51, the 4th ramp 52 and to be connected to the 3rd oblique
Slope portion 51 and the second connecting portion 53 of the 4th ramp 52, wherein, owing to field plate material layer 5 is to use
Chemical gaseous phase formation of deposits, the 3rd rake the 51, the 4th rake 52 and the thickness of the second connecting portion
Degree is equal, and therefore the shape of field plate material layer 5 is similar to the shape of field oxide 4.
Additionally, due to field plate material layer 5 and grid 2 are all conductors, if field plate material layer 5 and grid 2
Contact then can cause short circuit, and therefore the first connecting portion 43 is possible to prevent between field plate material layer 5 and grid 2
Short circuit, further, owing to gate oxide 16 is the thinnest, be not enough to insulated field plate material layer 5 He
Source region 13, drift region 14 and drain region 15 under gate oxide 16, therefore, the first horizontal part 44 and
Two horizontal parts 45 are possible to prevent the source region 13 below field plate material layer 5 and gate oxide 16, drift region 14
The short circuit caused is connected with drain region 15.Additionally, need strict control to etch bar when forming field oxide 4
Part, prevents first connecting portion the 43, first horizontal part the 410, second horizontal part 422 to be etched away.
Wherein, the 3rd rake 51 also includes the 3rd vertical portion 511 and the 3rd horizontal part 510, and the 4th inclines
Tiltedly portion 52 includes bending section 521 and the 4th horizontal part 520, the 3rd horizontal part 510 and the 4th horizontal part 520
For the part parallel with substrate 1, the 3rd vertical portion 511 is connected to the 3rd horizontal part 510 and second and connects
Between portion 53, bending section 521 is connected between the 4th horizontal part 520 and the second connecting portion 53, more
For concrete, the 3rd vertical portion 511 away from grid 2 side be shaped as arc, the side of arc-shaped bend
To for the direction away from grid 2, equally, bending section 521 is also arc away from the shape of the side of grid 2
Shape, the direction of arc-shaped bend is also the direction away from grid 2.Wherein, the 3rd vertical portion 511, bending
The shape in portion 521 can be arc as shown in Figure 3 C, can be triangle (not shown), or
Person is fan-shaped (not shown), and above shape all can guarantee that the 3rd vertical portion 511 of field plate material layer 5
And vertical dimension H of bending section 521 distance field oxide layer 4 is than field plate vertical component effect 1024 in prior art
Vertical dimension H1 of distance oxide layer 103 little, certain 3rd vertical portion 511 and bending section 521 also may be used
Think that other can reduce the shape of vertical dimension H, will not enumerate at this.Wherein, carve due to dry method
Etching technique is anisotropic, therefore when etching field oxide 4 by vertical for the first vertical portion 411 second
Portion 421 etching is easiest to for arc, namely the 3rd vertical portion 511 and bending section 521 be shaped as arc
Requirement for technique is the simplest, it is preferred, therefore, that the 3rd vertical portion 511 and the shape of bending section 521
Shape is arc.
As shown in Fig. 3 D-3E, etch field plate material layer, form field plate.
Concrete, as shown in Figure 3 D, the sheet material bed of material 5 on the scene forms photoresist layer 6, photoresist layer 6
One end be positioned at the top of grid 2, the other end of photoresist layer 6 is positioned at the side of grid 2, wherein,
Photoresist layer 6 is the photoresist layer after exposure imaging.Further, as shown in FIGURE 3 E, to field plate
Material layer 5 performs etching, and forms the field plate 50 with bending section 521, finally, removes photoresist layer 6.
In the manufacture method of the rf-ldmos semiconductor device that the present embodiment provides,
The field oxide 4 of first ramp the 41, second ramp 42, and further oxygen on the scene is included by formation
The surface changing layer 4 forms the field plate material layer 5 including the 3rd ramp the 51, the 4th ramp 52 so that
The vertical dimension of the 3rd ramp 51 and the 4th ramp 52 distance field oxide layer is reduced, and therefore, makes
Obtain follow-up field plate etching to be more prone to, field plate in prior art can be avoided to etch the residual caused, because of
And the problem that threshold voltage shift occurs can be reduced.
Embodiment three
The present embodiment also provides for a kind of rf-ldmos semiconductor device, this device
As shown in FIGURE 3 E, the rf-ldmos semiconductor device that the present embodiment provides can for structure
The making side of the rf-ldmos semiconductor device to be provided according to above-described embodiment
Method makes, and in this not go into detail, refers to for rf-ldmos half
The description of the manufacture method of conductor device.
In the rf-ldmos semiconductor device that the present embodiment provides, owing to field plate is
By including the 3rd ramp the 51, the 4th ramp 52 and being connected to the 3rd ramp 51 and the 4th ramp
Field plate material layer 5 etching of second connecting portion 53 of 52 forms, it therefore reduces make field plate 7
Etching difficulty, it is to avoid in prior art, field plate etches the residual caused, thus can reduce and come across generation
The problem of voltage drift, improves performance and the output yield of device.
Last it is noted that above example is only in order to illustrate technical scheme, rather than to it
Limit；Although the present invention being described in detail with reference to previous embodiment, the ordinary skill of this area
Personnel it is understood that the technical scheme described in foregoing embodiments still can be modified by it, or
Person carries out equivalent to wherein portion of techniques feature；And these amendments or replacement, do not make corresponding skill
The essence of art scheme departs from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (7)
1. the manufacture method of a rf-ldmos semiconductor device, it is characterised in that
Including:
Thick oxide layer is formed on the surface of suprabasil gate surface and described substrate；
Etch described thick oxide layer, form field oxide, described field oxide include the first ramp, the
Two ramp and be connected to described first ramp and the first connecting portion of described second ramp, described the
A junction is positioned at the surface of described grid, described first ramp and described second ramp and lays respectively at
The both sides of described grid；
On described field oxide formed field plate material layer, described field plate material layer include the 3rd ramp,
4th ramp and be connected to described 3rd ramp and the second connecting portion of the 4th ramp；
Etch described field plate material layer, form field plate.
The making of rf-ldmos semiconductor device the most according to claim 1
Method, it is characterised in that described formation field oxide includes:
It is 100-300 millitorr in vacuum, under conditions of the 20-40 Gauss of magnetic field, etches described thick oxide layer.
The making of rf-ldmos semiconductor device the most according to claim 1
Method, it is characterised in that the thickness of described thick oxide layer is 3000 angstroms-5000 angstroms.
The making of rf-ldmos semiconductor device the most according to claim 1
Method, it is characterised in that the etch period etching described thick oxide layer is 20 seconds-80 seconds.
The making of rf-ldmos semiconductor device the most according to claim 1
Method, it is characterised in that described first ramp, described first connecting portion and described second ramp exist
Length in horizontal direction is equal with the length of described substrate.
6. according to the rf-ldmos quasiconductor according to any one of claim 1-5
The manufacture method of device, it is characterised in that described etching described field plate material layer, forms field plate and includes:
Forming photoresist layer on described field plate material layer, one end of described photoresist layer is positioned at described grid
Top, the other end of described photoresist layer is positioned at the side of described grid；
Described field plate material layer is performed etching, forms the field plate with bending section；
Remove described photoresist layer.
The making of rf-ldmos semiconductor device the most according to claim 1
Method, it is characterised in that described field plate be polysilicon, tungsten silicide, titanium any one.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510229694.0A CN106206310A (en) | 2015-05-07 | 2015-05-07 | The manufacture method of rf-ldmos semiconductor device |
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| CN201510229694.0A CN106206310A (en) | 2015-05-07 | 2015-05-07 | The manufacture method of rf-ldmos semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899281A (en) * | 2018-06-20 | 2018-11-27 | 上海华虹宏力半导体制造有限公司 | The preparation method of lateral diffusion metal oxide semiconductor |
| CN113972265A (en) * | 2020-07-23 | 2022-01-25 | 和舰芯片制造(苏州)股份有限公司 | Method for improving LDMOS (laterally diffused metal oxide semiconductor) process technology of strip field plate |
| CN115497830A (en) * | 2022-11-21 | 2022-12-20 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device and semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1819270A (en) * | 2005-02-10 | 2006-08-16 | 恩益禧电子股份有限公司 | Field-effect transistor and method of manufacturing a field-effect transistor |
| CN102569381A (en) * | 2010-12-07 | 2012-07-11 | 上海华虹Nec电子有限公司 | LDMOS structure with shield grid and preparation method thereof |
-
2015
- 2015-05-07 CN CN201510229694.0A patent/CN106206310A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1819270A (en) * | 2005-02-10 | 2006-08-16 | 恩益禧电子股份有限公司 | Field-effect transistor and method of manufacturing a field-effect transistor |
| CN102569381A (en) * | 2010-12-07 | 2012-07-11 | 上海华虹Nec电子有限公司 | LDMOS structure with shield grid and preparation method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899281A (en) * | 2018-06-20 | 2018-11-27 | 上海华虹宏力半导体制造有限公司 | The preparation method of lateral diffusion metal oxide semiconductor |
| CN113972265A (en) * | 2020-07-23 | 2022-01-25 | 和舰芯片制造(苏州)股份有限公司 | Method for improving LDMOS (laterally diffused metal oxide semiconductor) process technology of strip field plate |
| CN113972265B (en) * | 2020-07-23 | 2023-07-04 | 和舰芯片制造(苏州)股份有限公司 | Method for improving LDMOS (laterally diffused metal oxide semiconductor) manufacturing process with field plate |
| CN115497830A (en) * | 2022-11-21 | 2022-12-20 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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Application publication date: 20161207 |