JP2010141028A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the yield and reliability of a semiconductor device having a trench MOSFET gate. <P>SOLUTION: An isotropic nature of etching can be enhanced by using SF<SB>6</SB>, a fluoride gas, as an etching gas in processing a gate electrode 9a, and the surface of the gate electrode 9a can be smoothly processed and the product yield and reliability can be improved. Furthermore, by keeping the temperature of an n<SP>+</SP>type single crystal silicon substrate 1 at 5°C in processing the gate electrode 9a, the reattachment of an etching residue to the processed surface can be prevented, and by making the shape of the processed surface smooth, the yield and reliability of the trench gate MOSFET can be improved. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to the manufacture of a semiconductor device having a trench gate type MOSFET.

  In the field of power electronics, high voltage semiconductor devices are increasingly used with the miniaturization of devices, and accordingly, higher voltage resistance and higher current are desired for high voltage semiconductor devices. Examples of the structure for increasing the breakdown voltage include trench gate type MOSFRET (Metal Oxide Semiconductor Field Effect Transistor).

In etching for processing the gate electrode of a power MOSFET such as a trench gate type MOSFET, a highly anisotropic microwave etcher is generally used, and Cl ₂ gas and O ₂ gas are generally used as etching gases.

JP-A-2005-286055 (Patent Document 1), manufacturing technology of trench gate type power MOSFET is disclosed having a step of performing dry etching using _SF 6 + the He-based gas in the etch-back process when a gate electrode formed Has been.

Japanese Patent Laying-Open No. 2005-286056 (Patent Document 2) discloses a technique for manufacturing a trench gate type power MOSFET having a process of performing dry etching using SF ₆ + He-based gas in an etch back process when forming a gate electrode. Has been.

Japanese Patent Application Laid-Open No. 2007-31547 (Patent Document 3) discloses a trench gate type power having a process of performing CDE (Chemical Dry Etching) using a mixed gas of CF ₄ and O ₂ in an etch back process when forming a gate electrode. A MOSFET manufacturing technique is disclosed.
JP 2005-286055 A JP 2005-286056 A JP 2007-311547 A

In the trench gate type MOSFET manufactured by the above-described conventional technique, when the poly-Si film as a gate material is etched back with Cl ₂ gas or Cl ₂ + O ₂ gas, the surface of the poly-Si film is poly-Si. It becomes uneven due to the influence of the grains constituting the film, which causes a decrease in yield and quality. As a countermeasure against this, the present inventors have examined the isotropic property of dry etching when the gate electrode of the trench gate type MOSFET is etched back.

  Further, when a low-temperature semiconductor substrate is etched, a residue of the photoresist film, a reaction product, or the like adheres to the processed surface, and the processed surface becomes uneven. As a result, the distance between the gate electrode having an uneven surface and the conductive film such as the upper metal wiring or other gate electrode disposed via the insulating film is narrowed. There is a problem that the withstand voltage between the gate electrode having an uneven surface decreases and the yield decreases.

  An object of the present invention is to provide a technique capable of smoothly processing the surface of a Poly-Si film, which is a gate electrode material of a trench gate type MOSFET, and improving the yield and reliability of a product.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of one embodiment of a representative one will be briefly described as follows.

A manufacturing method of a semiconductor device according to an embodiment of the present invention includes:
A method of manufacturing a semiconductor device having a trench gate type MOSFET,
(A) a step of preparing a semiconductor substrate;
(B) forming a vertical groove on the main surface of the semiconductor substrate;
(C) a step of forming an oxide film on the surface of the groove after the step (b);
(D) After the step (c), a step of forming a Poly-Si film as a gate electrode material on the main surface including the inside of the trench;
(E) After the step (d), the Poly-Si film is etched back by dry etching, and a gate electrode of the trench gate type MOSFET is formed in the trench.
(F) forming a source region on the main surface of the semiconductor substrate;
(G) forming a drain electrode on the back surface of the semiconductor substrate;
Including
In the step (e), a gas mainly composed of SF ₆ gas is used as an etching gas, and the temperature of the semiconductor substrate during etching is set to 5 ° C. or higher.

The effects obtained by one embodiment of the invention disclosed in this application will be briefly described as follows. When dry etching a poly-Si film as a gate electrode material, SF ₆ gas By using a gas mainly composed of as an etching gas, the isotropy of etching can be enhanced and the surface of the gate electrode can be processed smoothly.

  Further, by setting the temperature of the semiconductor substrate at the time of processing the gate electrode to 5 ° C., it is possible to prevent the etching residue from reattaching to the processing surface and to make the processing surface smooth.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. In addition, when referring to the constituent elements in the embodiments, etc., “consisting of A” and “consisting of A” do not exclude other elements unless specifically stated that only the elements are included. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In addition, when referring to materials, etc., unless specified otherwise, or in principle or not in principle, the specified material is the main material, and includes secondary elements, additives It does not exclude additional elements. For example, unless otherwise specified, the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (for example, SiGe) having silicon as a main element.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  In the drawings used in the following embodiments, even a plan view may be partially hatched to make the drawings easy to see.

(Embodiment 1)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present embodiment is applied to a method for manufacturing a trench gate type n-channel power MOSFET, and will be described with reference to FIGS.

First, as shown in FIG. 1, the impurities (e.g. As (arsenic)) is heavily doped n ⁺ type single crystal silicon substrate (semiconductor substrate) 1 on the main surface of n-conductivity type, CVD An n ⁻ type epitaxial layer 2 is deposited by a method, and an oxide film 3 is formed on the n ⁻ type epitaxial layer 2 by a thermal oxidation method. Thereafter, a p-type impurity (for example, B (boron)) is implanted into the n ⁻ -type epitaxial layer 2 by ion implantation, and then thermal diffusion is performed to form the p-type impurity diffusion layer 4. The n ⁺ type single crystal silicon substrate 1 becomes the drain of the vertical MOSFET.

Next, as shown in FIG. 2, an impurity having an n-type conductivity (for example, P (phosphorus)) is implanted at a high concentration into the p-type impurity diffusion layer 4 by ion implantation. The implantation conditions at this time are set to, for example, an ion acceleration energy of 40 keV, a dose amount of 5 × 10 ¹⁵ atoms / cm ² , and an implantation angle of 7 °. Thereafter, when thermal diffusion is performed, an n ⁺ -type impurity diffusion layer 5 is formed in the p-type impurity diffusion layer 4. The n ⁺ -type impurity diffusion layer 5 becomes the source of the vertical MOSFET.

  Next, as shown in FIG. 3, a mask material (for example, silicon nitride) 6 is deposited on the oxide film 3 by a CVD (Chemical Vapor Deposition) method. Further, a resist pattern (not shown) patterned by a photolithography technique is formed on the mask material 6, and the mask material 6 is etched by RIE (Reactive Ion Etching) using the resist pattern as a mask. Thereafter, the resist pattern is removed.

Subsequently, as shown in FIG. 4, the mask material 6 as a mask, oxide film 3 and n By RIE ^- etching the type epitaxial layer 2. As a result, a trench 7 is formed in the n ⁻ type epitaxial layer 2. This etching is performed until the trench 7 penetrates the p-type impurity diffusion layer 4 and the n ⁺ -type impurity diffusion layer 5 and the bottom thereof reaches the n ⁻ -type epitaxial layer 2.

Thereafter, sacrificial oxidation is performed at a temperature of about 950 ° C. in an H ₂ atmosphere, and damage (crystal defects and the like) generated in the n ⁻ type epitaxial layer 2 due to the formation of the trench 7 is recovered.

Next, as shown in FIG. 5, a gate oxide film 8 is formed on the inner surface of the trench 7 by thermal oxidation. At this time, since the mask material 6 that does not transmit oxygen atoms is disposed on the n ⁻ type epitaxial layer 2, the gate oxide film 8 is formed only on the surface of the trench 7.

  Next, as shown in FIG. 6, after removing the mask material 6, a conductive Poly containing impurities (for example, As (arsenic)) in the trench 7 and on the oxide film 3 by LPCVD (Low Pressure CVD) method. A Si film 9 is deposited. In addition, after a resist film is applied on the Poly-Si film 9, a resist pattern 10 patterned by a photolithography technique is formed.

Next, as shown in FIG. 7, the temperature of the ^{n +} type single crystal silicon substrate 1 under conditions that 5 ° C., the resist pattern 10 as a mask, by RIE using a gas mainly composed of SF ₆ POLY- The Si film 9 is etched back to form gate electrodes 9a and 9b made of a Poly-Si film 9 in the trench 7, and then the resist pattern 10 is removed.

Here, in general, Cl ₂ + O ₂ gas is mainly used as an etching gas at the time of gate processing. In this case, etching is performed on the gate electrode as in the surface of the gate electrode 9a of the trench gate type MOSFET shown in FIG. Influenced by the grain shape of the poly-Si material, the processed surface becomes uneven, causing a reduction in yield and quality.

In the present embodiment, SF ₆ that is a fluorine-based gas is used as an etching gas to enhance the isotropy of etching, and the gate electrode 9a is not affected by the shape of the poly-Si grain of the gate electrode material. Can be processed smoothly. As a result, it is possible to prevent local disappearance of Poly-Si on the surface of the gate electrode 9a in the downstream process, and to improve the yield and reliability of the product.

  Further, in the gate electrode processing step, the semiconductor substrate is often processed at a low temperature such as −40 ° C. When the semiconductor substrate is etched at a low temperature, a photoresist is formed as shown in FIG. The reaction product 20 consisting of a film and a residue of Poly-Si is redeposited on the surfaces of the gate oxide film 8 and the gate electrode 9b, and the processing surface becomes uneven without etching progressing uniformly. At this time, the reaction product 20 adhered to the side surface of the gate electrode 9b reduces the thickness of the interlayer insulating film 11 on the gate electrode 9b, and the gate electrode 9b and the metal film 15 deposited on the interlayer insulating film 11 As a result, the withstand voltage of the trench gate type MOSFET decreases, the performance of the trench gate type MOSFET decreases, and the yield decreases.

In this embodiment, by setting the temperature of the n ⁺ type single crystal silicon substrate 1 at the time of processing the gate electrode to 5 ° C., the etching residue is prevented from reattaching to the processing surface, and the processing surface is made into a smooth shape. As a result, the yield and the reliability of the trench gate type MOSFET can be improved.

  Next, as shown in FIG. 8, an interlayer insulating film (for example, silicon oxide film) 11 that completely covers the Poly-Si film 9 in the trench 7 is deposited on the oxide film 3 by CVD, and is deposited thereon. After applying the resist film, a resist pattern 12 patterned by a photolithography technique is formed.

  Next, as shown in FIG. 9, the interlayer insulating film 11 is etched by isotropic etching such as CDE (Chemical Dry Etching) using the resist pattern 12 as a mask. As a result, a trench 13a is formed in the interlayer insulating film 11 so as to enter the lower part of the resist pattern 12 and having a curved side surface.

Subsequently, using the resist pattern 12 as a mask, the n ⁻ type epitaxial layer 2 is etched by RIE, thereby forming a trench 13 b in the n ⁻ type epitaxial layer 2. This etching is performed until the trench 13 b penetrates the n ⁺ -type impurity diffusion layer 5 and the bottom reaches the p-type impurity diffusion layer 4. However, the bottom of the trench 13b is, n ^- it is necessary to avoid reaching -type epitaxial layer 2.

Next, as shown in FIG. 10, a p-type impurity (for example, BF ₂ ) is implanted into the p-type impurity diffusion layer 4 in the n ⁻ -type epitaxial layer 2 by ion implantation using the resist pattern 12 as a mask. . The implantation conditions at this time are set to, for example, an ion acceleration energy of 35 keV, a dose of 1.0 × 10 ¹⁵ atoms / cm ² , and an implantation angle of 0 °.

Here, the reason for setting the implantation angle (angle with respect to the vertical line of the surface of the n ⁺ type single crystal silicon substrate 1) to 0 ° is that the impurity concentration of the n ⁺ type impurity diffusion layer 5 exposed on the side surface of the trench 13b is thin. This is to prevent the conductivity type from being reversed.

Thereafter, thermal diffusion is performed to form a p ⁺ -type contact layer 14 in the p-type impurity diffusion layer 4, and then the resist pattern 12 is removed.

Next, as shown in FIG. 11, a metal film (for example, aluminum) 15 that completely fills the trenches 13a and 13b is deposited on the interlayer insulating film 11 by LPCVD. Then, the metal film 15 is patterned to form a source electrode of the vertical MOSFET (not shown). Further, a part of the interlayer insulating film 11 is removed, and a gate pad (not shown) is exposed. After washing the n ⁺ type single crystal silicon substrate 1, depositing a metal film made of Au (gold) on the rear surface of the n ⁺ type single crystal silicon substrate 1. Subsequently, the metal film is wet-etched to form the back electrode 16, thereby completing the trench gate type MOSFET. The back electrode 16 serves as the drain electrode of the trench gate type MOSFET.

(Embodiment 2)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present embodiment is applied to a method of manufacturing a trench gate type n-channel power MOSFET having a dummy gate, and will be described with reference to FIGS.

First, as shown in FIG. 13, CVD is performed on the main surface of an n ⁺ type single crystal silicon substrate (semiconductor substrate) 31 doped with an n-type impurity (for example, As (arsenic)) at a high concentration. After the n ⁻ type epitaxial layer 32 is deposited by the method, a p type impurity (for example, B) is injected into the n ⁻ type epitaxial layer 32 by the ion implantation method, and then thermal diffusion is performed. Form. The n ⁺ type single crystal silicon substrate 31 becomes the drain of the vertical MOSFET.

Next, as shown in FIG. 14, an impurity (for example, P) having an n-type conductivity is implanted at a high concentration into the p-type impurity diffusion layer 33 by ion implantation. The implantation conditions at this time are set to, for example, an ion acceleration energy of 40 keV, a dose amount of 5 × 10 ¹⁵ atoms / cm ² , and an implantation angle of 7 °. Thereafter, when thermal diffusion is performed, an n ⁺ -type impurity diffusion layer 34 is formed in the p-type impurity diffusion layer 33. The n ⁺ type impurity diffusion layer 34 becomes a source of the vertical MOSFET.

  Next, as shown in FIG. 15, a mask material (for example, silicon nitride) 35 is formed on the p-type impurity diffusion layer 33 by the CVD method. Further, a resist pattern (not shown) patterned by the photolithography technique is deposited on the mask material 35, and the mask material 35 is etched by RIE using the resist pattern as a mask. Thereafter, the resist pattern is removed.

Subsequently, as shown in FIG. 16, the n ⁻ type epitaxial layer 32 is etched by RIE using the mask material 35 as a mask. As a result, a trench 36 is formed in the n ⁻ type epitaxial layer 32. This etching trenches 36 penetrates the p-type impurity diffusion layer 33 and n ⁺ -type impurity diffusion layer 34, its bottom the n ^- are performed until the type epitaxial layer 32.

Thereafter, sacrificial oxidation at a temperature of about 950 ° C. is performed in an H ₂ atmosphere to recover damage (such as crystal defects) generated in the n ⁻ -type epitaxial layer 32 due to the formation of the trench 36, and then the mask material 35 is removed. To do.

  Next, as shown in FIG. 17, an oxide film 37 is formed on the inner surface of the trench 36 and on the p-type impurity diffusion layer 33 by thermal oxidation.

  Next, as shown in FIG. 18, a conductive Poly-Si film 38 containing impurities (for example, As) is deposited in the trench 36 and on the oxide film 37 by LPCVD.

Next, as shown in FIG. 19, the Poly-Si film 38 is formed in the trench 36 by RIE using a gas mainly composed of SF ₆ under the condition that the temperature of the n ⁺ type single crystal silicon substrate 31 is 5 ° C. The dummy gate electrode 39 made of the Poly-Si film 38 is formed in the trench 36 by etching back to a distance of 1 μm from the bottom of the trench. Thereafter, oxide film 40 is formed on the surface of oxide film 37 and on dummy gate electrode 39 by thermal oxidation.

  Next, as shown in FIG. 20, a conductive Poly-Si film 41 containing an impurity (for example, As) is deposited on the oxide film 40 by LPCVD.

Next, as shown in FIG. 21, the Poly-Si film 41 is etched back by RIE using a gas mainly composed of SF ₆ under the condition that the temperature of the n ⁺ -type single crystal silicon substrate 31 is 5 ° C. Then, the gate electrode 42 made of the Poly-Si film 41 is formed on the oxide film 40 in the trench 36.

Here, FIG. 23 shows a main part of a trench gate type MOSFET formed by using an etching gas mainly composed of Cl ₂ + O ₂ gas at the time of processing the gate electrode and processing the temperature of the semiconductor substrate at −40 ° C. Since the gate electrode formed under this condition is processed by etching with strong anisotropy by using an etching gas mainly composed of Cl ₂ + O ₂ gas, the surface of the dummy gate electrode 39 is a dummy. It becomes uneven by being affected by the grain of Poly-Si which is a gate electrode material. For this reason, the thickness of the oxide film 40 between the dummy gate electrode 39 and the gate electrode 42 is not uniform, and the breakdown voltage between the dummy gate electrode 39 and the gate electrode 42 decreases. Further, like the surface of the gate electrode 42, the etching is affected by the shape of the poly-Si grain of the gate electrode material, the processed surface becomes uneven, and the local disappearance of the poly-Si on the surface of the gate electrode 42 occurs. Therefore, it becomes a factor of a decrease in yield and quality.

  In addition, by performing the gate electrode processing at a low temperature of −40 ° C. or the like, the reaction product 50 composed of a photoresist film or a poly-Si residue is formed on the surface of the oxide film 40 or the gate electrode 42. Re-adhering, etching does not proceed evenly, and the processed surface becomes uneven. At this time, the reaction product 50 adhering to the upper surfaces of the oxide film 40 and the gate electrode 42 lowers the breakdown voltage between the gate electrode 42 and the metal film 46 deposited on the interlayer insulating film 43, thereby forming a trench gate type. The performance of the MOSFET is lowered and the yield is lowered.

In the present embodiment, as in the first embodiment, by using SF ₆ which is a fluorine-based gas as an etching gas, the isotropicity of etching is strengthened, and the shape of a poly-Si grain as a gate electrode material is obtained. The surface of the dummy gate electrode 39 and the gate electrode 42 can be processed smoothly without being affected. As a result, the local disappearance of Poly-Si on the surface of the gate electrode 9a in the downstream process can be prevented, and the yield and reliability of the product can be improved.

Further, by setting the temperature of the n ⁺ -type single crystal silicon substrate 31 at the time of processing the gate electrode to 5 ° C., it is possible to prevent the etching residue from reattaching to the processing surface and to make the processing surface smooth, thereby improving the yield. In addition, the reliability of the trench gate type MOSFET can be improved.

The subsequent steps are performed in the same manner as in the first embodiment. That is, as shown in FIG. 22, after forming an interlayer insulating film (for example, silicon oxide film) 43 and a resist pattern patterned by photolithography on the oxide film 40, a trench reaching the n ⁻ type epitaxial layer 32 by etching. 44 is formed. Subsequently, after forming a p ⁺ type contact layer 45 in the p type impurity diffusion layer 33 by ion implantation, the resist pattern is removed. Thereafter, a metal film (for example, aluminum) 46 is deposited on the interlayer insulating film 43 by the LPCVD method, a source electrode and a gate pad of the vertical MOSFET are formed, and Au (gold) is formed on the back surface of the n ⁺ type single crystal silicon substrate 31. ) To form a trench gate type MOSFET having a dummy gate. The presence of this dummy gate has the effect of reducing the ON resistance of the MOSFET.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The method for manufacturing a semiconductor device of the present invention is widely used for manufacturing a semiconductor element having a trench gate type MOSFET.

It is principal part sectional drawing explaining the manufacturing method of the trench gate type MOSFET contained in the semiconductor device which is Embodiment 1 of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; It is principal part sectional drawing which shows the trench gate type MOSFET manufactured by the prior art. It is principal part sectional drawing explaining the manufacturing method of the trench gate type MOSFET which has a dummy gate contained in the semiconductor device which is Embodiment 2 of this invention. FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; It is principal part sectional drawing which shows the trench gate type MOSFET which has a dummy gate manufactured with the prior art.

Explanation of symbols

1 n ⁺ type single crystal silicon substrate (semiconductor substrate)
2 n ⁻ type epitaxial layer 3 oxide film 4 p type impurity diffusion layer 5 n ⁺ type impurity diffusion layer 6 mask material 7 trench 8 gate oxide film 9 Poly-Si film 9a gate electrode 9b gate electrode 10 resist pattern 11 interlayer insulating film 12 Resist pattern 13a, 13b Trench 14 p ⁺ type contact layer 15 Metal film 16 Back electrode 20 Reaction product 31 n ⁺ type single crystal silicon substrate (semiconductor substrate)
32 n ⁻ type epitaxial layer 33 p type impurity diffusion layer 34 n ⁺ type impurity diffusion layer 35 mask material 36 trench 37 oxide film 38 Poly-Si film 39 dummy gate electrode 40 oxide film 41 Poly-Si film 42 gate electrode 43 interlayer insulation Film 44 Trench 45 p ⁺ type contact layer 46 Metal film 47 Back electrode 50 Reaction product

Claims (1)

A method of manufacturing a semiconductor device having a trench gate type MOSFET,
(A) a step of preparing a semiconductor substrate;
(B) forming a vertical groove on the main surface of the semiconductor substrate;
(C) a step of forming an oxide film on the surface of the groove after the step (b);
(D) After the step (c), a step of forming a Poly-Si film as a gate electrode material on the main surface including the inside of the trench;
(E) After the step (d), the Poly-Si film is etched back by dry etching, and a gate electrode of the trench gate type MOSFET is formed in the trench.
(F) forming a source region on the main surface of the semiconductor substrate;
(G) forming a drain electrode on the back surface of the semiconductor substrate;
Including
In the step (e), a gas mainly composed of SF ₆ gas is used as an etching gas, and the temperature of the semiconductor substrate during etching is set to 5 ° C. or higher.

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