CN101286478A - CMOS transistor and manufacturing method therefor - Google Patents
CMOS transistor and manufacturing method therefor Download PDFInfo
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- CN101286478A CN101286478A CNA2007100965118A CN200710096511A CN101286478A CN 101286478 A CN101286478 A CN 101286478A CN A2007100965118 A CNA2007100965118 A CN A2007100965118A CN 200710096511 A CN200710096511 A CN 200710096511A CN 101286478 A CN101286478 A CN 101286478A
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Abstract
The invention relates to a supplementary metal oxide semiconductor transistor which comprises a substrate, a first electric conduction metal oxide semiconductor transistor, a second electric conduction metal oxide semiconductor transistor, a buffer layer, a first stress layer and a second stress layer, wherein, a component isolation structure is arranged in the substrate which is defined to be a first active area and a second active area. The first and the second electric conduction metal oxide semiconductor transistors are respectively configured on the substrate of the first and the second active areas. Moreover, the thickness of the first nitride gap wall of the first electric conduction metal oxide semiconductor transistor is more than that of the second nitride gap wall of the second electric conduction metal oxide semiconductor transistor; the buffer layer is correspondingly configured on the first electric conduction metal oxide semiconductor transistor; the first stress layer is configured on the buffer layer; the second stress layer is correspondingly configured on the second electric conduction metal oxide semiconductor transistor.
Description
Technical field
The present invention relates to a kind of integrated circuit component and forming method thereof, relate in particular to a kind of CMOS transistor and manufacture method thereof.
Background technology
In the evolution of integrated circuit component, can reach the purpose of high speed operation and low power consumption by dwindling size of component.Yet owing to dwindle the restriction that the technology of component size is subjected to factors such as technology bottleneck, cost costliness at present, other are different from the technology of dwindling element so need development, to improve the drive current of element.
Therefore, industry proposes a kind of mode of utilizing strain (strain) control, increases the method for element efficiency, to overcome the limit of element downsizing.Above-mentioned method is, forms stressor layers on transistor unit, so that the channel region of this element produces the spacing that strain changes silicon (Si) lattice, increasing the mobility (mobility) in electronics or hole, and then improves the drive current of element.And (selective strain scheme SSS) can improve the drive current of P transistor npn npn and N transistor npn npn simultaneously to use so-called selectivity strain gauge technique.The selectivity strain gauge technique just is meant, on the N transistor npn npn, form and can be used as contact hole etching stop layer (contact etching stop layer, CESL) the stretch silicon nitride layer of (tensile) of a floor height improves the mobility of electronics so that its channel region produces elongation strain; And on the P transistor npn npn, form the silicon nitride layer of one deck high compression (compression) can be used as CESL, so that its channel region produces compression strain and improves the mobility in hole.
For integrated circuit component, its electrical performance is the important key that is related to element quality quality.Though, use the selective stress technology can improve the drive current of P type and N transistor npn npn at present, along with the continuous development of technology, only be rely on improve element integrated level or selective stress technology and can't can provide fully element required electrically.So how can further improve element electrically is one of positive target of making great efforts of present industry.
In addition, exposure is also arranged on some United States Patent (USP)s, for example US2006/0099763, US 7,002,209 and US 2005/0266639 about the above-mentioned correlation technique of mentioning.Above document is all the reference of this case.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method of CMOS transistor is being provided, can solve known only is to rely on to improve element integrated level or selective stress technology and can't provide element required electrical problem fully, and can come further significantly to improve the usefulness of element with easy technology.
Another object of the present invention provides a kind of CMOS transistor, and the known high integration element of efficiency ratio of element or the usefulness of application choice stress technique element are more significantly improved.
The present invention proposes a kind of manufacture method of CMOS transistor.The method is to form component isolation structure in substrate, to define first active area and second active area in substrate.Then, in the substrate of first active area, form the first conductivity type metal oxide semiconductor transistor, and in the substrate of second active area, form the second conductivity type metal oxide semiconductor transistor simultaneously.Wherein, the first conductivity type metal oxide semiconductor transistor comprises and is formed at suprabasil first grid structure, is formed at first doped region in the first grid structure substrate on two sides, and first nitride spacer that is formed at first grid structure side wall and cover part first doped region.The second conductivity type metal oxide semiconductor transistor comprises and is formed at suprabasil second grid structure, is formed at second doped region in the second grid structure substrate on two sides, and second nitride spacer that is formed at second grid structure side wall and cover part second doped region.Then, form one deck resilient coating in compliance ground, substrate top, to cover whole substrate.Subsequently, on resilient coating, form first stressor layers and dielectric layer in regular turn.Then, remove the dielectric layer, first stressor layers, resilient coating of second active area and to small part second silicon nitride gap wall.Afterwards, form second stressor layers in compliance ground, substrate top, to cover whole substrate.Then, remove second stressor layers of first active area.
According to the manufacture method of the described CMOS transistor of embodiments of the invention, the above-mentioned dielectric layer that removes second active area, first stressor layers, resilient coating and to the method for small part second nitride spacer for example be to carry out an etch process.Above-mentioned etch process for example is to utilize the original position mode to carry out.
According to the manufacture method of the described CMOS transistor of embodiments of the invention, the method for above-mentioned second stressor layers that removes first active area for example is to carry out an etch process.
Manufacture method according to the described CMOS transistor of embodiments of the invention, the first above-mentioned conductivity type metal oxide semiconductor transistor is the P-type mos transistor, the second conductivity type metal oxide semiconductor transistor is a N type metal oxide semiconductor transistor, then first stressor layers is a compressive stress layers, and second stressor layers is a tension stress layer.
According to the manufacture method of the described CMOS transistor of embodiments of the invention, the material of first, second above-mentioned nitride spacer for example is a silicon nitride.
According to the manufacture method of the described CMOS transistor of embodiments of the invention, material above-mentioned first, this second stressor layers for example is silicon nitride or silica.
According to the manufacture method of the described CMOS transistor of embodiments of the invention, formation method above-mentioned first, this second stressor layers for example is a chemical vapour deposition technique.
Manufacture method according to the described CMOS transistor of embodiments of the invention, on be set forth in before resilient coating forms, can be further between the first grid structure of the first conductivity type metal oxide semiconductor transistor and first nitride spacer, form first lining, and in formation second lining between the second grid structure of the second conductivity type metal oxide semiconductor transistor and second nitride spacer.The material of first, second above-mentioned lining for example is a silica.
Manufacture method according to the described CMOS transistor of embodiments of the invention, on be set forth in before resilient coating forms, also be included in and form one first metal silicide layer on the first grid body structure surface of the first conductivity type metal oxide semiconductor transistor and first doped region, and on the second grid body structure surface of the second conductivity type metal oxide semiconductor transistor and second doped region formation one second metal silicide layer.
The present invention proposes a kind of CMOS transistor in addition, and it comprises substrate, the first conductivity type metal oxide semiconductor transistor, the second conductivity type metal oxide semiconductor transistor, resilient coating, first stressor layers and second stressor layers.In substrate, have component isolation structure, substrate is defined first active area and second active area.The first conductivity type metal oxide semiconductor transistor is disposed in the substrate of first active area.The first conductivity type metal oxide semiconductor transistor comprises and is disposed at suprabasil first grid structure, is disposed at first doped region in the first grid structure substrate on two sides, and first nitride spacer that is disposed at first grid structure side wall and cover part first doped region.The second conductivity type metal oxide semiconductor transistor is disposed in the substrate of second active area.The second conductivity type metal oxide semiconductor transistor comprises and is disposed at suprabasil second grid structure, is disposed at second doped region in the second grid structure substrate on two sides, and second nitride spacer that is disposed at second grid structure side wall and cover part second doped region.Wherein, the thickness of first nitride spacer is greater than the thickness of second nitride spacer.In addition, be disposed to the resilient coating compliance on the first conductivity type metal oxide semiconductor transistor.First stressor layers is disposed on the resilient coating.Be disposed on the second conductivity type metal oxide semiconductor transistor to the second stressor layers compliance.
According to the described CMOS transistor of embodiments of the invention, the first above-mentioned conductivity type metal oxide semiconductor transistor is the P-type mos transistor, the second conductivity type metal oxide semiconductor transistor is a N type metal oxide semiconductor transistor, then first stressor layers is a compressive stress layers, and second stressor layers is a tension stress layer.
According to the described CMOS transistor of embodiments of the invention, the material of first, second above-mentioned nitride spacer for example is a silicon nitride.
According to the described CMOS transistor of embodiments of the invention, the material of first, second above-mentioned stressor layers for example is silicon nitride or silica.
According to the described CMOS transistor of embodiments of the invention, also comprise first lining and second lining.Wherein, first stress liner configuration is on the first grid structure side wall and first doped region of the first conductivity type metal oxide semiconductor transistor.Second stress liner configuration is on the second grid structure side wall and second doped region of the second conductivity type metal oxide semiconductor transistor.
According to the described CMOS transistor of embodiments of the invention, the material of first, second above-mentioned lining for example is a silica.
According to the described CMOS transistor of embodiments of the invention, also comprise first metal silicide layer and second metal silicide layer.Wherein, first metal silicide layer is disposed on the first grid body structure surface and first doped region of the first conductivity type metal oxide semiconductor transistor.Second metal silicide layer is disposed on the second grid body structure surface and second doped region of the second conductivity type metal oxide semiconductor transistor.
During the compressive stress layers of the present invention above removing N type metal oxide semiconductor transistor, can remove the nitride spacer of at least a portion in the lump, to reduce the thickness of nitride spacer.And this reduces the mode of the thickness of the transistorized nitride spacer of N type metal oxide semiconductor, can produce bigger stress in the transistorized raceway groove of N type metal oxide semiconductor, to improve its drive current gain (I
OnGain).Because the present invention has used so-called selectivity strain gauge technique, and (selective strainscheme is SSS) to improve P type and the transistorized usefulness of N type metal oxide semiconductor simultaneously.Therefore, add and utilize the thickness that reduces the transistorized nitride spacer of N type metal oxide semiconductor, can further significantly promote the usefulness of integral member to improve the mode of the transistorized drive current gain of N type metal oxide semiconductor.And, by the time of control etch process, can control the thickness of the transistorized nitride spacer of N type metal oxide semiconductor accurately, so can adjust required element efficiency according to the difference of technology.On the other hand, the method that removes the nitride spacer of at least a portion can for example be to utilize in-situ etch technology, so can keep the simplification of technology, and can save the technology cost.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 to Fig. 7 is the flow process generalized section according to the manufacture method of the CMOS transistor that one embodiment of the invention illustrated;
Fig. 8 is the generalized section according to the CMOS transistor that another embodiment of the present invention illustrated;
Fig. 9 is the graph of a relation of the thickness of P type and the transistorized nitride spacer of N type metal oxide semiconductor to the drive current gain percentage of element.
The main element symbol description
100: substrate
102: the first active areas
104: the second active areas
106: component isolation structure
108,110: grid structure
108a, 110a: gate dielectric
108b, 110b: grid conducting layer
112,114: the source/drain extension area
116,118: clearance wall
116a, 118a: liner oxide
116b, 118b: nitride spacer
120,122: source/drain
124,126: metal silicide layer
128: resilient coating
130: compressive stress layers
132: dielectric layer
134: the photoresist layer
136: tension stress layer
140:P type metal oxide semiconductor transistor
142:P type doped region
150:N type metal oxide semiconductor transistor
152:N type doped region
Embodiment
Fig. 1 to Fig. 7 is the flow process generalized section according to the manufacture method of the CMOS transistor that the embodiment of the invention illustrated.
At first, please refer to Fig. 1, in substrate 100, form an element isolation structure 106, to define first active area 102 and second active area 104.Component isolation structure 106 for example is a shallow slot isolation structure, and its formation method for example is prior to etching irrigation canals and ditches in the substrate 100, fills up these irrigation canals and ditches with dielectric material again and forms.
In the present embodiment, be to be example at first active area, 102 formation P-type mos transistors and at second active area, 104 formation N type metal oxide semiconductor transistors, be described in detail.
Then, please continue, in the substrate 100 of first active area 102, form grid structure 108, and in the substrate 100 of second active area 104, form grid structure 110 with reference to Fig. 1.Above-mentioned, grid structure 108 is made of gate dielectric 108a and grid conducting layer 108b, and grid structure 110 is made of gate dielectric 110a and grid conducting layer 110b.The formation method of grid structure 108,110 for example is to form one dielectric layer (not illustrating) in substrate 100.This dielectric layer comes at the bottom of the oxidation base 100 and form with high temperature usually.Afterwards, form a conductive layer (not illustrating) on dielectric layer, its material for example is a polysilicon, and its formation method for example is a chemical vapour deposition technique.Then, definition conductive layer and dielectric layer are to form grid structure 108,110.
Then, carry out an ion implantation technology, in grid structure 108,110 substrate on two sides 100, to form source/drain extension area (source/drain extension, SDE) 112,114.
Subsequently, please refer to Fig. 2, form clearance wall 116,118 at grid structure 108,110 sidewalls respectively.Above-mentioned, clearance wall 116 is made of liner oxide 116a and nitride spacer 116b, and clearance wall 118 is made of liner oxide 118a and nitride spacer 118b.The formation method of clearance wall 116,118 for example is to form one deck silicon oxide layer (not illustrating) and one deck silicon nitride layer (not illustrating) in regular turn in substrate 100 tops, compliance ground overlies gate structure 108,110 and source/drain extension area 112,114.Afterwards, utilize etching technique, etches both silicon nitride layer and silicon oxide layer, and form liner oxide 116a and nitride spacer 116b at grid structure 108 sidewalls, and form liner oxide 118a and nitride spacer 118b at grid structure 110 sidewalls.
In addition, in other embodiments, between grid structure 108 and clearance wall 116, and between grid structure 110 and clearance wall 118, also can respectively comprise a skew clearance wall (offset spacer) (not illustrating).This skew clearance wall can for example be oxide layer or nitration case.
In Fig. 2, nitride spacer 116b, 118b are depicted as one deck L shaped (L-shape), but it also can be arc (arc-shape), the present invention does not do special qualification to the shape and the number of plies of clearance wall.
Then, please refer to Fig. 3, carry out an ion implantation technology, in grid structure 108,110 substrate on two sides 100, to form source/drain 120,122.
Then, on grid structure 108 surface and exposed source/drain 120, form metal silicide layer 124, and on grid structure 110 surfaces and exposed source/drain 122, form metal silicide layer 126.Above-mentioned, the formation method of metal silicide layer 124,126 for example is, forms layer of metal layer (not illustrating) earlier, conformably covers whole substrate 100, and wherein the material of metal level for example is titanium (Ti), cobalt (Co), nickel (Ni) or other suitable materials.Then, metal level is carried out a heat treatment, so that metal level produces reaction with the rete that is contacted, and this heat treatment for example is rapid thermal anneal process.Afterwards, utilize an isotropic etching method, remove the unreacted metal layer, and stay metal silicide layer 124,126.
Hold above-mentionedly, after metal silicide layer 124 forms, can form P-type mos transistors 140 at first active area 102, and form N type metal oxide semiconductor transistors 150 at second active area 104.Wherein, source/drain extension area 112 and the doped region 142 of source/drain regions 120 as P-type mos transistor 140; Source/drain extension area 114 and the doped region 152 of source/drain regions 122 as N type metal oxide semiconductor transistor 150.
Then, please refer to Fig. 4, form one deck resilient coating 128, cover to compliance whole substrate 100.Resilient coating 128 for example is an oxide layer, and its material for example is silica or other suitable materials.The formation method of resilient coating 128 for example is chemical vapour deposition technique or other suitable methods.
Then, on resilient coating 128, form one deck compressive stress layers 130.The material of compressive stress layers 130 for example is a silicon nitride, and its formation method for example is a Low Pressure Chemical Vapor Deposition.Certainly, the material of compressive stress layers 130 can for example be a silica also.In addition, can be by compressive stress layers 130 be carried out a doping step or an annealing steps, to adjust its stress value.Subsequently, after compressive stress layers 130 forms, then on compressive stress layers 130, form one dielectric layer 132.The material of dielectric layer 132 for example is silica or silicon nitride, and its formation method for example is a chemical vapour deposition technique.
Then, please refer to Fig. 5, form one deck photoresist layer 134, cover the dielectric layer 132 of first active area 102.Then, be mask with photoresist layer 134, carry out an etch process, with the dielectric layer 132 that removes second active area 104, compressive stress layers 130, resilient coating 128 and to the silicon nitride gap wall 118b of small part.Above-mentioned etch process for example is to carry out in original position (in-situ) mode.In detail, the above-mentioned dielectric layer 132 that removes second active area 104, compressive stress layers 130, resilient coating 128 and to each etching step of the silicon nitride gap wall 118b of small part can for example be, in same reative cell (reaction chamber) or on same board, carry out, so can keep the simplification of technology, and can save the technology cost.
Be noted that especially above-mentioned removing to the step of the silicon nitride gap wall 118b of small part is meant, can partly remove silicon nitride gap wall 118b, or remove silicon nitride gap wall 118b fully, to reduce the thickness of nitride spacer 118b.In Fig. 5, show the diagram that is removed of silicon nitride gap wall 118b of a part, and being illustrated as the technical staff who knows field of the present invention and can understanding of fully silicon nitride gap wall 118b being removed do not illustrate out in this.
Subsequently, please refer to Fig. 6, form a tension stress layer 136 in compliance ground, substrate 100 top, to cover whole substrate 100.The material of tension stress layer 136 for example is a silicon nitride, and its formation method for example is a Low Pressure Chemical Vapor Deposition.Certainly, the material of tension stress layer 136 can for example be a silica also.In addition, can be by tension stress layer 136 be carried out a doping step or an annealing steps, to adjust its stress value.
Then, please refer to Fig. 7, remove the tension stress layer 136 of first active area 102, and stay the tension stress layer 136 of second active area 104.The method that removes the tension stress layer 136 of first active area 102 for example is, forming one deck photoresist layer (not illustrating), cover the tension stress layer 136 of second active area 104, is mask with the photoresist layer then, carry out an etch process, to form it.
It should be noted that in the above-described embodiments, when removing the compressive stress layers of N type metal oxide semiconductor transistor top, can remove the nitride spacer of at least a portion in the lump, to reduce the thickness of nitride spacer.And the method for the thickness of the transistorized nitride spacer of reduction N type metal oxide semiconductor of present embodiment can produce bigger stress in the transistorized raceway groove of N type metal oxide semiconductor, to improve its drive current gain (I
OnGain).
Particularly, the present invention is at so-called selectivity strain gauge technique (the selective strainscheme of utilization, SSS) with under the situation of improving P type and the transistorized usefulness of N type metal oxide semiconductor simultaneously, utilize the thickness that reduces the transistorized nitride spacer of N type metal oxide semiconductor and in raceway groove, produce bigger stress, improve the transistorized drive current gain of N type metal oxide semiconductor more.Thus, method of the present invention can further significantly promote the usefulness of integral member.And, by the time of control etch process, can control the thickness of the transistorized nitride spacer of N type metal oxide semiconductor accurately, so can adjust required element efficiency according to the difference of technology.
Then, describe the structure of the CMOS transistor that utilizes method manufacturing of the present invention in detail with Fig. 7.Omit in the following description about the material of each member and the repeat specification of shape.
Please referring again to Fig. 7, CMOS transistor comprises substrate 100, P-type mos transistor 140, N type metal oxide semiconductor transistor 150, resilient coating 128, compressive stress layers 130 and tension stress layer 136.Wherein, in substrate 100, dispose component isolation structure 106, substrate 100 is defined first active area 102 and second active area 104.Be disposed on the P-type mos transistor 140 to resilient coating 128 compliances.Compressive stress layers 130 is disposed on the resilient coating 128, and tension stress layer 136 compliances be disposed on the N type metal oxide semiconductor transistor 150.
The P-type mos transistor 140 of CMOS transistor is disposed in first active area 102.P-type mos transistor 140 mainly comprises grid structure 108, nitride spacer 116b and P type doped region 142.Wherein, grid structure 108 is made of gate dielectric 108a and grid conducting layer 108b.P type doped region 142 is made of source/drain extension area 112 and source/drain 120.In addition, also configurable on grid structure 108 sidewalls and P type doped region 142 have a liner oxide 116a.On grid structure 108 surface and exposed source/drain 120, can further dispose metal silicide layer 124.
The N type metal oxide semiconductor transistor 150 of CMOS transistor is disposed in second active area 104.N type metal oxide semiconductor transistor 150 mainly comprises grid structure 110, nitride spacer 118b and N type doped region 152.Wherein, grid structure 110 is made of gate dielectric 110a and grid conducting layer 110b.N type doped region 152 is made of source/drain extension area 114 and source/drain 122.In addition, also configurable on grid structure 110 sidewalls and N type doped region 152 have a liner oxide 118a.On grid structure 110 surface and exposed source/drain 122, can further dispose metal silicide layer 126.
In addition, in other embodiments, between grid structure 108 and clearance wall 116, and between grid structure 110 and clearance wall 118, also can dispose a skew clearance wall (not illustrating) respectively.
The thickness of nitride spacer 116b of P-type mos transistor 140 that is noted that present embodiment is greater than the thickness of the nitride spacer 118b of N type metal oxide semiconductor transistor 150.More specifically, as shown in Figure 7, the thickness of the nitride spacer 116b of P-type mos transistor 140 is the thickness of keeping the technological design criterion, and the thickness of the nitride spacer 118b of N type metal oxide semiconductor transistor 150 is then less than the thickness of technological design criterion.Or the thickness of the nitride spacer 116b of P-type mos transistor 140 is the thickness of keeping the technological design criterion, and does not dispose nitride spacer (as shown in Figure 8) on N type metal oxide semiconductor transistor 150.
Because, the thickness of the transistorized nitride spacer of P-type mos of present embodiment is kept the thickness of technological design criterion, and the thickness of the transistorized nitride spacer of N type metal oxide semiconductor is less than the thickness of the transistorized nitride spacer of P-type mos, therefore can in the transistorized raceway groove of N type metal oxide semiconductor, produce bigger stress, to improve the transistorized drive current gain of N type metal oxide semiconductor.
In addition, used so-called selectivity strain gauge technique in the present embodiment, to improve P type and the transistorized usefulness of N type metal oxide semiconductor simultaneously.Add, make the thickness of the thickness of the transistorized nitride spacer of N type metal oxide semiconductor less than the transistorized nitride spacer of P-type mos, the transistorized usefulness of N type metal oxide semiconductor can be improved, the usefulness of integral member can be further promoted thus.And, by the thickness of the transistorized nitride spacer of control N type metal oxide semiconductor, can adjust required element efficiency according to the difference of technology.
Next, illustrate that with Fig. 9 the present invention can reach the purpose of lift elements usefulness really.
Please refer to Fig. 9, its be P type and the transistorized clearance wall of N type metal oxide semiconductor thickness (
) to the graph of a relation of the drive current of element gain percentage (%).Wherein, ▲ expression P-type mos transistor when being coated with compressive stress layers, the drive current gain percentage of measured element under the condition of the thickness of different gap wall.△ represents N type metal oxide semiconductor transistor when being coated with tension stress layer, the drive current of measured element gain percentage under the condition of the thickness of different gap wall.In Fig. 9, be that the technological design criterion thickness of the clearance wall (comprising liner oxide and nitride spacer) with metal oxide semiconductor transistor is
And the thickness of clearance wall is reduced to
With
Condition, carry out testing electrical property.
By among Fig. 9 as can be known, reduce the thickness of the transistorized clearance wall of P-type mos, its drive current gain is descended.Yet the thickness of the transistorized clearance wall of reduction N type metal oxide semiconductor can make to promote its drive current gain.Therefore, can use so-called selectivity strain gauge technique to improve P type and the transistorized usefulness of N type metal oxide semiconductor simultaneously in the present invention, and utilize the thickness that reduces the transistorized nitride spacer of N type metal oxide semiconductor, come more further to promote the usefulness of integral member.And, by the thickness of the transistorized nitride spacer of control N type metal oxide semiconductor, can adjust required element efficiency according to the difference of technology.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (18)
1. the manufacture method of a CMOS transistor comprises:
In substrate, form component isolation structure, in this substrate, to define first active area and second active area;
In this substrate of this first active area, form the first conductivity type metal oxide semiconductor transistor, and in this substrate of this second active area, form the second conductivity type metal oxide semiconductor transistor simultaneously,
Wherein, this first conductivity type metal oxide semiconductor transistor comprises and is formed at this suprabasil first grid structure, is formed at first doped region in this substrates of this first grid structure both sides, and first nitride spacer that is formed at this first grid structure side wall and this first doped region of cover part
This second conductivity type metal oxide semiconductor transistor comprises and is formed at this suprabasil second grid structure, is formed at second doped region in this substrates of this second grid structure both sides, and second nitride spacer that is formed at this second grid structure side wall and this second doped region of cover part;
Form resilient coating in this compliance ground, substrate top, to cover whole this substrate;
On this resilient coating, form first stressor layers and dielectric layer in regular turn;
Remove this dielectric layer, this first stressor layers, this resilient coating of this second active area and to this second silicon nitride gap wall of small part;
Form second stressor layers in this compliance ground, substrate top, to cover whole this substrate; And
Remove this second stressor layers of this first active area.
2. the manufacture method of CMOS transistor as claimed in claim 1, wherein remove this dielectric layer, this first stressor layers, this resilient coating of this second active area and, comprise and carry out etch process to the method for this second nitride spacer of small part.
3. the manufacture method of CMOS transistor as claimed in claim 2, wherein this etch process comprises and utilizes the original position mode to carry out.
4. the manufacture method of CMOS transistor as claimed in claim 1, the method that wherein removes this second stressor layers of this first active area comprises carries out etch process.
5. the manufacture method of CMOS transistor as claimed in claim 1, wherein this first conductivity type metal oxide semiconductor transistor is the P-type mos transistor, this second conductivity type metal oxide semiconductor transistor is a N type metal oxide semiconductor transistor, then this first stressor layers is a compressive stress layers, and this second stressor layers is a tension stress layer.
6. the manufacture method of CMOS transistor as claimed in claim 1, wherein this first, the material of this second nitride spacer comprises silicon nitride.
7. the manufacture method of CMOS transistor as claimed in claim 1, wherein this first, the material of this second stressor layers comprises silicon nitride or silica.
8. the manufacture method of CMOS transistor as claimed in claim 1, wherein this first, the formation method of this second stressor layers comprises chemical vapour deposition technique.
9. the manufacture method of CMOS transistor as claimed in claim 1, wherein before this resilient coating forms, also be included in and form first lining between this first grid structure of this first conductivity type metal oxide semiconductor transistor and this first nitride spacer, and in formation second lining between this second grid structure of this second conductivity type metal oxide semiconductor transistor and this second nitride spacer.
10. the manufacture method of CMOS transistor as claimed in claim 9, wherein this first, the material of this second lining comprises silica.
11. the manufacture method of CMOS transistor as claimed in claim 1, wherein before this resilient coating forms, also be included in and form first metal silicide layer on this first grid body structure surface of this first conductivity type metal oxide semiconductor transistor and this first doped region, and on this second grid body structure surface of this second conductivity type metal oxide semiconductor transistor and this second doped region formation second metal silicide layer.
12. a CMOS transistor comprises:
Substrate has component isolation structure in this substrate, and this substrate is defined first active area and second active area;
The first conductivity type metal oxide semiconductor transistor, be disposed in this substrate of this first active area, this first conductivity type metal oxide semiconductor transistor comprises and is disposed at this suprabasil first grid structure, is disposed at first doped region in this substrates of this first grid structure both sides, and first nitride spacer that is disposed at this first grid structure side wall and this first doped region of cover part;
The second conductivity type metal oxide semiconductor transistor, be disposed in this substrate of this second active area, this second conductivity type metal oxide semiconductor transistor comprises and is disposed at this suprabasil second grid structure, is disposed at second doped region in this substrates of this second grid structure both sides, and second nitride spacer that is disposed at this second grid structure side wall and this second doped region of cover part
Wherein the thickness of this first nitride spacer is greater than the thickness of this second nitride spacer;
Resilient coating is disposed to compliance on this first conductivity type metal oxide semiconductor transistor;
First stressor layers is disposed on this resilient coating; And
Second stressor layers is disposed to compliance on this second conductivity type metal oxide semiconductor transistor.
13. CMOS transistor as claimed in claim 12, wherein this first conductivity type metal oxide semiconductor transistor is the P-type mos transistor, this second conductivity type metal oxide semiconductor transistor is a N type metal oxide semiconductor transistor, then this first stressor layers is a compressive stress layers, and this second stressor layers is a tension stress layer.
14. CMOS transistor as claimed in claim 12, wherein this first, the material of this second nitride spacer comprises silicon nitride.
15. CMOS transistor as claimed in claim 12, wherein this first, the material of this second stressor layers comprises silicon nitride or silica.
16. CMOS transistor as claimed in claim 12, also comprise: configuration first lining on this first grid structure side wall of this first conductivity type metal oxide semiconductor transistor and this first doped region, and on this second grid structure side wall of this second conductivity type metal oxide semiconductor transistor and this second doped region, dispose second lining.
17. CMOS transistor as claimed in claim 16, wherein this first, the material of this second lining comprises silica.
18. CMOS transistor as claimed in claim 12, also comprise: configuration first metal silicide layer on this first grid body structure surface of this first conductivity type metal oxide semiconductor transistor and this first doped region, and on this second grid body structure surface of this second conductivity type metal oxide semiconductor transistor and this second doped region, dispose second metal silicide layer.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376578A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for implementing dual stress strain technology |
| CN102468236A (en) * | 2010-10-29 | 2012-05-23 | 中芯国际集成电路制造(北京)有限公司 | Formation method of metal-oxide semiconductor device |
| CN102610513A (en) * | 2012-03-31 | 2012-07-25 | 上海华力微电子有限公司 | Method for forming silicon nitride film on dual-stress layer |
| CN102768993A (en) * | 2011-05-03 | 2012-11-07 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of NMOS (N-channel metal oxide semiconductor) device by stress memorization technique |
| CN101630660B (en) * | 2009-07-07 | 2013-01-23 | 北京大学 | Method for improving irradiation resistance of CMOS transistor, SMOS transistor and integrated circuit |
| CN102969231A (en) * | 2011-09-01 | 2013-03-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal gate |
| CN103794561A (en) * | 2012-11-02 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN107968035A (en) * | 2016-10-19 | 2018-04-27 | 株式会社村田制作所 | Semiconductor device and its manufacture method |
| CN108461448A (en) * | 2017-02-17 | 2018-08-28 | 力晶科技股份有限公司 | Method for manufacturing semiconductor element |
| CN112103190A (en) * | 2020-11-03 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Structure of semiconductor device and preparation method thereof |
| CN114207703A (en) * | 2020-05-09 | 2022-03-18 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN116759462A (en) * | 2023-08-22 | 2023-09-15 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101630660B (en) * | 2009-07-07 | 2013-01-23 | 北京大学 | Method for improving irradiation resistance of CMOS transistor, SMOS transistor and integrated circuit |
| CN102376578A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for implementing dual stress strain technology |
| CN102468236A (en) * | 2010-10-29 | 2012-05-23 | 中芯国际集成电路制造(北京)有限公司 | Formation method of metal-oxide semiconductor device |
| CN102768993B (en) * | 2011-05-03 | 2014-12-10 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of NMOS (N-channel metal oxide semiconductor) device by stress memorization technique |
| CN102768993A (en) * | 2011-05-03 | 2012-11-07 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of NMOS (N-channel metal oxide semiconductor) device by stress memorization technique |
| CN102969231B (en) * | 2011-09-01 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of metal gate |
| CN102969231A (en) * | 2011-09-01 | 2013-03-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal gate |
| CN102610513A (en) * | 2012-03-31 | 2012-07-25 | 上海华力微电子有限公司 | Method for forming silicon nitride film on dual-stress layer |
| CN103794561A (en) * | 2012-11-02 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN107968035A (en) * | 2016-10-19 | 2018-04-27 | 株式会社村田制作所 | Semiconductor device and its manufacture method |
| CN107968035B (en) * | 2016-10-19 | 2022-02-25 | 株式会社村田制作所 | Semiconductor device and method for manufacturing the same |
| CN108461448A (en) * | 2017-02-17 | 2018-08-28 | 力晶科技股份有限公司 | Method for manufacturing semiconductor element |
| CN114207703A (en) * | 2020-05-09 | 2022-03-18 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN114207703B (en) * | 2020-05-09 | 2022-08-12 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN112103190A (en) * | 2020-11-03 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Structure of semiconductor device and preparation method thereof |
| CN112103190B (en) * | 2020-11-03 | 2021-02-19 | 晶芯成(北京)科技有限公司 | Structure of semiconductor device and preparation method thereof |
| CN116759462A (en) * | 2023-08-22 | 2023-09-15 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN116759462B (en) * | 2023-08-22 | 2023-11-28 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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