CN102969231A - Manufacturing method of metal gate - Google Patents
Manufacturing method of metal gate Download PDFInfo
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- CN102969231A CN102969231A CN2011102561647A CN201110256164A CN102969231A CN 102969231 A CN102969231 A CN 102969231A CN 2011102561647 A CN2011102561647 A CN 2011102561647A CN 201110256164 A CN201110256164 A CN 201110256164A CN 102969231 A CN102969231 A CN 102969231A
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Abstract
The invention provides a manufacturing method of a metal gate. An oxidation layer on the metal gate is removed through an argon sputtering process simultaneously, and nickel-silicon metal at an active area is protected effectively. Firstly, a semiconductor base is provided, and a source electrode, a drain electrode, a metal grid electrode and a self-aligned silicide layer are formed on the semiconductor base. The following steps are performed: depositing an aluminum oxide film, forming a contact hole etching stop layer; forming an inter-layer dielectric layer; forming a light resistance layer; performing graph definition on a contact hole; removing the light resistance layer and a part of the contact hole etching stop layer; and performing the argon sputtering process, and opening an aluminum oxide layer formed through auto-oxidation of the metal grid electrode. Finally, the steps of contact hole metal deposition and chemical mechanical grinding are performed.
Description
Technical field
The present invention relates to the manufacture method of a kind of manufacture method of semiconductor device, particularly a kind of metal gate.
Background technology
In the development of integrated circuit, make gate electrode with metal, can fundamentally eliminate the boron penetration effects of polysilicon gate depletion layer effect and p type field effect transistor, obtain low-down grid sheet resistance, and metal gate is can be well compatible with high-dielectric-coefficient grid medium, effectively overcomes Fermi's pinning effect.Therefore the preparation method of metal gate becomes very important technological means.Because metal gate is easy to oxidation in air, formed oxide layer can cause contact hole to disconnect, and therefore must remove this oxide layer before deposition contact hole adhesive layer.In the prior art, usually adopt the argon sputtering method to remove the alumina layer that the metal gate top forms owing to autoxidation, but this can cause the nickel of active area-silicon loss, and the exterior contour of destruction contact hole, shown in Figure 1A-1B.
Touch pitting stop-layer at quarter (Contact Etch Stop Layer, CESL) and be generally silicon nitride (SiN) material.Prior art provides a kind of method, keeps the silicon nitride material on a part of nickel-silicon metal level in etching process.In argon sputtering technology process, when opening alumina layer on the metal gate by physics exposure, the silicon nitride layer that is retained also is consumed in the physics exposure process fully.In the metal gate process processing procedure, rear grid technique can be controlled the work function of grid material well, and the favourable silicon adaptability to changes that improves the channel carrier flowability can also be provided for the raceway groove of PMOS pipe, therefore help the performance of improving product and the stand-by power consumption of reduction product.Yet, for rear grid technique processing procedure, in etching and chemico-mechanical polishing (CMP) operation, can run into some difficult problems.Because in the etching process of this method, selectivity between metallic aluminium and the silicon nitride is very large, causes process window very little, can not control well the reservation of silicon nitride: when the retained nitrogen SiClx is too much, because the argon sputter procedure can be removed whole silicon nitrides, thereby can cause contact hole to be opened; When the retained nitrogen SiClx is very few, can cause the punch through of nickel-silicon.
In sum, in the rear grid technique manufacturing process of metal gate, how effectively removing the oxide layer on the metal gate in protection nickel-silicon metal level, is the important step in the metal gate manufacture craft.
Summary of the invention
The present invention relates to the manufacture method of a kind of manufacture method of semiconductor device, particularly a kind of metal gate.In existing metal gate process processing procedure, because argon sputtering technology process causes nickel-silicon loss.The present invention proposes a kind of manufacture method of metal gate, and the nickel of active area-silicon metal is protected.
The invention provides a kind of manufacture method of metal gate, comprising:
Semiconductor base is provided; The self-alignment silicide layer that forms source electrode, drain electrode, metal gates and be formed at source electrode, drain electrode, metal gates surface at described semiconductor base; Deposition of aluminium oxide film on described semiconductor base; Form and touch pitting stop-layer at quarter; Form interlayer dielectric layer; Form photoresist layer; Carry out the graphical definition of contact hole; Remove described photoresist layer and a part and touch pitting stop-layer at quarter; Carry out the argon sputtering technology, remove the aluminum oxide film at described metal gates top and the oxide layer that autoxidation forms.
Preferably, described self-alignment silicide layer is nickel-silicon metal material.
Preferably, described aluminum oxide film film thickness is 10 ~ 40.
Preferably, described tactile pitting stop-layer at quarter is silicon nitride material.
Preferably, described metal gates is metallic aluminium or aluminum titanium alloy material.
Preferably, insert a silicon nitride layer in described interlayer dielectric layer, this silicon nitride layer is hard mask layer and the exhaustion layer in the argon sputtering technology.
Preferably, described silicon nitride layer is 30 ~ 100 to the distance on described interlayer dielectric layer surface.
Preferably, described silicon nitride layer is used as reducing the critical size of described contact hole.
Preferably, before forming photoresist layer, also comprise the formation bottom anti-reflection layer.
Preferably, after removing described photoresist layer, also comprise the described bottom anti-reflection layer of removal.
Preferably, the step that after carrying out the argon sputtering technology, also comprises contact metal deposition and cmp.
The present invention removes the autoxidizable oxide layer of metal gate top layer by physical method.Method provided by the invention has the following advantages: can protect well the nickel of active area-silicon metal and obtain the process window of device; The exterior contour of contact hole is also protected, thereby the deposition of adhesive layer is subsequently carried out easily; Need not additional special cmp or wet clean process.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of one embodiment of the present of invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1B is the technological process sectional view that available technology adopting argon sputtering method is removed the alumina layer that is positioned at the formation of metal gate top layer autoxidation;
Fig. 2 A-2F is the sectional view according to each step in the method flow of one embodiment of the invention making metal gate;
Fig. 3 is the process chart of making metal gate according to one embodiment of the invention.
Symbol description:
Fig. 1
100: semiconductor base, 101: metal gates, 102: self-alignment silicide layer, 103: shallow channel isolation area, 110: touch pitting and carve stop-layer, 120: the oxide layer that the metal gates autoxidation forms, 121: the first interlayer dielectric layers, 122: the second interlayer dielectric layers, 123: contact hole
Fig. 2
200: semiconductor base, 201: metal gates, 202: self-alignment silicide layer, 211: aluminum oxide film, 212: touch pitting and carve stop-layer, 220: the oxide layer that the metal gates autoxidation forms, 221: the first interlayer dielectric layers, 222: the second interlayer dielectric layers, 223: hard mask layer and exhaustion layer, 224: bottom anti-reflection layer, 225: photoresist layer, 230: contact metal
Embodiment.
Next, more intactly describe the present invention in connection with accompanying drawing, the cross-sectional view as the schematic diagram of desirable embodiment of the present invention (and intermediate structure) shown in the accompanying drawing is described inventive embodiment.In the accompanying drawings, for clear, size and the relative size in floor and district may be exaggerated.And, owing to for example manufacturing technology and/or tolerance, change of shape shown in causing.Therefore, embodiments of the invention should not be confined to the specific size shape in district shown here, but comprise owing to for example make the form variations that causes.The district that shows among the figure is in fact schematically, their shape be not intended display device the district actual size and shape and be not intended to limit scope of the present invention.The present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, it is thorough and complete to provide these embodiment to expose, and scope of the present invention is fully passed to those skilled in the art.
The purpose of term only is to describe specific embodiment and not as restriction of the present invention as used herein.Should be noted that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, perhaps can have between two parties element or layer.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, then do not have between two parties element or layer." one ", " one " and " described/as to be somebody's turn to do " that should be noted that singulative also are intended to comprise plural form, unless the other mode of pointing out known in context.Also should be noted that, term " composition " and/or " comprising ", when in these specifications, using, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group.When this uses, term " and/or " comprise any and all combinations of relevant Listed Items.
Fig. 2 A-2F is the sectional view according to each step in the method flow of one embodiment of the invention making metal gate.
At first, provide semiconductor substrate 200, be formed with source electrode, drain electrode, metal gates 201 at described semiconductor base 200, and be formed for reducing the self-alignment silicide layer 202 of contact resistance on described source electrode, drain electrode, metal gates surface.The illustrative examples that can be used as the semi-conducting material of semiconductor base comprises: SiGe (SGOI) on Si, SiGe, SiC, SiGeC, silicon-on-insulator (SOI) or the insulator, but be not limited to this.Preferably, described metal gates 201 is the metal aluminum or aluminum alloy, such as aluminum titanium alloy.Self-aligning metal silicide technology is finished via following steps: in semiconductor substrate surface jet-plating metallization layer, for example comprise the material of nickel (nickel), cobalt (cobalt) and platinum (platinum) or its combination.Then annealing (RTA) technique that is rapidly heated, the partial reaction that metal level is contacted with grid and regions and source/drain forms metal silicified layer.Then use the erodable metal level, but the etchant in unlikely attack metal disilicide layer zone, so that unreacted metal level is removed.Preferably, described self-alignment silicide layer 202 is nickel-silicon metal material.
Then, please refer to Fig. 2 A, after the nickel-silicon structure that forms described self-alignment silicide layer 202, deposition one deck aluminum oxide film 211.Described aluminum oxide film 211 is by for example chemical vapour deposition technique or physical vaporous deposition deposition.Preferably, described alumina layer thickness is 10 ~ 40.Next touch the deposition that stop-layer 212 is carved in pitting.Etching stopping layer can comprise a dielectric material, such as material, nitrogenous material, carbonaceous material or homologue.Etching stopping layer can comprise any number of in several etch stop materials.Non-limiting example comprises that conductor etch stop material, conductor etching stop material and dielectric etch stop material.Preferably, described tactile pitting stop-layer 212 at quarter is silicon nitride material.
Because metal gate is easy to oxidation in air, thereby can form the oxide layer 220 that the metal gates autoxidation forms.Then, please refer to Fig. 2 B, form respectively interlayer dielectric layer and photoresist layer.Preferably, interlayer dielectric layer is silicon oxide layer, comprise the material layer that doping or unadulterated silica are arranged that utilizes thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process to form, for example the silex glass of undoped (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).Preferably, form respectively the first interlayer dielectric layer 221 and the second interlayer dielectric layer 222.Preferably, insert a silicon nitride layer in the second interlayer dielectric layer 222, this silicon nitride layer is hard mask layer and the exhaustion layer 223 in the argon sputtering technology.Preferably, the distance on described hard mask layer and exhaustion layer 223 to second interlayer dielectrics 222 surfaces is 30 ~ 100.Preferably, described nitride layer is used as reducing the critical size of contact hole.Preferably, before forming photoresist layer 225, also comprise formation bottom anti-reflection layer 224.Bottom anti-reflection layer (BARC) can be divided into two large classes: the first kind is the organic bottom antireflective layer, and this type of bottom anti-reflection layer has been widely used in the IC processing procedure.The organic bottom antireflective layer generally has absorbability than the photoresistance that covers on it, and its coating method adopts the rotary coating mode.The Equations of The Second Kind bottom anti-reflection layer is the inorganic bottom anti-reflection layer with the chemical vapour deposition technique growth.It has the advantage that composition is adjustable and thickness is adjustable, so can eliminate the reflection on the high reflective substrate of difference fully.This class bottom anti-reflection layer material has amorphous phase carbon film (a-C), silicon nitride (SiN), silicon oxynitride (SiO
xN
y) and titanium oxide (TiO) etc.
Next shown in Fig. 2 C, carry out the graphical definition of contact hole.Adopt dry etching to implement the main etching operation and form contact hole, contact hole etching is carved stop-layer 212 in tactile pitting and is stopped.The nickel that described aluminum oxide film 211 is self-alignment silicide layer 202-silicon protective layer, and in the argon sputtering technology, be opened.
Next shown in Fig. 2 D, remove photoresist layer 225 and bottom anti-reflection layer 224 by photoresistance ashing (Photo Resist Ashing) process, and remove a part by lithographic method and touch pitting stop-layer 212 at quarter, form completely Metal Contact for making follow-up contact metal deposition.Then, please refer to Fig. 2 E, carry out the argon sputtering technology, open the oxide layer 220 that the metal gates autoxidation forms.At last, please refer to Fig. 2 F, carry out the contact metal deposition, and by the cmp smooth surface.Preferably, contact metal 230 adopts the tungsten deposition.
As shown in Figure 3, for make a kind of process chart of metal gate according to one embodiment of the invention.In step 301, at first provide the semiconductor substrate.In step 302, form source electrode, drain electrode, metal gates and be formed at source electrode, drain electrode, the lip-deep self-alignment silicide layer of metal gates at semiconductor base.In step 303, at described semiconductor base deposition one deck aluminum oxide film.In step 304, form and touch pitting stop-layer at quarter.In step 305, form the first interlayer dielectric layer, the second interlayer dielectric layer, hard mask and exhaustion layer, bottom anti-reflection layer and photoresist layer.In step 306, carry out the graphical definition of contact hole.In step 307, remove photoresist layer and bottom anti-reflection layer by the photoresistance podzolic process, and remove a part by lithographic method and touch pitting stop-layer at quarter.In step 308, carry out the argon sputtering technology, remove the oxide layer that the metal gates autoxidation forms.In step 309, carry out the contact metal deposition, and by the cmp smooth surface.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (11)
1. the manufacture method of a metal gate comprises:
Semiconductor base is provided;
The self-alignment silicide layer that forms source electrode, drain electrode, metal gates and be formed at source electrode, drain electrode, metal gates surface at described semiconductor base;
Deposition of aluminium oxide film on described semiconductor base;
Form and touch pitting stop-layer at quarter;
Form interlayer dielectric layer;
Form photoresist layer;
Carry out the graphical definition of contact hole;
Remove described photoresist layer and a part and touch pitting stop-layer at quarter;
Carry out the argon sputtering technology, remove the aluminum oxide film at described metal gates top and the oxide layer that autoxidation forms.
2. method according to claim 1, wherein said self-alignment silicide layer is nickel-silicon metal material.
3. method according to claim 1, wherein said aluminum oxide film film thickness is 10 ~ 40.
4. method according to claim 1, it is silicon nitride material that stop-layer is carved in wherein said tactile pitting.
5. method according to claim 1, wherein said metal gates is metallic aluminium or aluminum titanium alloy material.
6. method according to claim 5 is characterized in that, inserts a silicon nitride layer in described interlayer dielectric layer, and this silicon nitride layer is hard mask layer and the exhaustion layer in the argon sputtering technology.
7. method according to claim 6, wherein said silicon nitride layer is 30 ~ 100 to the distance on described interlayer dielectric layer surface.
8. method according to claim 6, wherein said silicon nitride layer is used as reducing the critical size of described contact hole.
9. method according to claim 1 is characterized in that, also comprises the formation bottom anti-reflection layer before forming photoresist layer.
10. method according to claim 9 is characterized in that, also comprises removing described bottom anti-reflection layer after removing described photoresist layer.
11. method according to claim 1 is characterized in that, also comprises the step of contact metal deposition and cmp after carrying out the argon sputtering technology.
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| CN201110256164.7A CN102969231B (en) | 2011-09-01 | 2011-09-01 | A kind of manufacture method of metal gate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217990A (en) * | 2013-06-04 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Method for formation of contact hole |
| CN104347486A (en) * | 2013-08-06 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1670979A (en) * | 2004-03-18 | 2005-09-21 | 国际商业机器公司 | Phase change memory cell on silicon-on insulator substrate |
| CN101286452A (en) * | 2007-04-09 | 2008-10-15 | 联华电子股份有限公司 | Method for manufacturing metal-oxide-semiconductor transistor element |
| CN101286478A (en) * | 2007-04-11 | 2008-10-15 | 联华电子股份有限公司 | CMOS transistor and manufacturing method therefor |
-
2011
- 2011-09-01 CN CN201110256164.7A patent/CN102969231B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1670979A (en) * | 2004-03-18 | 2005-09-21 | 国际商业机器公司 | Phase change memory cell on silicon-on insulator substrate |
| CN101286452A (en) * | 2007-04-09 | 2008-10-15 | 联华电子股份有限公司 | Method for manufacturing metal-oxide-semiconductor transistor element |
| CN101286478A (en) * | 2007-04-11 | 2008-10-15 | 联华电子股份有限公司 | CMOS transistor and manufacturing method therefor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217990A (en) * | 2013-06-04 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Method for formation of contact hole |
| CN104347486A (en) * | 2013-08-06 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN104347486B (en) * | 2013-08-06 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for forming contact hole |
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