JP5074093B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a high breakdown voltage semiconductor device and a method for manufacturing the same.

  Conventionally, a mesa diode is known as a rectifier for high power. A conventional mesa diode will be described with reference to FIG.

An N ⁻ type semiconductor layer 101 in which an N type impurity is diffused at a low concentration is formed on one surface (hereinafter referred to as a surface) of the N ⁺ type semiconductor substrate 100. A P-type semiconductor layer 102 in which P-type impurities are diffused is formed on the surface of the N ⁻ -type semiconductor layer 101, and the insulating film 103 and the P-type semiconductor layer 102 are electrically connected to the P-type semiconductor layer 102. An anode electrode 104 connected to is formed. Further, a mesa groove 105 reaching the N ⁻ type semiconductor layer 101 from the surface of the semiconductor substrate 100 is formed. A cathode electrode 106 is formed on the other surface (hereinafter referred to as the back surface) of the semiconductor substrate 100.

  The inner wall of the mesa groove 105 is gently inclined in a U shape from the front surface side to the back surface side of the semiconductor substrate 100, and a passivation film 107 containing an insulating material such as glass is formed on the inner wall surface.

Techniques related to the present invention are described in, for example, the following patent documents.
Japanese Patent Laid-Open No. 2003-347306

  In the mesa type semiconductor device as described above, it is required to improve the breakdown voltage when a reverse bias is applied. Therefore, the present inventor has found that the breakdown voltage can be improved by forming the mesa structure as follows. That is, in the case of the conventional structure shown in FIG. 8, the entire inner wall of the mesa groove 105 was inclined, but it was found that the breakdown voltage can be improved by making the side wall of the mesa groove perpendicular to the substrate surface. It was. This is presumably because the depletion layer near the mesa groove is likely to spread, and charge concentration is less likely to occur compared to the conventional structure.

  Therefore, when a mesa groove having a more vertical side wall portion was formed by a highly anisotropic dry etching process, the breakdown voltage could be improved. In this dry etching process, for example, the reaction gas is turned into plasma in a vacuum chamber, and the semiconductor substrate is etched using the high-density plasma.

  However, it has been found that when a mesa groove having a vertical side wall is formed by the conventional method, the breakdown voltage is improved, but the following problem is newly generated. First, there is a problem that a leak current near the mesa groove is large and desired operation characteristics cannot be obtained.

  In addition, since the width of the mesa groove is fine from the viewpoint of designing the chip size to be small, when a material that becomes a passivation film (for example, glass paste) is applied in the mesa groove by a screen printing method or a dispensing method, the material It was very difficult to apply with good coverage. In particular, the passivation film is likely to be insufficiently covered in the upper part near the surface of the semiconductor substrate. Accordingly, such a lack of passivation film coverage causes a defect in the semiconductor device (for example, generation of cracks in the passivation film due to mechanical stress, penetration of corrosive substances such as moisture and dust, generation of local leakage current, etc.). There was a problem. Although it may be possible to easily apply the material of the passivation film into the groove by increasing the width of the groove, this increases the chip size and cannot form a fine semiconductor device.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a high breakdown voltage and capable of reducing a leakage current, and further improving the passivation film coverage without increasing the chip size, and a method for manufacturing the same. .

The present invention has been made in view of the above problems, and its main features are as follows. That is, a semiconductor device of the present invention includes a semiconductor substrate, a first semiconductor layer of the first conductivity type formed on the semiconductor substrate, and a second conductor type of the second conductivity type formed on the first semiconductor layer. Two semiconductor layers, an insulating film formed on the surface of the second semiconductor layer, and a passivation film that covers end portions of the insulating film and covers side surfaces of the first and second semiconductor layers, The first semiconductor layer and the second semiconductor layer are in contact with each other to form a PN junction, and the side surfaces of the first and second semiconductor layers are formed on the semiconductor substrate at the PN junction. The side surface of the second semiconductor layer is perpendicular to the surface, and the side surface of the second semiconductor layer is inclined to the surface of the semiconductor substrate at a portion closer to the surface of the second semiconductor layer than the PN junction portion Yes, and an end portion of the insulating film includes an inclined portion of said second semiconductor layer And to continue to tilt, and an end portion of the insulating film is covered with the passivation film.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate on which a first conductive type first semiconductor layer is formed; and a second conductive type second semiconductor layer on the first semiconductor layer. Forming a PN junction by the first and second semiconductor layers, forming an insulating film on the second semiconductor layer, and forming a semiconductor substrate from the surface side of the insulating film . The groove is cut halfway in the thickness direction to form a groove exposing the first and second semiconductor layers, and side surfaces of the first and second semiconductor layers are formed on the surface of the semiconductor substrate at the PN junction. A first etching step that is processed so as to be perpendicular to the groove; and an inner wall of the groove is flattened, and a portion of the inner wall of the groove that is closer to the surface of the second semiconductor layer than the PN junction is formed. And the end of the insulating film is inclined A second etching step of tilting of the semiconductor layer and the Ru is continuously inclined, that from the insulating film end portion overlying said groove in a step of forming a passivation film that extends outside of the groove Features.

  The semiconductor device according to the present invention includes first and second semiconductor layers constituting a PN junction, and the side surfaces of the first and second semiconductor layers at the PN junction are formed perpendicular to the surface of the semiconductor substrate. is doing. Therefore, when a reverse bias is applied, charge concentration near the PN junction portion is less likely to occur than in the conventional structure, and the breakdown voltage can be improved.

  Further, the side surface of the second semiconductor layer is inclined with respect to the surface of the semiconductor substrate at a portion closer to the surface of the second semiconductor layer than the PN junction. Therefore, the passivation film is formed with good coverage.

  Next, embodiments of the present invention will be described with reference to the drawings. 1 to 6 are cross-sectional views or plan views respectively shown in the order of manufacturing steps. Note that the manufacturing process described below is performed using a wafer-shaped semiconductor substrate, and a large number of semiconductor devices are formed in a matrix with a predetermined dicing line as a boundary. A process for forming two semiconductor devices will be described.

First, as shown in FIG. 1, an N ⁻ type semiconductor layer 2 is formed on an N ⁺ type semiconductor substrate 1 having a thickness of about 200 μm by a known epitaxial crystal growth method. Note that N-type impurities such as phosphorus are diffused in the semiconductor substrate 1 at a high concentration, and the back surface of the semiconductor substrate 1 is connected to a cathode electrode 7 described later.

Next, a P-type semiconductor layer 3 is formed by thermally diffusing a P-type impurity such as boron in the N ⁻ -type semiconductor layer 2. As a result, the PN junction 4 is formed substantially parallel to the main surface of the semiconductor substrate 1 at the interface between the N ⁻ type semiconductor layer 2 and the P type semiconductor layer 3.

  Next, an insulating film (for example, a silicon oxide film formed by a thermal oxidation method or a CVD method) is formed on the surface of the semiconductor substrate 1, and then the insulating film is selectively etched using a predetermined mask. Thus, as shown in FIG. 2, an insulating film 5 having an opening is formed on at least a part of the P-type semiconductor layer 3. Next, an anode electrode 6 made of a conductive material such as aluminum is formed on the P-type semiconductor layer 3 exposed from the opening by, for example, sputtering or vapor deposition. Further, a cathode electrode 7 made of a conductive material such as aluminum is formed on the back surface of the semiconductor substrate 1 by the same method as the anode electrode 6.

Next, as shown in FIG. 3, a resist layer 9 having an opening in a region where the groove 8 is to be formed is selectively formed on the surface of the semiconductor substrate 1. Next, the insulating film 5 and the semiconductor substrate 1 are moved in the thickness direction of the semiconductor substrate 1 by anisotropic etching (first etching) using the resist layer 9 as a mask, at least from the PN junction 4. The semiconductor substrate 1 is deeply cut to form the grooves 8. Accordingly, the side surfaces of the P-type semiconductor layer 3 and the N ⁻ -type semiconductor layer 2 are exposed by the formation of the grooves 8.

  The width of the groove 8 is about 50 μm and the depth is about 100 μm. Further, the PN junction portion 4 is separated by the groove 8, and the region surrounded by the groove 8 becomes the main operation region of the semiconductor device (diode in the present embodiment) finally obtained.

  The inner wall of the groove 8 is perpendicular to the main surface of the semiconductor substrate 1. Note that the term “perpendicular” here means that it is ideally 90 degrees with respect to the main surface of the semiconductor substrate 1, but it is assumed that a slight angle deviation due to etching conditions is also included vertically. The bottom of the groove 8 is formed in parallel to the main surface of the semiconductor substrate 1 and the PN junction 4.

As the first etching, dry etching using an etching gas such as CF, HBr, SF ₆ , or Cl ₂ is preferable, or a Bosch process may be used. The Bosch process includes a plasma etching process in which the surface of a semiconductor substrate is isotropically etched mainly using SF ₆ gas, and a carbon polymer mainly using C ₄ F ₈ gas on the inner wall of a groove formed by the plasma etching process. In this process, the semiconductor substrate is vertically and deeply anisotropically etched by periodically repeating both steps of the plasma deposition step of depositing as a protective film.

  Further, when the groove 8 is formed by dry etching including the dry etching using a CF-based gas, HBr-based gas, or the like, or the Bosch process, the inner wall of the groove 8 is often rough due to plasma damage during the etching. For this reason, it is considered that the roughness of the inner wall is a cause of the leakage current that has conventionally occurred.

  The groove 8 may be formed in a slit shape vertically and horizontally so as to correspond to the boundary (dicing line DL1) of each semiconductor device finally divided into pieces as shown in FIG. 4A. As shown, it may be formed in a ring shape inside each section surrounded by the boundary (dicing line DL2) of each semiconductor device. 4A and 4B are schematic plan views showing the relationship between the boundaries of the individual semiconductor devices and the grooves 8.

Next, isotropic etching (second etching) is performed on the groove 8. The isotropic etching is preferably a wet etching process using a predetermined chemical solution (preferably an acid-based chemical solution). Alternatively, isotropic etching by chemical dry etching (CDE) may be used. Thereby, the roughness generated on the inner wall of the trench 8 is removed, and the inner wall of the trench 8 (that is, the side surfaces of the P-type semiconductor layer 3 and the N ⁻ -type semiconductor layer 2) is planarized.

  Further, since the etching is isotropic, the etching proceeds in the horizontal direction, and the upper portion 10 of the groove 8 (the portion close to the surface of the P-type semiconductor layer 3) is on the surface side of the semiconductor substrate 1 as shown in FIG. As it approaches, it becomes rounded and inclined. The end portion of the insulating film 5 is also etched in the same manner, and the end portion of the insulating film 5 is continuously inclined with the inclination of the upper portion 10 of the groove 8 (inclination of the side surface of the P-type semiconductor layer 3). The second etching is performed to such an extent that the vertical shape portion thereof does not change excessively except for the upper portion 10 of the groove 8.

Next, the resist layer 9 is removed. Next, as shown in FIG. 6, a passivation film 11 is formed in the trench 8, and the P-type semiconductor layer 3 and the N ⁻ -type semiconductor layer 2 exposed from the trench 8 are covered with the passivation film 11. The passivation film 11 is preferably formed to extend from the upper part 10 of the groove 8 onto the insulating film 5 outside the groove 8. Thus, by extending the passivation film 11 on the surface of the insulating film 5 (or the semiconductor substrate 1 in the case of a semiconductor device that does not require the formation of the insulating film 5), the P-type semiconductor layer 3 and the N ⁻ type are formed from the groove 8. The semiconductor layer 2 can be completely prevented from being exposed to the outside, and leakage current can be prevented.

  Formation of the passivation film 11 is performed as follows. For example, a screen printing method in which a paste-like material is applied using a predetermined printing mask and squeegee, a so-called dispensing method in which a paste-like material is applied with a dispenser along the groove 8 formation region, or a spin coating method. A material is applied in the groove 8 by using it. And the passivation film 11 is formed by giving heat processing after that and hardening the said paste-form material. The passivation film 11 is preferably made of a material having high insulating properties and good embedding in the groove 8, and a glass paste containing a polyimide resin, a lead-based or zinc-based glass powder, and a resin. Etc. are preferably used.

  Here, since the upper portion 10 of the groove 8 is rounded and inclined as described above, the material of the passivation film 11 can easily enter the groove 8. Therefore, it is possible to uniformly apply the material into the groove 8 and form the passivation film 11 with good coverage, and as a result, a semiconductor device with high breakdown voltage and high reliability can be manufactured.

  In addition, the material and formation method of the passivation film 11 are not limited to the above, For example, insulating films, such as a silicon nitride film formed by CVD method, may be sufficient. Even in this case, since the upper portion 10 of the groove 8 is rounded, it is covered as compared with the case where the second etching process is not performed (the case where the upper portion of the groove has a right-angled shape with no inclination). It is possible to form the passivation film 11 having good properties.

  Next, the semiconductor substrate 1 is cut along a predetermined dicing line DL to obtain chip-shaped individual semiconductor devices. As a method for dividing the semiconductor substrate 1, there are a dicing method, an etching method, a laser cut method and the like.

  Here, when the groove 8 is formed along the dicing line DL1 as shown in FIG. 4A, the semiconductor substrate 1 is cut along substantially the center of the groove 8. In other words, each semiconductor device is separated with the groove 8 as a boundary. Therefore, since the chip size is equal to the operation region range, the semiconductor device can be miniaturized.

  In addition, as shown in FIG. 4B, when the groove 8 is not formed along the dicing line DL2, but is formed in a ring shape inside each individual semiconductor device to be separated, an insulating film 5 and the semiconductor substrate 1 are cut along the dicing line DL2. Therefore, since stress due to contact of a dicing blade, a laser, or the like is not applied to the passivation film 11, it is possible to effectively suppress the generation of cracks in the passivation film 11. In particular, when the passivation film 11 includes a glass material, it has a tendency to be difficult to cut with a dicing blade or the like because of its high hardness. For this reason, it is effective to separate the dicing line and groove formation positions as shown in FIG. 4B when it is difficult to cut the passivation film 11.

The semiconductor device (diode) including the groove 8 is completed through the above steps. In the configuration of the present embodiment, the inner wall of the groove 8 (side surfaces of the P-type semiconductor layer 3 and the N ⁻ -type semiconductor layer 2) is formed vertically at the PN junction 4. Therefore, compared to the conventional structure, the concentration of electric charges in the vicinity of the PN junction 4 is less likely to occur, and the breakdown voltage when applying a reverse bias can be improved. Moreover, since the groove can be formed as deep as possible within the range in which the mechanical strength of the semiconductor substrate 1 is maintained, the structure is suitable for improving the breakdown voltage. Furthermore, in the mesa groove 105 having the conventional structure (see FIG. 8), the width increases according to the depth of the mesa groove 105, but the groove of this embodiment has no such restriction and has a high aspect ratio. Therefore, even if the groove is deepened as compared with the conventional structure, the width does not expand. Therefore, the chip size is reduced, the number of semiconductor devices obtained from one wafer is increased, and the manufacturing cost is kept low. Can do.

Further, the inner wall of the groove 10 (side surfaces of the P-type semiconductor layer 3 and the N ⁻ -type semiconductor layer 2) is flattened by the second etching process described above. Therefore, leakage current can be reduced.

  Further, the upper portion 10 of the groove 8 is rounded and inclined. Therefore, the passivation film 11 can be formed in the groove 8 with good coverage, and defects due to insufficient coverage of the passivation film 11 (for example, generation of cracks in the passivation film due to mechanical stress, corrosion substances such as moisture and dust). Intrusion, local leakage current generation, breakdown voltage degradation, etc.) can be prevented.

  Needless to say, the present invention is not limited to the above-described embodiment, and can be changed without departing from the gist thereof. For example, in the above-described embodiment, the passivation film 11 is directly formed in the trench with respect to the exposed surface of the semiconductor substrate 1, but the passivation film 11 and the semiconductor are formed by adding an insulating film forming process such as a thermal oxide film. Another insulating film may be formed between the substrate 1 and the substrate 1. Alternatively, it is possible to form only an insulating film in the trench by a thermal oxidation method or a CVD method.

In the above-described embodiments, the semiconductor device functioning as a diode has been described. However, the present invention can be similarly applied to bipolar transistors, MOSFETs, IGBTs, thyristors, etc. , Improvement of the passivation film coverage, etc.) can be obtained. Specifically, for example, the present invention can be applied to a bipolar transistor as shown in FIG. In the bipolar transistor, an N ⁺ type semiconductor layer 20 is formed on the surface layer of the P type semiconductor layer 3, and an emitter connected to the N ⁺ type semiconductor layer 20 through the opening of the insulating film 5 on the semiconductor substrate 1. An electrode 21 is formed. A base electrode 22 connected to the P-type semiconductor layer 3 through another opening of the insulating film 5 is formed on the surface of the semiconductor substrate 1. A collector electrode 23 is formed on the back surface of the semiconductor substrate 1. In addition, about the structure similar to the structure already demonstrated, the same code | symbol is shown and the description is abbreviate | omitted.

It is sectional drawing explaining the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing process. It is a top view explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing process. It is sectional drawing explaining the semiconductor device which concerns on the example of a change of this invention. It is sectional drawing explaining the conventional semiconductor device.

Explanation of symbols

1 semiconductor substrate 2 N ^- -type semiconductor layer 3 P-type semiconductor layer 4 PN junction 5 support 6 the anode electrode 7 cathode electrode 8 grooves
9 Resist layer 10 Upper part 11 Passivation film
20 N ⁺ type semiconductor layer 21 Emitter electrode 22 Base electrode
23 Collector electrode 100 Semiconductor substrate 101 N ^- type semiconductor layer
102 P-type semiconductor layer 103 Insulating film 104 Anode electrode 105 Mesa groove 106 Cathode electrode 107 Passivation film

Claims (3)

A semiconductor substrate;
A first conductivity type first semiconductor layer formed on the semiconductor substrate;
A second conductivity type second semiconductor layer formed on the first semiconductor layer;
An insulating film formed on the surface of the second semiconductor layer;
A passivation film that covers an end portion of the insulating film and covers side surfaces of the first and second semiconductor layers;
The first semiconductor layer and the second semiconductor layer are in contact with each other to form a PN junction;
Side surfaces of the first and second semiconductor layers are perpendicular to the surface of the semiconductor substrate at the PN junction,
Side surface of the second semiconductor layer have a sloped portion that is inclined with respect to the surface of the semiconductor substrate at a portion close to the surface of the second semiconductor layer from the PN junction,
An end portion of the insulating film is continuously inclined with an inclined portion of the second semiconductor layer, and the end portion of the insulating film is covered with the passivation film . Preparing a semiconductor substrate on which a first semiconductor layer of a first conductivity type is formed;
Forming a second conductivity type second semiconductor layer on the first semiconductor layer, and forming a PN junction with the first and second semiconductor layers;
Forming an insulating film on the second semiconductor layer;
Cutting is performed from the surface side of the insulating film to the middle of the thickness direction of the semiconductor substrate to form a groove exposing the side surfaces of the first and second semiconductor layers, and for the first and second semiconductor layers. A first etching step of processing a side surface to be perpendicular to the surface of the semiconductor substrate at the PN junction;
The inner wall of the groove is flattened, the portion of the inner wall of the groove that is closer to the surface of the second semiconductor layer than the PN junction is inclined , and the end of the insulating film is made to be the second semiconductor a second etching step of Ru is continuously inclined and the inclined layer,
Forming a passivation film that covers an end portion of the insulating film and extends from the inside of the groove to the outside of the groove . 3. The method of manufacturing a semiconductor device according to claim 2 , wherein the step of forming the passivation film includes a step of applying a paste-like material in the groove.

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