CN106098791A - U-shaped etching right angle table top silicon diode and silicon core thereof and preparation method - Google Patents
U-shaped etching right angle table top silicon diode and silicon core thereof and preparation method Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 152
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 113
- 239000010703 silicon Substances 0.000 title claims abstract description 110
- 238000005530 etching Methods 0.000 title claims abstract description 67
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000013078 crystal Substances 0.000 claims abstract description 60
- 238000009792 diffusion process Methods 0.000 claims abstract description 47
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 40
- 239000012535 impurity Substances 0.000 claims abstract description 34
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 20
- 239000000126 substance Substances 0.000 claims abstract description 17
- 239000007788 liquid Substances 0.000 claims abstract description 9
- 239000003292 glue Substances 0.000 claims abstract description 5
- 238000002161 passivation Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 230000007797 corrosion Effects 0.000 claims description 9
- 238000005260 corrosion Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 5
- 239000003550 marker Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000000465 moulding Methods 0.000 abstract description 7
- 238000003825 pressing Methods 0.000 abstract description 3
- 238000011031 large-scale manufacturing process Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 14
- 230000005684 electric field Effects 0.000 description 10
- 230000002159 abnormal effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000001788 irregular Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 210000003793 centrosome Anatomy 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 102100028717 Cytosolic 5'-nucleotidase 3A Human genes 0.000 description 1
- 101710095312 Cytosolic 5'-nucleotidase 3A Proteins 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003518 caustics Substances 0.000 description 1
- 210000002421 cell wall Anatomy 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000001815 facial effect Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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Abstract
The invention discloses a kind of U-shaped etching right angle table top silicon diode and silicon core thereof and preparation method.Preparation method comprises the steps: 1) diffuse into P+ type and N+ type impurity on positive and negative two surfaces of N type (110) crystal face silicon single crystal flake the most simultaneously, obtain P+N N+ type silicon diffusion wafer;2) positive and negative at P+N N+ type silicon diffusion wafer plate nickel dam;3) anticorrosive glue is coated in the positive and negative at P+N N+ type silicon diffusion wafer, and N+ face is opened groined type etching tank window;4) with anisotropic silicon preferential etch liquid, the N+ face groined type etching tank window of silicon diffusion wafer is carried out chemical attack, it is thus achieved that U-shaped etching right angle table top P+N N+ type silicon core;5) U-shaped etching right angle table top P+N N+ type silicon core is removed photoresist, sawing, weld, clean, mesa passivation, pressing mold molding, be packaged into silicon diode.Simplified manufacturing process of the present invention, low cost, it is easy to large-scale production, product cost is higher, produces distinct economic.
Description
Technical field
The present invention relates to the manufacture of semiconductor device, particularly relate to a kind of U-shaped etching right angle table top silicon diode and silicon thereof
Core and preparation method.
Background technology
It is known that silicon diode is most important basic device, in applications of electronic circuitry, the reverse breakdown of PN junction
Voltage VBWith device forward voltage drop VFFor two most important unit for electrical property parameters of silicon diode, they all with manufacture device raw material
The resistivity of silicon single crystal is directly related.The resistivity of silicon single crystal used is the highest, the breakdown reverse voltage V of diode PN junctionBIt is the highest,
Device forward voltage drop VFThe biggest.Require that silicon diode can bear high reverse operation during the work of high-pressure electronic circuit pressure, simultaneously
There is alap device forward voltage drop VF, there is therebetween contradiction, must do one's utmost to dissolve it.Current conventionally fabricated silicon
The method of diode silicon core right angle table top is typically: directly silicon is spread wafer carries out sawing acquisition, then carries out table top
Chemical attack is to remove the table top mechanical damage that sawing causes.The right angle platform facial deformity that the method obtains is irregular, is easily caused
Low-voltage punctures.
Summary of the invention
It is an object of the invention to solve problems of the prior art, and a kind of U-shaped etching right angle table top silicon is provided
Diode silicon core.Concrete technical scheme of the present invention is as follows:
U-shaped etching right angle table top silicon diode silicon core, the most respectively P+ type impurity diffusion layer, original silicon single crystal N-type layer
With N+ type impurity diffusion layer, the table top of silicon core side is rectangular, and described right angle table top is the most smooth plane.In the present invention
Described the most smooth referring to that the smooth-sided compression candles of right angle table top is straight, silicon lattice structure is complete, does not haves direct saw cutting warp again
The irregular table top of deformity caused after chemical attack.
As preferably, described right angle table top is to be obtained by the corrosion of anisotropy preferential chemical.
Another object of the present invention is to provide a kind of silicon diffusion wafer preparing described silicon core, be followed successively by from the bottom to top
P+ type impurity diffusion layer, original silicon single crystal N-type layer, N+ type impurity diffusion layer, nickel dam and anticorrosive glue-line, described nickel dam and
Offering groined type etching tank window on anticorrosive glue-line, groined type etching tank window is through to table on N+ type impurity diffusion layer
Face.
Another object of the present invention is to the U-shaped etching right angle table top silicon diode providing a kind of described silicon core to prepare, institute
The P+ type impurity diffusion layer stated connects diode cathode, and N+ type impurity diffusion layer connects diode cathode.
Another object of the present invention is to provide the preparation method of a kind of U-shaped etching right angle table top silicon diode, its step
Rapid as follows:
1) front at (110) crystal face silicon single crystal flake of N-type diffuses into the boron semiconductor impurities of P+ type, and reverse side diffuses into N simultaneously
The phosphorus semiconductor impurities of+type, obtains P+N-N+ type silicon diffusion wafer;
2) obverse and reverse at P+N-N+ type silicon diffusion wafer plates nickel dam;
3) on the obverse and reverse nickel dam of P+N-N+ type silicon diffusion wafer, coat anticorrosive glue, sawing is passed through in N+ face
Anticorrosive glue-line and nickel dam, open the through groined type etching tank window to N+ type impurity diffusion layer upper surface;
4) use anisotropic silicon preferential etch liquid that N+ face groined type etching tank window is carried out supersonic vibration chemical attack reaction,
Above-mentioned corrosion reaction is only along longitudinally carrying out and be laterally automatically stopped, thus obtains U-shaped etching right angle table top P+N-N+ type silicon core;
5) U-shaped etching right angle table top P+N-N+ type silicon core is removed photoresist, sawing, weld, clean, mesa passivation and being compression molded into
Type, is packaged into silicon diode.
As preferably, described step 1) in (110) crystal face silicon single crystal flake of N-type there is the location mark in (111) crystal orientation
Will line.
As preferably, described step 3) in N+ face in the etching tank window opened, groined type each bar limit is put down respectively
Row or be perpendicular to the witness marker line in silicon single crystal flake (111) crystal orientation.
As preferably, described groined type etching tank window uses automatic sawing, cutting to remove anticorrosive glue-line and the unlatching of nickel dam
Method, the edge width of selected saw blade is 200um.
As preferably, described step 4) in anisotropic silicon preferential etch liquid consisting of with mass ratio range: KOH:
H2O=1:10, chemical attack reaction temperature is 90~95 DEG C.
The present invention is only the most pressure in the hope of obtaining silicon diode height reverse operation by improving single crystal silicon resistivity, but passes through
Tap the latent power on terminal moulding and the silicon crystal lattice of silicon diode PN junction are complete power, receive simultaneously and be effectively improved silicon diode reverse operation
The pressure ideal effect with reduction device forward voltage drop.Specific practice is that silicon diode PN junction border is fabricated to U-shaped etching is straight
Angle mesa structure pattern, it is therefore intended that PN junction border obtains the right angle table top of rule and the most complete silicon lattice structure, as
This makes PN junction border have the identical generous space charge layer (relevant principle refers to aftermentioned) with in PN junction centrosome, and result makes PN
The backward voltage electric field intensity of junction boundary scope keeps identical with the electric field intensity in PN junction centrosome, and this point is significant,
As long as because the electric field that there is certain on PN junction inside or junction boundary the most suddenly increases reaches marginal value, soon there is PN junction
Backward voltage avalanche breakdown.Theoretical and practice confirms, under bearing identical working inverse voltage situation, compares shown in Fig. 4
The irregular eutectic of right angle table top PN junction obtained by common sawing molding, U-shaped etching right angle table top is made on silicon PN junction border can
Substantially reverse silicon diode reverse operation time on PN junction border time and starting low backward voltage avalanche breakdown so damage electricity
The passive situation of electronic circuit, it is ensured that the breakdown reverse voltage V of diode PN junctionBKeep reaching a comparatively ideal average level.
Owing to the silicon PN junction border of manufacture of the present invention has U-shaped etching right angle mesa structure, make silicon diode PN junction breakdown reverse voltage
VBThe realization of index is substantially dependent on the ideal case of PN junction central interior backward voltage avalanche breakdown level, the then present invention
Only need to consider reasonably to choose the theoretical value parameter of silicon material resistivity when designing device, and without staying extra allowance,
Such then take into account again and reduce device forward voltage drop VFTarget, kill two birds with one stone just.
Say one say that what is " U-shaped etching right angle " below?See Fig. 2, the represented P+N-N being the present invention and manufacturing in figure
One cross section of+type silicon core, it is therefore apparent that the angle between PN junction boundary line and the horizontal bottom in cross section is that U-shaped etching forms
Right angle, so the P+N-N+ type silicon core also known as Fig. 2 is right angle mesa structure.
The present invention introduced below is how to make U-shaped etching right angle table top.It is known that there are three crystalline substances in silicon single crystal body
To, be called (111), (110), (100) crystal orientation, relevant each face perpendicular with above crystal orientation be called 111},
{ 100}, { 110} series crystal face, the research of silicon atom structure points out: in silicon single crystal body, the silicon atom density of number (111) crystal faces
For the highest, the silicon atom density of (110) crystal face is minimum, if using KOH solution to make the caustic of silicon, then on (111) crystal orientation
Corrosion rate be minimum, low to being less than on (110) direction, crystal orientation 1/10th of corrosion rate, so also known as this phenomenon being
The anisotropy preferential etch of silicon.Ironically, the most rotten from the groined type groove window of (110) crystal plane surface when KOH solution
During erosion silicon single crystal flake, chemical reaction is automatically stopped the most at last on sidewall, is obtained " U " type etching tank four sidewall is all
(111) crystal face, as shown in Figure 2.Particularly point out, for obtaining rule " u " type groove, first (110) crystal face silicon single crystal flake must be by
(111) crystal orientation strictly positions, and the groined type secondly opened at silicon chip surface treats that etching tank window each bar limit must be with (111) of silicon
Location, crystal orientation line is perpendicular or parallel.Fig. 1 gives the intersecting lens of (110) crystal face silicon wafer and (111) crystal face the most visually
(being represented by dotted lines), contrast see Fig. 1 and Fig. 2 it finds that, right angle (the U groove of the U-shaped table top of the P+N-N+ type silicon core shown in Fig. 2
Base angle) i.e. it is equal to silicon (111) crystal face shown in Fig. 1 and intersects formed right angle with (110) crystal face.
It is set forth below why silicon core PN junction has selected U-shaped etching right angle table top just can improve the breakdown reverse voltage of silicon PN junction
VBProblem, the ultimate principle of semiconductor PN points out: when the original silicon single crystal flake a certain conduction type (N-type or p-type)
Middle mix abnormity conduction (p-type or N-type) semiconductor impurities time, i.e. formed in the interface moment in two kinds of special-shaped conductive impurity districts
PN junction, this is that the concentration distribution of impurity owing to being mixed in quasiconductor from outward appearance to inner essence also exists Concentraton gradient, the most just leads
Induced semiconductor carrier (electronics and hole) is along the diffusion motion in impurity concentration gradient direction, and the current-carrying concurrently caused
The son drift motion along PN junction built-in field direction, two kinds of interaction between moving also tend to balance, and result is built at PN junction center
Erect space-charge region, see Fig. 3.Leaning on side, P district in space-charge region is negative fixed charge, is just to fix electricity by side, N district
Lotus, positive fixed charge and negative fixed charge are the most equal.From positive fixed charge layer to negative fixed charge layer i.e. now
Producing PN junction built-in field E, negative fixed charge layer is pointed to by positive fixed charge layer in direction, and result PN junction is in balance and stability shape
State.Thereafter, when external circuit applies backward voltage to PN junction, the original balance of PN junction is broken, applied voltage electric field driven silicon
Middle carrier makees the result of drift motion, has thickened space-charge region, and then the electric field intensity in PN junction increases therewith, final PN
Till when knot internal electric field increases to the effect resisting applied voltage completely, PN junction reaches new balance.This i.e. means PN junction
Space-charge region the widest, the working inverse voltage that PN junction can bear will be the highest.And if the space-charge region of PN junction is a certain
Place narrows or any distortion occurs, and sees Fig. 4, the most necessarily causes the fixed charge at this most crowded and high concentration, then
Electric field intensity in PN junction increases the most suddenly herein, and just will rise suddenly to marginal value because of regional area electric field occurs low-voltage snowslide
Puncturing, we are mostly undesired sees for this, just because of be not it is contemplated that in the range of happen suddenly the most prematurely low-voltage
Avalanche breakdown, its hidden danger is bigger.It is clear that the U groove in Fig. 3 is obtained by uniform chemical attack reaction, cell wall platform
Face is straight and smooth, substantially guarantees silicon crystal lattice integrity, then makes at the space charge layer width W holding on PN junction mesa boundaries
Uniformly, its result is as desired by us, due to PN junction U-shaped etching right angle table top borderline back-pressure electric field intensity at place
Uniformity the most everywhere, this is for preventing and being avoided the border of PN junction to be often more easy to, than knot central interior, the backward voltage that takes place frequently
The phenomenon of avalanche breakdown plays key effect.It is known that only when the security boundary of PN junction, just can ensure that PN junction safety
Reliably achieve by internal center breakdown reverse voltage VBThe resistance to voltage levels of theory that index is determined.The U-shaped etching of PN junction is straight in fact
The technology of angle table top just had begun to be applied in semiconductor device manufacturing industry before more than 30 years, except for the difference that prepared
U-shaped etching right angle table top be all the center being located at device PN junction, be not intended in the border terminal moulding of PN junction, Er Qiechun
Essence is from improving silicon chip area utilization rate, integrated level and device current density aspect.For ease of comparing discriminating, special at this
The technique with regard to the current conventionally fabricated right angle open PN junction silicon of table top of anticipating makees an explanation with products characteristics, pays close attention to
Be after prepared P+N-N+ type silicon diffusion wafer, the conventional way obtaining right angle table top is straight by silicon core size specification requirement
Connect and diffusion sheet is sawed into square chips one by one, because the lateral sawing face of chip is completely exposed outside, and put down with chip list
Face is at a right angle, so the right angle table top open PN junction silicon core that is otherwise known as.This manufacture method disadvantage is that silicon core sawing mouth is deep
(running through whole silicon wafer thickness), due to sawing force big, the most necessarily abnormal journey is caused on the PN junction border in silicon core four side stage face
The mechanical damage of degree, is more particularly perpendicular to the deep crystal boundary rift defect of table top, it is necessary to thoroughly remove.Conventional method
It is to utilize the top layer of more than about 100 microns on nitration mixture erosion removal table top.If at that time at PN junction bounds internal memory any one
In place of fourth point does not meets above-mentioned requirements, then PN junction must present low, voltage breakdown characteristic, i.e. under extremely low backward voltage, PN
I.e. there is the biggest abnormal electric leakage in knot, causes product rejection.But the above-mentioned right angle table top acid corrosion amount of exceeding is the most not all right,
Acid excessive erosion, the adverse consequences brought be not only make chip area reduce, device current capacity reduce and forward voltage drop
Increase, but make PN junction right angle table top therefore become abnormal irregular, see Fig. 4, such as by the right angle of sawing previously
The present has become concave shape, even forms the negative bevel on PN junction local boundary.Negative bevel has been intended to negative effect, it is judged that PN border
Whether negative bevel, it is according to being to see that PN junction is lightly doped the sectional area of side, N-district and whether is gradually increasing on knot center position,
The P+N-N+ type silicon core cross section of Fig. 4 start from PN junction center sectional area up tend to really increase, present negative bevel platform
Face pattern, then according to PN junction elrectroneutrality pcharge-neutrality principle, the positive fixed charge being in the N-district lateral boundaries in the range of negative bevel is distributed court
Knot center position indentation, causes the space charge layer of this regional area to narrow, electric field on PN junction local boundary naturally occurs
The abnormal case of concentrations, thus cause PN junction low backward voltage avalanche breakdown, and then damage circuit.
It is an advantage of the invention that technique simplifies, low cost, it is easy to accomplish large-scale production, product cost is higher, produces aobvious
Write economic benefit.
Accompanying drawing explanation
Fig. 1 be silicon single crystal body (111), (110) crystal face intersect silicon atom structural representation;
Fig. 2 is U-shaped etching right angle table top P+N-N+ type silicon core sectional view;
Fig. 3 is space charge layer distribution under U-shaped etching right angle table top PN junction working inverse voltage;
Fig. 4 be common (111) crystal face sawing of silicon wafers molding right angle table top PN junction working inverse voltage under space charge layer distribution.
Detailed description of the invention
With detailed description of the invention the present invention it is further elaborated below in conjunction with the accompanying drawings and illustrates.In the present invention, each is implemented
The technical characteristic of mode, on the premise of not colliding with each other, all can carry out respective combination.
The U-shaped etching right angle table top silicon diode of the present invention solves frequency on conventional right-angle table top silicon diode PN junction border
Send out backward voltage avalanche breakdown and damage the problem of electronic circuit, overcome that currently common silicon diode manufacturing technology aspect exists no
Foot.
The step of the preparation method of U-shaped etching right angle table top silicon diode is as follows:
1) front at (110) crystal face silicon single crystal flake of N-type diffuses into the boron semiconductor impurities of P+ type, and reverse side diffuses into N simultaneously
The phosphorus semiconductor impurities of+type, obtains P+N-N+ type silicon diffusion wafer.The parameter of silicon single crystal flake can be selected according to actual needs
Select.One of which be single-chip resistivity be 10~15 Ω .cm, thickness is 255~260um.Diffusion temperature is 1265~1270
DEG C, diffusion time is 10~15 hours, P+ district junction depth be 60um, N+ district junction depth be 65um, contaminant surface concentration is 1021/cm3。
2) obverse and reverse at P+N-N+ type silicon diffusion wafer plates nickel dam.
3) on the obverse and reverse nickel dam of P+N-N+ type silicon diffusion wafer, coat anticorrosive glue, N+ face is passed through
The anticorrosive glue-line of sawing and nickel dam, open the through groined type etching tank window to N+ type impurity diffusion layer upper surface.Groined type
One group of limit of etching tank window is perpendicular to silicon single crystal flake (111) crystal orientation witness marker line, a width of 200um of etching tank window.Well word
Shape etching tank window uses automatic sawing, cutting to remove anticorrosive glue-line and the open method of nickel dam, the cutting edge width of selected saw blade
Degree is 200um.
4) use anisotropic silicon preferential etch liquid that N+ face groined type etching tank window is carried out supersonic vibration chemical attack
Reaction, above-mentioned corrosion reaction is only along longitudinally carrying out and be laterally automatically stopped, thus obtains U-shaped etching right angle table top P+N-N+ type silicon
Core.Anisotropic silicon preferential etch liquid consisting of with mass ratio range: KOH:H2O=1:10, chemical attack reaction temperature is 90
DEG C~95 DEG C, the chemical attack response time adding supersonic vibration is 10~15 minutes, and the " u "-shaped etching tank degree of depth is 230~235 micro-
Rice.Being derived from U-shaped etching right angle table top silicon diode silicon core, this silicon core is respectively P+ type impurity diffusion layer, former from down to up
Beginning silicon single crystal N-type layer and N+ type impurity diffusion layer, the table top of silicon core side is rectangular, and described right angle table top is the most smooth
Plane.
5) U-shaped etching right angle table top P+N-N+ type silicon core is removed photoresist, sawing, weld, clean, mesa passivation, pressing mold
Molding, is packaged into silicon diode.
Embodiment 1
1) front at (110) crystal face silicon single crystal flake of N-type diffuses into the boron semiconductor impurities of P+ type, and reverse side diffuses into N simultaneously
The phosphorus semiconductor impurities of+type, obtains P+N-N+ type silicon diffusion wafer.The silicon single crystal flake resistivity used in the present embodiment is 15
Ω .cm, thickness is 260um.Diffusion temperature is 1270 DEG C, and diffusion time is 10 hours, and P+ district junction depth is that 60um, N+ district junction depth is
65um, contaminant surface concentration is 1021/cm3。
2) obverse and reverse at P+N-N+ type silicon diffusion wafer plates nickel dam;
3) on the obverse and reverse nickel dam of P+N-N+ type silicon diffusion wafer, coat anticorrosive glue, sawing is passed through in N+ face
Anticorrosive glue-line and nickel dam, open the through groined type etching tank window to N+ type impurity diffusion layer upper surface.Groined type corrodes
One group of limit of groove window is perpendicular to silicon single crystal flake (111) crystal orientation witness marker line, a width of 200um of etching tank window.
4) use anisotropic silicon preferential etch liquid that N+ face groined type etching tank window is carried out supersonic vibration chemical attack
Reaction, above-mentioned corrosion reaction is only along longitudinally carrying out and be laterally automatically stopped, thus obtains U-shaped etching right angle table top P+N-N+ type silicon
Core.Anisotropic silicon preferential etch liquid consisting of with mass ratio range: KOH:H2O=1:10, chemical attack reaction temperature is 95
DEG C, the chemical attack response time adding supersonic vibration is 15 minutes, and the " u "-shaped etching tank degree of depth is 235um.
5) U-shaped etching right angle table top P+N-N+ type silicon core is removed photoresist, sawing, welding (P+ type impurity diffusion layer connect
Diode cathode, N+ type impurity diffusion layer connects diode cathode), clean, mesa passivation and pressing mold molding, be packaged into silicon two pole
Pipe.
Embodiment described above is the one preferably scheme of the present invention, and so it is not intended to limiting the invention.Have
Close the those of ordinary skill of technical field, without departing from the spirit and scope of the present invention, it is also possible to make various change
Change and modification.The technical scheme that the most all modes taking equivalent or equivalent transformation are obtained, all falls within the guarantor of the present invention
In the range of protecting.
Claims (9)
1. a U-shaped etching right angle table top silicon diode silicon core, it is characterised in that from down to up be respectively P+ type impurity diffusion layer,
Original silicon single crystal N-type layer and N+ type impurity diffusion layer, the table top of silicon core side is rectangular, and described right angle table top is complete light
Sliding plane.
U-shaped etching right angle the most as claimed in claim 1 table top silicon diode silicon core, it is characterised in that described right angle table top is
Obtained by the corrosion of anisotropy preferential chemical.
3. the silicon diffusion wafer preparing silicon core described in claim 1, it is characterised in that be followed successively by P+ type from the bottom to top miscellaneous
Matter diffusion layer, original silicon single crystal N-type layer, N+ type impurity diffusion layer, nickel dam and anticorrosive glue-line, described nickel dam and anticorrosive
Offering groined type etching tank window on glue-line, groined type etching tank window is through to N+ type impurity diffusion layer upper surface.
4. the U-shaped etching right angle table top silicon diode that prepared by silicon core described in a claim 1, it is characterised in that described P+
Type impurity diffusion layer connects diode cathode, and N+ type impurity diffusion layer connects diode cathode.
5. the preparation method of a U-shaped etching right angle table top silicon diode, it is characterised in that its step is as follows:
1) front at (110) crystal face silicon single crystal flake of N-type diffuses into the boron semiconductor impurities of P+ type, and reverse side diffuses into N simultaneously
The phosphorus semiconductor impurities of+type, obtains P+N-N+ type silicon diffusion wafer;
2) obverse and reverse at P+N-N+ type silicon diffusion wafer plates nickel dam;
3) on the obverse and reverse nickel dam of P+N-N+ type silicon diffusion wafer, coat anticorrosive glue, sawing is passed through in N+ face
Anticorrosive glue-line and nickel dam, open the through groined type etching tank window to N+ type impurity diffusion layer upper surface;
4) use anisotropic silicon preferential etch liquid that N+ face groined type etching tank window is carried out supersonic vibration chemical attack reaction,
Above-mentioned corrosion reaction is only along longitudinally carrying out and be laterally automatically stopped, thus obtains U-shaped etching right angle table top P+N-N+ type silicon core;
5) U-shaped etching right angle table top P+N-N+ type silicon core is removed photoresist, sawing, weld, clean, mesa passivation and being compression molded into
Type, is packaged into silicon diode.
The preparation method of a kind of U-shaped etching right angle the most according to claim 5 table top silicon diode, it is characterised in that described
Step 1) in (110) crystal face silicon single crystal flake of N-type there is the witness marker line in (111) crystal orientation.
The preparation method of a kind of U-shaped etching right angle the most according to claim 5 table top silicon diode, it is characterised in that described
Step 3) in N+ face on open etching tank window in, groined type each bar limit is parallel or perpendicular to silicon single crystal flake respectively
(111) the witness marker line in crystal orientation.
The preparation method of a kind of U-shaped etching right angle the most according to claim 5 table top silicon diode, it is characterised in that described
Groined type etching tank window use automatic sawing, cutting to remove anticorrosive glue-line and the open method of nickel dam, selected saw blade
Edge width is 200um.
The preparation method of a kind of U-shaped etching right angle the most according to claim 5 table top silicon diode, it is characterised in that described
Step 4) in anisotropic silicon preferential etch liquid consisting of with mass ratio range: KOH:H2O=1:10, chemical attack is reacted
Temperature is 90~95 DEG C.
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