JP2004087955A - Manufacturing method of semiconductor device, and semiconductor device - Google Patents

Manufacturing method of semiconductor device, and semiconductor device Download PDF

Info

Publication number
JP2004087955A
JP2004087955A JP2002249156A JP2002249156A JP2004087955A JP 2004087955 A JP2004087955 A JP 2004087955A JP 2002249156 A JP2002249156 A JP 2002249156A JP 2002249156 A JP2002249156 A JP 2002249156A JP 2004087955 A JP2004087955 A JP 2004087955A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
semiconductor device
electrode
manufacturing
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002249156A
Other languages
Japanese (ja)
Other versions
JP4022113B2 (en
Inventor
Kazuhiko Ito
伊藤　一彦
Kyosuke Endo
遠藤　恭介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP2002249156A priority Critical patent/JP4022113B2/en
Publication of JP2004087955A publication Critical patent/JP2004087955A/en
Application granted granted Critical
Publication of JP4022113B2 publication Critical patent/JP4022113B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for manufacturing the semiconductor device having no deterioration of forward voltage (VF) characteristics and peak surge current (IFS) characteristics in a comparatively short process. <P>SOLUTION: The manufacturing method of the semiconductor device comprises a groove forming process for forming a groove 20 of a depth exceeding pn junction from one surface of a semiconductor base substance 10 with pn junction formed in parallel on a main face, a glass layer forming process for forming a glass layer 24 on the inner face of the groove 20, a semiconductor base substance grinding process for grinding one surface 32 of the semiconductor base substance with a plane grinding machine or a plane polishing machine, and an electrode forming process for forming an electrode 34 on at least one surface of the semiconductor base substance in this order. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明が属する技術分野】
本発明は、主面に平行なＰＮ接合が形成された半導体基体の一方の表面からＰＮ接合を超える深さの溝を形成し、その溝の内面にＰＮ接合を保護するためのパッシベーション用のガラス層を形成する半導体装置の製造方法に関する。また、本発明は、主面に平行なＰＮ接合が形成された半導体基体の表面に形成された凹部にパッシベーション用のガラス層が形成された半導体装置に関する。
【０００２】
【従来の技術】
ダイオード、トランジスタ、サイリスタ等の主面に平行なＰＮ接合が形成された半導体基体の一方の表面からＰＮ接合を超える深さの溝を形成し、その溝の内面にＰＮ接合を保護するためのパッシベーション用のガラス層を形成することは、従来より広く実施されている。
【０００３】
図２及び図３は、そのような従来の半導体装置（ダイオード）の製造方法を示す図である。この従来技術に係る半導体装置の製造方法は、図２及び図３に示されるように、以下の工程からなっている。
【０００４】
（ａ）半導体基体形成工程
Ｎ型シリコン基板１１０の一方の表面からのアクセプタ不純物の拡散によりＰ＋層１１２、他方の表面からのドナー不純物の拡散によりＮ＋層１１４を形成して、主面に平行なＰＮ接合が形成された半導体基体を形成する。この後、熱酸化によりＰ＋層１１２及びＮ＋層１１４の表面にシリコン酸化膜１１６，１１８を形成する。（図２（ａ）参照。）。
【０００５】
（ｂ）溝形成工程
次に、フォトエッチング法によって、シリコン酸化膜１１６の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基体のエッチングを行い、半導体基体の一方の表面からＰＮ接合を超える深さの溝１２０を形成する（図２（ｂ）参照。）。
【０００６】
（ｃ）ガラス層形成工程
次に、溝１２０の表面に、電気泳動法などにより、溝１２０の内面及びその近傍の半導体基体表面に、ガラス層１２４を形成する（図２（ｃ）参照。）。
【０００７】
（ｄ）フォトレジスト形成工程
次に、ガラス層１１２の表面を覆うようにフォトレジスト１２６を形成する（図２（ｄ）参照。）。
【０００８】
（ｅ）シリコン酸化膜除去工程
次に、フォトレジスト１２６をマスクとしてシリコン酸化膜１１６のエッチングを行い、Ｎｉめっき電極膜を形成する部位１３０におけるシリコン酸化膜１１６を除去する。（図３（ｅ）参照。）。
【０００９】
（ｆ）粗面化領域形成工程
次に、Ｎｉめっき電極膜を形成する部位１３０における半導体基体表面の粗面化処理を行い、Ｎｉめっき電極と半導体基体との密着性を高くするための粗面化領域１３２を形成する。（図３（ｆ）参照。）。
【００１０】
（ｇ）Ｎｉめっき電極形成工程
次に、半導体基体にＮｉめっきを行い、粗面化領域１３２上にＮｉめっき電極１３４を形成する。この工程では、半導体基体の他方の表面にもＮｉめっき電極１３６を形成する。（図３（ｇ）参照。）。
【００１１】
（ｈ）半導体基体切断工程
次に、ダイシング等により、ガラス層１２４の中央部において半導体基体を切断して半導体基体をチップ化して、ダイオードを作成する。（図３（ｈ）参照。）。従来の半導体装置の製造方法においては、以上のようにして半導体装置が製造されている。
【００１２】
しかしながら、上記の従来の半導体装置の製造方法においては、（ｃ）ガラス層形成工程でガラス層１２４を形成してから（ｇ）Ｎｉめっき電極形成工程でＮｉめっき電極１３４，１３６を形成するまでの間に、（ｄ）フォトレジスト形成工程でガラス層１２４を覆うようにフォトレジスト１２６を形成し、その後（ｅ）シリコン酸化膜除去工程でＮｉめっき電極膜を形成する部位１３０におけるシリコン酸化膜１１６を除去し、その後（ｆ）粗面化領域形成工程でＮｉめっき電極膜を形成する部位１３０に粗面化領域１３２を形成していたため（図２（ｃ）〜図３（ｇ）参照。）、プロセスが比較的長いという問題点があった。
【００１３】
また、上記の従来の半導体装置の製造方法においては、図３（ｈ）に示されるように、半導体基体の表面の一部（溝近傍）にシリコン酸化膜１１６ａが残存するため、Ｎｉめっき電極１３４の面積はＰＮ接合の面積よりも狭くなり、その結果、順電圧（ＶＦ）特性や尖頭サージ電流（ＩＦＳＭ）特性が劣化するという問題点があった。
【００１４】
【発明が解決しようとする課題】
そこで、本発明は上記のような問題を解決するためになされたもので、比較的短いプロセスで、順電圧（ＶＦ）特性や尖頭サージ電流（ＩＦＳ）特性の劣化のない半導体装置を製造することができる半導体装置の製造方法を提供することを目的とする。また、本発明は、順電圧（ＶＦ）特性や尖頭サージ電流（ＩＦＳ）特性の劣化のない半導体装置を提供することを目的とする。
【００１５】
【課題を解決するための手段】
（１）本発明の半導体装置の製造方法は、主面に平行なＰＮ接合が形成された半導体基体の一方の表面からＰＮ接合を超える深さの溝を形成する溝形成工程と、
この溝の内面にガラス層を形成するガラス層形成工程と、
平面研削機又は平面研磨機で、前記半導体基体の一方の表面を研削する半導体基体研削工程と、
前記半導体基体の少なくとも一方の表面に電極を形成する電極形成工程と、をこの順序で有することを特徴とする。
【００１６】
このため、本発明の半導体装置の製造方法によれば、ガラス層形成工程でガラス層を形成してから電極形成工程で電極を形成するまでの間に、従来のフォトレジスト形成工程、シリコン酸化膜除去工程及び粗面化領域形成工程の３工程を実施するのに代えて、半導体基体の一方の表面を研削する半導体基体研削工程を実施するだけで済むので、プロセスを比較的短くすることができるという効果がある。これは、本発明の半導体装置の製造方法においては、半導体基体研削工程がシリコン酸化膜の除去と半導体基体の表面粗面化を同時に行うとともに、シリコン酸化膜の除去の際にエッチング液を使わないのでフォトレジスト形成工程が不要になるためである。
【００１７】
また、本発明の半導体装置の製造方法によれば、溝近傍にシリコン酸化膜が残存することがなくなるため、電極の面積をＰＮ接合の面積に近いものとすることができるようになり、その結果、順電圧（ＶＦ）特性や尖頭サージ電流（ＩＦＳＭ）特性が劣化することがないという効果がある。
【００１８】
（２）上記（１）に記載の半導体装置の製造方法においては、前記半導体基体研削工程において前記半導体基体を研削する深さが０．５μｍ以上かつ３０μｍ以下であることが好ましい。
【００１９】
このように、半導体基体を研削する深さを０．５μｍ以上とすることにより、十分な粗面化効果が得られるようになり、半導体基体と電極との密着度を十分高いものとすることが可能となる。この観点からいえば、半導体基体を研削する深さが１μｍ以上であることがより好ましく、２μｍ以上とすることがさらに好ましい。
【００２０】
また、半導体基体を研削する深さを３０μｍ以下とすることにより、研削されたＰ＋層の表面における不純物濃度が電極とのコンタクトを取るために十分な値となり、半導体基体と電極とのコンタクト抵抗を十分低い値に保つことが可能となる。この観点からいえば、前記半導体基体を研削する深さが２０μｍ以下であることがより好ましく、１０μｍ以下であることがさらに好ましい。
【００２１】
（３）上記（１）又は（２）に記載の半導体装置の製造方法においては、前記半導体基体研削工程において２０００番よりも粗い研磨剤を用いて研削することが好ましい。
【００２２】
このように、２０００番よりも粗い研磨剤を用いて研削することにより、十分な粗面化効果が得られるようになり、半導体基体と電極との密着度を十分高いものとすることが可能となる。
【００２３】
（４）上記（１）乃至（３）のいずれかに記載の半導体装置の製造方法においては、はんだとの接着性の観点から、前記電極がめっき電極であることが好ましく、Ｎｉめっき電極であることがさらに好ましい。
【００２４】
（５）本発明の半導体装置は、主面に平行なＰＮ接合が形成された半導体基体と、
この半導体基体の一方の表面からＰＮ接合を超える深さまで形成された凹部の表面に形成されたパッシベーション用のガラス層と、
前記半導体基体の一方の表面に形成された電極とを有する半導体装置であって、
前記電極は前記半導体基体の一方の表面のうち前記凹部を除く全面に形成されてなることを特徴とする。
【００２５】
このため、本発明の半導体装置によれば、電極の面積をＰＮ接合の面積に近似させることができるので、順電圧（ＶＦ）特性や尖頭サージ電流（ＩＦＳＭ）特性の劣化がない。
【００２６】
（６）上記（５）に記載の半導体装置においては、前記半導体装置がダイオード、トランジスタ又はサイリスタである場合に顕著な効果が得られる。
【００２７】
【発明の実施の形態】
以下、図面を用いて、本発明の実施の形態を詳しく説明する。
【００２８】
図１は、実施の形態に係る半導体装置の製造方法の製造工程を示す図である。実施の形態に係る半導体装置の製造方法は、図１に示されるように、以下の工程によって製造される。なお、実施の形態に係る半導体装置は電流整流用のダイオードである。
【００２９】
（１）半導体基体形成工程
従来の半導体装置の製造方法と場合と同様に、Ｎ型シリコン基板１０の一方の表面からのアクセプタ不純物の拡散によりＰ＋層１２、他方の表面からのドナー不純物の拡散によりＮ＋層１４を形成して、主面に平行なＰＮ接合が形成された半導体基体を形成する。この後、熱酸化によりＰ＋層１２及びＮ＋層１４の表面にシリコン酸化膜１６，１８を形成する（図示せず。）。
【００３０】
（２）溝形成工程
次に、フォトエッチング法によって、シリコン酸化膜１６の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基体のエッチングを行い、半導体基体の一方の表面からＰＮ接合を超える深さの溝２０を形成する（図１（ａ）参照。）。
【００３１】
（３）ガラス層形成工程
次に、溝２０の表面に、電気泳動法などにより、溝２０の内面及びその近傍の半導体基体表面に、ガラス層２４を形成する（図１（ｂ）参照。）。
【００３２】
（４）半導体基体研削工程
次に、平面研削機又は平面研磨機で、半導体基体の一方の表面を研削して、シリコン酸化膜を除去するとともに、Ｎｉめっき電極と半導体基体との密着性を高くするための粗面化領域３２を形成する（図１（ｃ）参照。）。
【００３３】
（５）Ｎｉめっき電極形成工程
次に、従来の半導体装置の製造方法と同様に、半導体基体にＮｉめっきを行い、粗面化領域３２上にＮｉめっき電極３４を形成する。この工程では、半導体基体の他方の表面にもＮｉめっき電極３６を形成する（図１（ｄ）参照。）。
【００３４】
（６）半導体基体切断工程
次に、従来の半導体装置の製造方法と場合と同様に、ダイシング等により、ガラス層２４の中央部において半導体基体を切断して半導体基体をチップ化して、ダイオードを作成する（図示せず。）。実施の形態に係る半導体装置の製造方法においては、以上のようにして半導体装置を製造する。
【００３５】
実施の形態に係る半導体装置の製造方法によれば、（３）ガラス層形成工程でガラス層を形成してから（５）Ｎｉめっき電極形成工程でＮｉめっき電極を形成するまでの間に、従来のフォトレジスト形成工程、シリコン酸化膜除去工程及び粗面化領域形成工程の３工程を実施するのに代えて、（４）半導体基体の一方の表面を研削する半導体基体研削工程を実施するだけで済むので、プロセスを比較的短くすることができる。
【００３６】
また、実施の形態に係る半導体装置の製造方法によれば、従来の半導体装置の製造方法の場合のように溝近傍にシリコン酸化膜が残存してしまうことがなくなるため、電極の面積をＰＮ接合の面積に近いものとすることができるようになり、その結果、順電圧（ＶＦ）特性や尖頭サージ電流（ＩＦＳＭ）特性が劣化することがない。
【００３７】
実施の形態に係る半導体装置の製造方法においては、ＰＮ接合の深さを６０μｍとし、溝の深さを９０μｍとしている。また、上記（４）半導体基体研削工程において半導体基体を研削する深さを３μｍとしている。このため、十分な粗面化効果が得られ半導体基体と電極との密着度を十分高いものとすることが可能となっている。さらに、研削されたＰ＋層の表面における不純物濃度が電極とのコンタクトを取るために十分な値となりコンタクト抵抗を十分低い値に保つことが可能となっている。
【００３８】
実施の形態に係る半導体装置の製造方法においては、半導体基体研削工程において２０００番よりも粗い研磨剤を用いて研削している。このため、十分な粗面化効果が得られ、半導体基体と電極との密着度を十分高いものとすることが可能となっている。
【００３９】
上記した実施の形態に係る半導体装置の製造方法によって製造された半導体装置は、主面に平行なＰＮ接合が形成された半導体基体と、半導体基体の一方の表面からＰＮ接合を超える深さまで形成された凹部の表面に形成されたパッシベーション用のガラス層２４と、半導体基体の一方の表面に形成された電極３４とを有する半導体装置である。そして、この半導体装置においては、電極３４は半導体基体の一方の表面のうち前記凹部を除く全面に形成されている。
【００４０】
このため、この半導体装置によれば、電極の面積をＰＮ接合の面積に近似させることができるので、順電圧（ＶＦ）特性や尖頭サージ電流（ＩＦＳＭ）特性の劣化がない。
【００４１】
【発明の効果】
以上説明したように、本発明の半導体装置の製造方法によれば、ガラス層形成工程でガラス層を形成してから電極形成工程で電極を形成するまでの間に、従来のフォトレジスト形成工程、シリコン酸化膜除去工程及び粗面化領域形成工程の３工程を実施するのに代えて、半導体基体の一方の表面を研削する半導体基体研削工程を実施するだけで済むので、プロセスを比較的短くすることができるという効果がある。
【００４２】
また、本発明の半導体装置の製造方法によれば、溝近傍にシリコン酸化膜が残存することがなくなるため、電極の面積をＰＮ接合の面積に近いものとすることができるようになり、その結果、順電圧（ＶＦ）特性や尖頭サージ電流（ＩＦＳＭ）特性が劣化することがないという効果がある。
【００４３】
さらにまた、本発明の半導体装置によれば、電極の面積をＰＮ接合の面積に近似させることができるので、順電圧（ＶＦ）特性や尖頭サージ電流（ＩＦＳＭ）特性の劣化がないという効果がある。
【００４４】
なお、本発明の実施の形態においては、本発明の半導体装置の製造方法及び半導体装置を電流整流用のダイオードを用いて説明したが、本発明はこれに限られるものではなく、他のダイオード、トランジスタ又はサイリスタの場合であっても同様の効果が得られる。
【図面の簡単な説明】
【図１】実施の形態に係る半導体装置の製造工程図である。
【図２】従来の半導体装置の製造工程図である。
【図３】従来の半導体装置の製造工程図である。
【符号の説明】
１０　Ｎ型半導体基板
１２　Ｐ＋層
１４　Ｎ＋層
１６　シリコン酸化膜
２０　溝
２４　ガラス層
３２　粗面化領域
３４　Ｎｉめっき電極
３６　Ｎｉめっき電極
１１０　Ｎ型半導体基板
１１２　Ｐ＋層
１１４　Ｎ＋層
１１６、１１８　シリコン酸化膜
１１６ａ　溝の近傍のシリコン酸化膜
１２０　溝
１２４　ガラス層
１２６　フォトレジスト
１３０　Ｎｉめっき電極を形成する領域
１３２　粗面化領域
１３４　Ｎｉめっき電極
１３６　Ｎｉめっき電極[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides a passivation glass for forming a groove having a depth exceeding the PN junction from one surface of a semiconductor substrate having a PN junction formed parallel to the main surface, and protecting the PN junction on the inner surface of the groove. The present invention relates to a method for manufacturing a semiconductor device for forming a layer. Further, the present invention relates to a semiconductor device in which a glass layer for passivation is formed in a concave portion formed on a surface of a semiconductor substrate having a PN junction parallel to a main surface.
[0002]
[Prior art]
A groove having a depth exceeding the PN junction is formed from one surface of a semiconductor substrate on which a PN junction parallel to the main surface of a diode, transistor, thyristor, or the like is formed, and passivation for protecting the PN junction on the inner surface of the groove. Forming a glass layer for use has been widely practiced conventionally.
[0003]
2 and 3 are diagrams showing a method for manufacturing such a conventional semiconductor device (diode). The method of manufacturing a semiconductor device according to the conventional technique includes the following steps as shown in FIGS.
[0004]
(A) Semiconductor substrate forming step P + layer 112 is formed by diffusing an acceptor impurity from one surface of N-type silicon substrate 110, and N + layer 114 is formed by diffusing a donor impurity from the other surface. A semiconductor body having a parallel PN junction is formed. Thereafter, silicon oxide films 116 and 118 are formed on the surfaces of the P + layer 112 and the N + layer 114 by thermal oxidation. (See FIG. 2 (a).)
[0005]
(B) Groove forming step Next, a predetermined opening is formed in a predetermined portion of the silicon oxide film 116 by a photoetching method. After the etching of the oxide film, the semiconductor substrate is subsequently etched to form a groove 120 having a depth exceeding the PN junction from one surface of the semiconductor substrate (see FIG. 2B).
[0006]
(C) Glass Layer Forming Step Next, a glass layer 124 is formed on the surface of the groove 120 by electrophoresis or the like on the inner surface of the groove 120 and the surface of the semiconductor substrate near the groove 120 (see FIG. 2C). .
[0007]
(D) Photoresist formation step Next, a photoresist 126 is formed so as to cover the surface of the glass layer 112 (see FIG. 2D).
[0008]
(E) Silicon Oxide Film Removal Step Next, the silicon oxide film 116 is etched using the photoresist 126 as a mask to remove the silicon oxide film 116 at the portion 130 where the Ni plating electrode film is to be formed. (See FIG. 3 (e).)
[0009]
(F) Step of forming a roughened region Next, a roughening treatment is performed on the surface of the semiconductor substrate at the portion 130 where the Ni-plated electrode film is to be formed, so as to increase the adhesion between the Ni-plated electrode and the semiconductor substrate. Formation region 132 is formed. (See FIG. 3 (f).)
[0010]
(G) Ni-Plating Electrode Forming Step Next, Ni plating is performed on the semiconductor substrate to form a Ni-plating electrode 134 on the roughened region 132. In this step, the Ni plating electrode 136 is also formed on the other surface of the semiconductor substrate. (See FIG. 3 (g)).
[0011]
(H) Semiconductor Substrate Cutting Step Next, the semiconductor substrate is cut at the central portion of the glass layer 124 by dicing or the like, and the semiconductor substrate is formed into chips to produce diodes. (See FIG. 3 (h).) In the conventional method of manufacturing a semiconductor device, the semiconductor device is manufactured as described above.
[0012]
However, in the above-described conventional method for manufacturing a semiconductor device, the steps from (c) forming the glass layer 124 in the glass layer forming step to (g) forming the Ni plating electrodes 134 and 136 in the Ni plating electrode forming step are described. In the meantime, a photoresist 126 is formed so as to cover the glass layer 124 in the (d) photoresist formation step, and then the silicon oxide film 116 in the portion 130 where the Ni plating electrode film is to be formed in the (e) silicon oxide film removal step is formed. After that, the roughened region 132 was formed in the portion 130 where the Ni-plated electrode film is to be formed in the (f) roughened region forming step (see FIGS. 2C to 3G). There was a problem that the process was relatively long.
[0013]
Further, in the above-described conventional method for manufacturing a semiconductor device, as shown in FIG. 3H, since the silicon oxide film 116a remains on a part of the surface of the semiconductor substrate (in the vicinity of the groove), the Ni plating electrode 134 is formed. Is smaller than the area of the PN junction, and as a result, there is a problem that the forward voltage (VF) characteristics and the peak surge current (IFSM) characteristics are deteriorated.
[0014]
[Problems to be solved by the invention]
Accordingly, the present invention has been made to solve the above-described problem, and a semiconductor device without a deterioration in forward voltage (VF) characteristics and peak surge current (IFS) characteristics is manufactured by a relatively short process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be used. Another object of the present invention is to provide a semiconductor device that does not deteriorate forward voltage (VF) characteristics and peak surge current (IFS) characteristics.
[0015]
[Means for Solving the Problems]
(1) A method of manufacturing a semiconductor device according to the present invention includes a groove forming step of forming a groove having a depth exceeding the PN junction from one surface of a semiconductor substrate having a PN junction formed parallel to the main surface;
A glass layer forming step of forming a glass layer on the inner surface of the groove,
A semiconductor substrate grinding step of grinding one surface of the semiconductor substrate with a surface grinder or a plane polishing machine,
Forming an electrode on at least one surface of the semiconductor substrate in this order.
[0016]
Therefore, according to the method of manufacturing a semiconductor device of the present invention, a conventional photoresist forming step and a silicon oxide film are formed between the time when the glass layer is formed in the glass layer forming step and the time when the electrode is formed in the electrode forming step. Instead of performing the three steps of the removing step and the roughened region forming step, it is only necessary to perform the semiconductor substrate grinding step of grinding one surface of the semiconductor substrate, so that the process can be relatively shortened. This has the effect. This is because, in the method of manufacturing a semiconductor device according to the present invention, the semiconductor substrate grinding step simultaneously removes the silicon oxide film and roughens the surface of the semiconductor substrate, and does not use an etching solution when removing the silicon oxide film. Therefore, a photoresist forming step is not required.
[0017]
Further, according to the method for manufacturing a semiconductor device of the present invention, since the silicon oxide film does not remain near the trench, the area of the electrode can be made close to the area of the PN junction. This has the effect that the forward voltage (VF) characteristics and the peak surge current (IFSM) characteristics do not deteriorate.
[0018]
(2) In the method of manufacturing a semiconductor device according to the above (1), it is preferable that a depth at which the semiconductor substrate is ground in the semiconductor substrate grinding step is 0.5 μm or more and 30 μm or less.
[0019]
As described above, by setting the depth at which the semiconductor substrate is ground to 0.5 μm or more, a sufficient surface roughening effect can be obtained, and the degree of adhesion between the semiconductor substrate and the electrode can be sufficiently increased. It becomes possible. From this viewpoint, the depth at which the semiconductor substrate is ground is more preferably 1 μm or more, and further preferably 2 μm or more.
[0020]
Further, by setting the depth at which the semiconductor substrate is ground to 30 μm or less, the impurity concentration on the ground surface of the P + layer becomes a value sufficient to make contact with the electrode, and the contact resistance between the semiconductor substrate and the electrode is reduced. Can be maintained at a sufficiently low value. From this viewpoint, the grinding depth of the semiconductor substrate is more preferably 20 μm or less, and further preferably 10 μm or less.
[0021]
(3) In the method for manufacturing a semiconductor device according to the above (1) or (2), it is preferable that in the semiconductor substrate grinding step, grinding is performed using a polishing agent coarser than No. 2000.
[0022]
As described above, by grinding using a polishing agent coarser than No. 2000, a sufficient surface roughening effect can be obtained, and the degree of adhesion between the semiconductor substrate and the electrode can be made sufficiently high. Become.
[0023]
(4) In the method of manufacturing a semiconductor device according to any one of the above (1) to (3), the electrode is preferably a plated electrode, and is a Ni-plated electrode from the viewpoint of adhesiveness with solder. Is more preferable.
[0024]
(5) A semiconductor device according to the present invention includes: a semiconductor substrate having a PN junction parallel to the main surface;
A glass layer for passivation formed on the surface of the recess formed from one surface of the semiconductor substrate to a depth exceeding the PN junction;
A semiconductor device having an electrode formed on one surface of the semiconductor substrate,
The electrode is formed on one surface of the semiconductor substrate except the concave portion.
[0025]
Therefore, according to the semiconductor device of the present invention, the area of the electrode can be approximated to the area of the PN junction, so that the forward voltage (VF) characteristics and the peak surge current (IFSM) characteristics do not deteriorate.
[0026]
(6) In the semiconductor device described in (5), a remarkable effect is obtained when the semiconductor device is a diode, a transistor, or a thyristor.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0028]
FIG. 1 is a diagram showing a manufacturing process of a method for manufacturing a semiconductor device according to an embodiment. The method for manufacturing a semiconductor device according to the embodiment is manufactured by the following steps as shown in FIG. Note that the semiconductor device according to the embodiment is a diode for current rectification.
[0029]
(1) Step of Forming Semiconductor Substrate As in the case of the conventional semiconductor device manufacturing method, diffusion of acceptor impurities from one surface of N-type silicon substrate 10 causes diffusion of P + layer 12 and diffusion of donor impurities from the other surface. To form an N + layer 14 to form a semiconductor substrate in which a PN junction parallel to the main surface is formed. Thereafter, silicon oxide films 16 and 18 are formed on the surfaces of the P + layer 12 and the N + layer 14 by thermal oxidation (not shown).
[0030]
(2) Groove forming step Next, a predetermined opening is formed in a predetermined portion of the silicon oxide film 16 by a photoetching method. After the oxide film is etched, the semiconductor substrate is subsequently etched to form a groove 20 having a depth exceeding the PN junction from one surface of the semiconductor substrate (see FIG. 1A).
[0031]
(3) Step of Forming Glass Layer Next, a glass layer 24 is formed on the inner surface of the groove 20 and on the surface of the semiconductor substrate near the groove 20 by electrophoresis or the like (see FIG. 1B). .
[0032]
(4) Semiconductor Substrate Grinding Step Next, one surface of the semiconductor substrate is ground with a surface grinder or a plane polisher to remove the silicon oxide film and increase the adhesion between the Ni plating electrode and the semiconductor substrate. (See FIG. 1C).
[0033]
(5) Ni-Plating Electrode Forming Step Next, as in the conventional method for manufacturing a semiconductor device, Ni plating is performed on the semiconductor substrate to form a Ni-plating electrode 34 on the roughened region 32. In this step, a Ni-plated electrode 36 is also formed on the other surface of the semiconductor substrate (see FIG. 1D).
[0034]
(6) Semiconductor Substrate Cutting Step Next, as in the case of the conventional method of manufacturing a semiconductor device, the semiconductor substrate is cut at the center of the glass layer 24 by dicing or the like to make the semiconductor substrate into a chip, thereby forming a diode. (Not shown). In the method for manufacturing a semiconductor device according to the embodiment, the semiconductor device is manufactured as described above.
[0035]
According to the method of manufacturing a semiconductor device according to the embodiment, a conventional method is used between (3) forming a glass layer in a glass layer forming step and (5) forming a Ni plating electrode in a Ni plating electrode forming step. Instead of performing the three steps of the photoresist forming step, the silicon oxide film removing step, and the roughened region forming step, (4) merely performing the semiconductor substrate grinding step of grinding one surface of the semiconductor substrate The process can be relatively short.
[0036]
Further, according to the method of manufacturing a semiconductor device according to the embodiment, the silicon oxide film does not remain near the trench unlike the conventional method of manufacturing a semiconductor device. , And as a result, the forward voltage (VF) characteristics and the peak surge current (IFSM) characteristics do not deteriorate.
[0037]
In the method of manufacturing a semiconductor device according to the embodiment, the depth of the PN junction is 60 μm, and the depth of the groove is 90 μm. In the above (4) semiconductor substrate grinding step, the depth at which the semiconductor substrate is ground is 3 μm. Therefore, a sufficient surface roughening effect can be obtained, and the degree of adhesion between the semiconductor substrate and the electrode can be made sufficiently high. Further, the impurity concentration on the grounded P + layer surface has a sufficient value for making contact with the electrode, and the contact resistance can be kept at a sufficiently low value.
[0038]
In the method of manufacturing a semiconductor device according to the embodiment, in the semiconductor substrate grinding step, grinding is performed using an abrasive coarser than No. 2000. Therefore, a sufficient surface roughening effect can be obtained, and the degree of adhesion between the semiconductor substrate and the electrode can be made sufficiently high.
[0039]
The semiconductor device manufactured by the method of manufacturing a semiconductor device according to the above-described embodiment includes a semiconductor substrate having a PN junction formed parallel to the main surface, and a depth from one surface of the semiconductor substrate exceeding the PN junction. This is a semiconductor device having a glass layer 24 for passivation formed on the surface of the recessed portion and an electrode 34 formed on one surface of the semiconductor substrate. In this semiconductor device, the electrode 34 is formed on one surface of the semiconductor substrate except the concave portion.
[0040]
Therefore, according to this semiconductor device, the area of the electrode can be approximated to the area of the PN junction, so that the forward voltage (VF) characteristics and the peak surge current (IFSM) characteristics do not deteriorate.
[0041]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, a conventional photoresist forming step is performed after a glass layer is formed in a glass layer forming step and an electrode is formed in an electrode forming step. Instead of performing the three steps of the silicon oxide film removing step and the roughened area forming step, it is only necessary to perform the semiconductor substrate grinding step of grinding one surface of the semiconductor substrate, so that the process is relatively shortened. There is an effect that can be.
[0042]
Further, according to the method for manufacturing a semiconductor device of the present invention, since the silicon oxide film does not remain near the trench, the area of the electrode can be made close to the area of the PN junction. This has the effect that the forward voltage (VF) characteristics and the peak surge current (IFSM) characteristics do not deteriorate.
[0043]
Furthermore, according to the semiconductor device of the present invention, since the area of the electrode can be approximated to the area of the PN junction, there is an effect that the forward voltage (VF) characteristic and the peak surge current (IFSM) characteristic do not deteriorate. is there.
[0044]
In the embodiments of the present invention, the method of manufacturing a semiconductor device and the semiconductor device of the present invention have been described using a diode for current rectification. However, the present invention is not limited to this. Similar effects can be obtained even in the case of a transistor or a thyristor.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment.
FIG. 2 is a manufacturing process diagram of a conventional semiconductor device.
FIG. 3 is a manufacturing process diagram of a conventional semiconductor device.
[Explanation of symbols]
10 N-type semiconductor substrate 12 P + layer 14 N + layer 16 silicon oxide film 20 groove 24 glass layer 32 roughened area 34 Ni-plated electrode 36 Ni-plated electrode 110 N-type semiconductor substrate 112 P + layer 114 N + layer 116, 118 silicon oxide film 116a silicon oxide film 120 near the groove 120 groove 124 glass layer 126 photoresist 130 area for forming Ni-plated electrode 132 roughened area 134 Ni-plated electrode 136 Ni-plated electrode

Claims (6)

主面に平行なＰＮ接合が形成された半導体基体の一方の表面からＰＮ接合を超える深さの溝を形成する溝形成工程と、
この溝の内面にガラス層を形成するガラス層形成工程と、
平面研削機又は平面研磨機で、前記半導体基体の一方の表面を研削する半導体基体研削工程と、
前記半導体基体の少なくとも一方の表面に電極を形成する電極形成工程と、をこの順序で有することを特徴とする半導体装置の製造方法。A groove forming step of forming a groove having a depth exceeding the PN junction from one surface of the semiconductor substrate on which the PN junction parallel to the main surface is formed;
A glass layer forming step of forming a glass layer on the inner surface of the groove,
A semiconductor substrate grinding step of grinding one surface of the semiconductor substrate with a surface grinder or a plane polishing machine,
An electrode forming step of forming an electrode on at least one surface of the semiconductor substrate in this order. 請求項１に記載の半導体装置の製造方法において、前記半導体基体研削工程において前記半導体基体を研削する深さが０．５μｍ以上かつ３０μｍ以下であることを特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein a depth at which the semiconductor substrate is ground in the semiconductor substrate grinding step is 0.5 μm or more and 30 μm or less. 請求項１又は２に記載の半導体装置の製造方法において、前記半導体基体研削工程において２０００番よりも粗い研磨剤を用いて研削することを特徴とする半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein in the semiconductor substrate grinding step, grinding is performed using an abrasive that is coarser than No. 2000. 4. 請求項１乃至３のいずれかに記載の半導体装置の製造方法において、前記電極がめっき電極であることを特徴とする半導体装置の製造方法。4. The method for manufacturing a semiconductor device according to claim 1, wherein said electrode is a plated electrode. 主面に平行なＰＮ接合が形成された半導体基体と、
この半導体基体の一方の表面からＰＮ接合を超える深さまで形成された凹部の表面に形成されたパッシベーション用のガラス層と、
前記半導体基体の一方の表面に形成された電極とを有する半導体装置であって、
前記電極は前記半導体基体の一方の表面のうち前記凹部を除く全面に形成されてなることを特徴とする半導体装置。A semiconductor substrate on which a PN junction parallel to the main surface is formed;
A glass layer for passivation formed on the surface of the recess formed from one surface of the semiconductor substrate to a depth exceeding the PN junction;
A semiconductor device having an electrode formed on one surface of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the electrode is formed on one surface of the semiconductor substrate except for the concave portion. 請求項５に記載の半導体装置において、前記半導体装置はダイオード、トランジスタ又はサイリスタであることを有することを特徴とする半導体装置。6. The semiconductor device according to claim 5, wherein the semiconductor device is a diode, a transistor, or a thyristor.
JP2002249156A 2002-08-28 2002-08-28 Semiconductor device manufacturing method and semiconductor device Expired - Fee Related JP4022113B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002249156A JP4022113B2 (en) 2002-08-28 2002-08-28 Semiconductor device manufacturing method and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002249156A JP4022113B2 (en) 2002-08-28 2002-08-28 Semiconductor device manufacturing method and semiconductor device

Publications (2)

Publication Number Publication Date
JP2004087955A true JP2004087955A (en) 2004-03-18
JP4022113B2 JP4022113B2 (en) 2007-12-12

Family

ID=32056353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002249156A Expired - Fee Related JP4022113B2 (en) 2002-08-28 2002-08-28 Semiconductor device manufacturing method and semiconductor device

Country Status (1)

Country Link
JP (1) JP4022113B2 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101930919A (en) * 2009-06-23 2010-12-29 新电元工业株式会社 Semiconductor device and manufacture method thereof
CN102781861A (en) * 2011-05-26 2012-11-14 新电元工业株式会社 Glass composition for semiconductor junction protection, production method for semiconductor device, and semiconductor device
JP5139596B2 (en) * 2011-05-23 2013-02-06 新電元工業株式会社 Semiconductor junction protecting glass composition, semiconductor device manufacturing method, and semiconductor device
WO2013114562A1 (en) 2012-01-31 2013-08-08 新電元工業株式会社 Glass composition for semiconductor junction protection, production method for semiconductor device, and semiconductor device
WO2013114563A1 (en) * 2012-01-31 2013-08-08 新電元工業株式会社 Glass composition
JP5340511B1 (en) * 2012-05-08 2013-11-13 新電元工業株式会社 Semiconductor device manufacturing method and semiconductor device
WO2013168237A1 (en) 2012-05-08 2013-11-14 新電元工業株式会社 Glass composition for semiconductor junction protection, method for manufacturing semiconductor device, and semiconductor device
WO2013168236A1 (en) 2012-05-08 2013-11-14 新電元工業株式会社 Resin-sealed semiconductor device and production method for resin-sealed semiconductor device
CN103703548A (en) * 2012-05-08 2014-04-02 新电元工业株式会社 Glass composition for semiconductor junction protection, method for producing semiconductor device, and semiconductor device
CN103748667A (en) * 2011-08-29 2014-04-23 新电元工业株式会社 Glass composition for semiconductor junction protection, process for producing semiconductor device, and semiconductor device
WO2014155739A1 (en) 2013-03-29 2014-10-02 新電元工業株式会社 Glass composition for semiconductor junction protection, method for manufacturing semiconductor device, and semiconductor device
KR20160075562A (en) 2014-11-13 2016-06-29 신덴겐코교 가부시키가이샤 Manufacturing method of semiconductor device and glass coating film forming apparatus
CN106098791A (en) * 2016-06-16 2016-11-09 杭州赛晶电子有限公司 U-shaped etching right angle table top silicon diode and silicon core thereof and preparation method
CN107533976A (en) * 2014-10-31 2018-01-02 新电元工业株式会社 The manufacture method of semiconductor device and glass against corrosion

Cited By (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI421921B (en) * 2009-06-23 2014-01-01 Shindengen Electric Mfg Semiconductor apparatus and manufacturing method thereof
CN101930919A (en) * 2009-06-23 2010-12-29 新电元工业株式会社 Semiconductor device and manufacture method thereof
CN101930919B (en) * 2009-06-23 2013-01-02 新电元工业株式会社 Semiconductor device and manufacture method thereof
JP5139596B2 (en) * 2011-05-23 2013-02-06 新電元工業株式会社 Semiconductor junction protecting glass composition, semiconductor device manufacturing method, and semiconductor device
US9159549B2 (en) 2011-05-26 2015-10-13 Shindengen Electric Manufacturing Co., Ltd. Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device
US9941112B2 (en) * 2011-05-26 2018-04-10 Shindengen Electric Manufacturing Co., Ltd Method of manufacturing semiconductor device and semiconductor device
US20140312472A1 (en) * 2011-05-26 2014-10-23 Shindengen Electric Manufacturing Co., Ltd. Method of manufacturing semiconductor device and semiconductor device
WO2012160704A1 (en) 2011-05-26 2012-11-29 新電元工業株式会社 Glass composition for semiconductor junction protection, production method for semiconductor device, and semiconductor device
CN102781861A (en) * 2011-05-26 2012-11-14 新电元工业株式会社 Glass composition for semiconductor junction protection, production method for semiconductor device, and semiconductor device
CN103748667A (en) * 2011-08-29 2014-04-23 新电元工业株式会社 Glass composition for semiconductor junction protection, process for producing semiconductor device, and semiconductor device
US9006113B2 (en) 2011-08-29 2015-04-14 Shindengen Electric Manufacturing Co. Ltd. Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device
TWI466288B (en) * 2011-08-29 2014-12-21 Shindengen Electric Mfg Semiconductor composite material for semiconductor bonding, semiconductor device manufacturing method, and semiconductor device
WO2013114562A1 (en) 2012-01-31 2013-08-08 新電元工業株式会社 Glass composition for semiconductor junction protection, production method for semiconductor device, and semiconductor device
WO2013114563A1 (en) * 2012-01-31 2013-08-08 新電元工業株式会社 Glass composition
CN103403846A (en) * 2012-01-31 2013-11-20 新电元工业株式会社 Glass composition for semiconductor junction protection, production method for semiconductor device, and semiconductor device
US9099483B2 (en) 2012-01-31 2015-08-04 Shindengen Electric Manufacturing Co., Ltd. Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device
JPWO2013114563A1 (en) * 2012-01-31 2015-05-11 新電元工業株式会社 Glass composition
WO2013168236A1 (en) 2012-05-08 2013-11-14 新電元工業株式会社 Resin-sealed semiconductor device and production method for resin-sealed semiconductor device
JP5340511B1 (en) * 2012-05-08 2013-11-13 新電元工業株式会社 Semiconductor device manufacturing method and semiconductor device
CN103858213A (en) * 2012-05-08 2014-06-11 新电元工业株式会社 Glass composition for semiconductor junction protection, method for producing semiconductor device, and semiconductor device
CN103703548A (en) * 2012-05-08 2014-04-02 新电元工业株式会社 Glass composition for semiconductor junction protection, method for producing semiconductor device, and semiconductor device
CN103518254A (en) * 2012-05-08 2014-01-15 新电元工业株式会社 Semiconductor device production method and semiconductor device
WO2013168237A1 (en) 2012-05-08 2013-11-14 新電元工業株式会社 Glass composition for semiconductor junction protection, method for manufacturing semiconductor device, and semiconductor device
US9190365B2 (en) 2012-05-08 2015-11-17 Shindengen Electric Manufacturing Co., Ltd. Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device
DE112012003178B4 (en) 2012-05-08 2022-12-08 Shindengen Electric Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and semiconductor device
US9318401B2 (en) 2012-05-08 2016-04-19 Shindengen Electric Manufacturing Co., Ltd. Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device
US9698069B2 (en) 2012-05-08 2017-07-04 Shindengen Electric Manufacturing Co., Ltd. Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device
US9455231B2 (en) 2012-05-08 2016-09-27 Shindengen Electric Manufacturing Co., Ltd. Resin-sealed semiconductor device and method of manufacturing the same
US9570408B2 (en) 2012-05-08 2017-02-14 Shindengen Electric Manufacturing Co., Ltd. Resin-sealed semiconductor device and method of manufacturing resin-sealed semiconductor device
DE112013002368B4 (en) * 2012-05-08 2016-12-22 Shindengen Electric Manufacturing Co., Ltd. GLASS COMPOSITION FOR THE PROTECTION OF SEMICONDUCTOR TRANSFER
WO2014155739A1 (en) 2013-03-29 2014-10-02 新電元工業株式会社 Glass composition for semiconductor junction protection, method for manufacturing semiconductor device, and semiconductor device
US9236318B1 (en) 2013-03-29 2016-01-12 Shindengen Electric Manufacturing Co., Ltd. Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device
CN107533976A (en) * 2014-10-31 2018-01-02 新电元工业株式会社 The manufacture method of semiconductor device and glass against corrosion
US10186425B2 (en) 2014-10-31 2019-01-22 Shindengen Electric Manufacturing Co., Ltd. Method of manufacturing semiconductor device and resist glass
CN107533976B (en) * 2014-10-31 2020-12-22 新电元工业株式会社 Method for manufacturing semiconductor device and resist glass
KR20160075562A (en) 2014-11-13 2016-06-29 신덴겐코교 가부시키가이샤 Manufacturing method of semiconductor device and glass coating film forming apparatus
US9978882B2 (en) 2014-11-13 2018-05-22 Shindengen Electric Manufacturing Co., Ltd. Method of manufacturing semiconductor device and glass film forming apparatus
DE112014005031B4 (en) 2014-11-13 2019-04-25 Shindengen Electric Manufacturing Co., Ltd. Method for producing a semiconductor device and device for producing a glass layer
CN106098791A (en) * 2016-06-16 2016-11-09 杭州赛晶电子有限公司 U-shaped etching right angle table top silicon diode and silicon core thereof and preparation method

Also Published As

Publication number Publication date
JP4022113B2 (en) 2007-12-12

Similar Documents

Publication Publication Date Title
US6803294B2 (en) Semiconductor wafer and manufacturing method of semiconductor device
TWI411041B (en) Methods of processing semiconductor wafers having silicon carbide power devices thereon
JP4022113B2 (en) Semiconductor device manufacturing method and semiconductor device
JP5914060B2 (en) Method for manufacturing silicon carbide semiconductor device
JP2013511155A (en) Device with crackstop
JP6004561B2 (en) Method for manufacturing silicon carbide semiconductor element
JP2010118573A (en) Method for manufacturing semiconductor device
US20090291520A1 (en) Method for manufacturing semiconductor apparatus
US9824927B2 (en) Methods for producing semiconductor devices
JP2010016188A (en) Method of manufacturing semiconductor device, and semiconductor device
JP2014229843A (en) Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
JP2010103310A (en) Method of manufacturing semiconductor device
JPH08130197A (en) Manufacture of semiconductor device
JP3208319B2 (en) Method for manufacturing semiconductor device
JP2003338620A (en) Semiconductor device and manufacturing method therefor
JP6028325B2 (en) Manufacturing method of semiconductor device
JP7135352B2 (en) Semiconductor device manufacturing method
JP3860080B2 (en) Semiconductor device and manufacturing method thereof
JP2011054914A (en) Manufacturing method of semiconductor device and semiconductor wafer
JPS6246534A (en) Manufacture of glass coated semiconductor chip
JPH05291186A (en) Formation of metal contact on surface of semiconductor chip
JP2005026428A (en) Method for manufacturing semiconductor device
JP2004119498A (en) Method for manufacturing semiconductor device
JP4724729B2 (en) Manufacturing method of semiconductor device
JPH0212920A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041101

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070201

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070227

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070423

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070529

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070729

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070911

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070928

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101005

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4022113

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111005

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121005

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121005

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131005

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees