JP2021082689A - Silicon carbide semiconductor device, and method for manufacturing the same - Google Patents

Abstract

To provide a silicon carbide semiconductor device which can prevent the decrease in the channel mobility, and the worsening of the reliability of a gate insulative film, and a method for manufacturing such a silicon carbide semiconductor device.SOLUTION: A method for manufacturing a silicon carbide semiconductor device comprises the step of removing, by etching, a dopant precipitation layer produced on a trench inner wall during a thermal treatment or an excessive carbon precipitation layer produced on a trench inner wall by sacrificial oxidation before deposition of a gate insulative film and after the thermal treatment for rounding a trench corner portion. The etching is a low-damage etching by use of plasma of an etching gas containing no carbon nor oxygen. The low-damage etching step does not cause the re-formation of the excessive carbon precipitation layer on a trench side wall nor the re-deposition of a CF-based polymer thereon. In addition, thanks to the low-damage etching, the height of a protrusion formed on the trench side wall during trench etching is made 3 nm or smaller, and the trench side wall becomes a flat face. Thus, roughness scattering by the trench side wall can be decreased.SELECTED DRAWING: Figure 2

Description

The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Conventionally, a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a trench gate structure using silicon carbide (SiC) as a semiconductor material: a MOS type field effect transistor having an insulating gate having a three-layer structure of metal-oxide film-semiconductor. In), a damage layer, a surplus carbon (C) precipitation layer, a dopant precipitation layer, and the like are formed on the inner wall of the trench by various treatments performed at the time of forming the trench or before the formation of the gate insulating film after the formation of the trench. It is known.

For example, in a semiconductor substrate made of silicon carbide, a trench is formed by anisotropic etching with high-density plasma, and a damage layer is formed on the inner wall of the trench due to collision of ions and radicals generated from the plasma. When sacrificing oxidation of the inner wall of the trench to remove the damaged layer of the inner wall of the trench, the surface region (carbonization) of the inner wall of the trench is formed by _{sacrificing the inner wall of the trench to form a silicon oxide (SiO 2) film.} Excess carbon is desorbed from the silicon portion) and deposited on the inner wall of the trench to form an excess carbon precipitation layer.

When high temperature annealing (heat treatment) is performed to round the corners (corners) of the trench, the dopant is redisposited on the inner wall surface of the trench to form a precipitation layer of the dopant having a high impurity concentration. The damaged layer, excess carbon precipitation layer, and dopant precipitation layer on the inner wall of the trench are chemically dry-etched (CDE) using a gas containing _{carbon tetrafluoride (CF 4} ) and oxygen (O _{2) on the inner wall of the trench.} It is removed by Dry Etching) or plasma etching (PE: Plasma Etching).

A method for manufacturing a conventional silicon carbide semiconductor device will be described by taking MOSFET as an example. FIG. 7 is a flowchart showing an outline of a conventional method for manufacturing a silicon carbide semiconductor device. In forming the MOS gate of the conventional silicon carbide semiconductor device, first, a trench reaching a predetermined depth from the front surface of the semiconductor substrate is formed by photolithography and etching (hereinafter referred to as trench etching) (step S101). ). This trench etching is, for example, anisotropic etching using a high-density plasma.

^{The semiconductor substrate is formed by sequentially laminating each epitaxial layer serving as an n-} type drift region and a p-type base region on the front surface of ^{an n +} type starting substrate using silicon carbide as a semiconductor material. The main surface of the semiconductor substrate on the p-type epitaxial layer side, which is the p-type base region, is the front surface, and the main surface on the n ⁺ type departure substrate side is the back surface. ^{In the process of step S101, the trench penetrates the n +} type source region and the p-type base region formed in the p-type epitaxial layer from the front surface of the semiconductor substrate ^{and reaches the n-} type drift region.

A damage layer due to trench etching is formed on the inner wall of the trench. Further, in trench etching, ^{the etching rates near the first boundary between the n-} type drift region and the p-type base region and near ^{the second boundary between the p-type base region and the n +} type source region are the second in the epitaxial layer. 1, It is slower than the etching rate of the part between the second boundaries. The slow etching rate portion of the epitaxial layer remains as protrusions on the side walls of the trench. Therefore, a step is formed on the side wall of the trench 7 due to the protrusion.

Next, the corners of the trench are rounded by plasma etching or high temperature (for example, 1500 ° C. or higher) annealing (step S102). By the process of step S102, etching of the inner wall of the trench and surface diffusion of silicon (Si) and carbon (C) of the inner wall of the trench occur at the same time, and the corner portion of the trench is rounded. Further, when the treatment of step S102 is performed by high temperature annealing, a precipitation layer of a dopant having a high impurity concentration is formed on the inner wall of the trench as described above.

Next, the inner wall of the trench is sacrificed to oxidize to form a sacrificial oxide film (step S103), and the sacrificial oxide film is removed to remove the damaged layer and the precipitate layer of the dopant generated on the inner wall of the trench. Due to the sacrificial oxidation in step S103, an excess carbon precipitation layer is formed on the inner wall of the trench as described above. The process of step S103 can be omitted. Next, the inner wall of the trench is chemically dry-etched or plasma-etched using a gas containing _{CF 4} and O _{2 (step S104).}

The treatment in step S104 removes the excess carbon precipitation layer on the inner wall of the trench. When the process of step S103 is omitted, the process of step S104 removes the damaged layer on the inner wall of the trench and the precipitation layer of the dopant. Next, after depositing a gate insulating film along the inner wall of the trench (step S105), a gate electrode is formed inside the trench (step S106). Then, the conventional silicon carbide semiconductor device is completed by forming each part other than the MOS gate (not shown) at a predetermined timing by a general method.

As a conventional method for manufacturing a silicon carbide semiconductor device, after the trench is formed, the inner wall of the trench is not sacrificed to be oxidized, or the damaged layer on the inner wall of the trench is _{subjected to chemical dry etching using a gas containing CF 4} and O _2. A method of depositing a gate insulating film after removing the above-mentioned material has been proposed (see, for example, Patent Document 1 below). In Patent Document 1 below, by not sacrificing oxidation of the inner wall of the trench, it is possible to prevent the inner wall of the trench from being rapidly oxidized in the exposed portion of the ^{n + type source region having a higher impurity concentration than the p-type base region.} There is.

Japanese Patent No. 6299102

However, in _{etching using a gas containing CF 4} and O ₂ , the inner wall of the trench is thinly oxidized to re-form an excess carbon precipitation layer on the inner wall of the trench, or a carbon-based polymer containing fluorine is generated. It causes new problems such as being adhered to the inner wall of the trench. The excess carbon precipitation layer formed on the inner wall of the trench causes a decrease in channel mobility and an increase in on-resistance. The fluorine-containing carbon-based polymer formed on the inner wall of the trench causes a decrease in the reliability of the gate insulating film.

The present invention solves the above-mentioned problems caused by the prior art, and thus can prevent a decrease in channel mobility and a decrease in reliability of the gate insulating film. Silicon carbide semiconductor device and silicon carbide An object of the present invention is to provide a method for manufacturing a semiconductor device.

In order to solve the above-mentioned problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. A first conductive type first semiconductor region is provided inside a semiconductor substrate made of silicon carbide. A second conductive type second semiconductor region is provided between the first main surface of the semiconductor substrate and the first semiconductor region. A first conductive type third semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region.

The trench penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region. The gate insulating film is provided along the inner wall of the trench. The gate electrode is provided on the gate insulating film inside the trench. The first electrode is electrically connected to the third semiconductor region and the second semiconductor region. The second electrode is provided on the second main surface of the semiconductor substrate. The protrusion height is 3 nm or less at the interface of different conductive type regions on the side wall of the trench.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. A first step is performed on the first conductive type starting substrate made of silicon carbide to form a first conductive type silicon carbide layer which is a first conductive type first semiconductor region having a lower impurity concentration than the starting substrate. .. The second step of forming the second conductive type silicon carbide layer to be the second conductive type second semiconductor region is performed on the first conductive type silicon carbide layer. The third step of selectively forming the first conductive type third semiconductor region on the surface region of the second conductive type silicon carbide layer is performed. The fourth step of forming a trench that penetrates the third semiconductor region and the second conductive silicon carbide layer and reaches the first conductive silicon carbide layer by the first etching is performed.

The fifth step of rounding the corner portion of the trench by heat treatment is performed. After the fifth step, a sixth step of second etching the inner wall of the trench in a plasma atmosphere is performed. After the sixth step, a seventh step of depositing a gate insulating film along the inner wall of the trench is performed. The eighth step of forming the gate electrode on the gate insulating film inside the trench is performed. The etching gas of the second etching does not contain a first element that attaches carbon-containing deposits to the inner wall of the trench and a second element that oxidizes the inner wall of the trench.

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the first element is carbon.

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second element is oxygen.

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the etching gas for the second etching is nitrogen trifluoride gas.

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the etching gas for the second etching is chlorine trifluoride gas.

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the second etching is chemical dry etching.

Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the etching amount of the second etching is 100 nm or less in the direction orthogonal to the side wall of the trench from the side wall of the trench. It is characterized by that.

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is the above-described invention, in the sixth step, in the first etching of the fourth step, the first conductive type silicon carbide on the side wall of the trench. Due to the difference in etching rate between the boundary between the layer and the second conductive silicon carbide layer, the boundary between the second conductive silicon carbide layer and the third semiconductor region, and the surface between the boundaries. The height of the protrusions formed at each of the boundaries is lowered by the second etching to be 3 nm or less.

According to the invention described above, since the etching gas used for the second etching does not contain the second element that oxidizes the inner wall of the trench, the inner wall of the trench is not oxidized at the time of the second etching, so that the inner wall of the trench is formed. The excess carbon precipitation layer is not reformed. Since the etching gas used for the second etching does not contain the first element that attaches carbon-containing deposits to the inner wall of the trench, the carbon-based polymer containing fluorine does not adhere to the inner wall of the trench during the second etching. ..

According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention, it is possible to prevent a decrease in channel mobility and a decrease in reliability of the gate insulating film. Play.

It is sectional drawing which shows an example of the structure of the silicon carbide semiconductor device which concerns on embodiment. It is a flowchart which shows the outline of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment. It is a perspective view which shows typically the result of having detected the surface shape of the part surrounded by the frame A of FIG. 3 by AFM. It is sectional drawing which shows the part of the side wall of the trench of FIG. 4 enlarged. It is sectional drawing which shows typically the surface shape of the side wall of the trench immediately after the processing of step S4 of FIG. It is a flowchart which shows the outline of the manufacturing method of the conventional silicon carbide semiconductor device.

Hereinafter, preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than the layers and regions to which they are not attached, respectively. In the following description of the embodiment and the attached drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment)
The structure of the silicon carbide semiconductor device according to the embodiment will be described by taking MOSFET as an example. FIG. 1 is a cross-sectional view showing an example of the structure of the silicon carbide semiconductor device according to the embodiment. The silicon carbide semiconductor device 10 according to the embodiment shown in FIG. 1 is provided with a general trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 30 using silicon carbide (SiC) as a semiconductor material. It is a vertical MOSFET.

The semiconductor substrate 30 has an n-type buffer region 2, an n ^- type drift region (first semiconductor region) 3, and a p-type base region ^{on the front surface of an n +} type starting substrate 31 using silicon carbide as a semiconductor material. Each epitaxial layer 32 to 34 (second semiconductor region) 4 is laminated in order. The main surface of the semiconductor substrate 30 on the p-type epitaxial layer 34 side is the front surface, and the main surface of the n ⁺ type departure substrate 31 side ( ^{the back surface of the n +} type departure substrate 31) is the back surface. The n ⁺ type starting board 31 is an n ⁺ type drain region 1.

The n-type epitaxial layer 32 is an n-type buffer region 2. The n-type buffer area 2 may not be provided. The n ^- type drift region 3 is an n ^- type epitaxial layer 33 (first conductive type silicon carbide layer), and is n when the n-type buffer region 2 (n-type buffer region 2 is not provided) in the depth direction Z. ^{It touches the +} type drain region 1). The p-type base region 4 is provided between the front surface of the semiconductor substrate 30 and the n ^- type drift region 3 in contact with the n ^- type drift region 3.

Between the front surface of the semiconductor substrate 30 and the p-type base region 4, the n ⁺ type source region (third semiconductor region) 5 and the p ⁺ type contact region 6 are selected in contact with the p-type base region 4, respectively. It is provided as a target. The n ⁺ type source region 5 and the p ⁺ type contact region 6 are exposed on the front surface of the semiconductor substrate 30. The portion of the p-type epitaxial layer (second conductive type silicon carbide layer) 34 ^{excluding the n +} type source region 5 and the p ⁺ type contact region 6 is the p-type base region 4.

A channel (n-type inversion layer) 4a is formed in a portion of the p-type base region 4 ^{sandwiched between the n +} type source region 5 and the n ^{-type drift region 3 when the MOSFET is on.} without providing the p ⁺ -type contact region 6, p-type base region 4 may be exposed on the front surface of the semiconductor substrate 30. ^{The trench 7 penetrates the n +} type source region 5 and the p-type base region 4 in the depth direction Z from the front surface of the semiconductor substrate 30 ^{and reaches the n-} type drift region 3.

The trench 7 extends linearly in the first direction X parallel to the front surface of the semiconductor substrate 30, for example. The corners (corners) of the trench 7 are rounded. Since the corner portion of the trench 7 is rounded, the electric field applied to the gate insulating film 8 at the corner portion of the trench 7 can be relaxed, so that the gate withstand voltage can be ensured. The corner portion of the trench 7 is a boundary between the side wall and the bottom surface of the trench 7.

At the side wall of the trench 7, ^{the first boundary 41 between the n-} type drift region 3 and the p-type base region 4 and the second boundary 42 between the p-type base region 4 and the n ⁺ type source region 5 are terminated. There is. The end portions of the first, second, and first boundaries 41 and 42 are exposed on the side wall of the trench 7. No step is formed on the side wall of the trench 7 at the end portions of the first and second boundaries 41 and 42, and the side wall of the trench 7 is a substantially flat surface over the entire surface of the side wall of the trench 7.

The fact that there is no step on the side wall of the trench 7 means that the heights of the protrusions 41a and 42a (see FIG. 3 to be described later) formed at the end portions of the first, second boundaries 41 and 42 on the side wall of the trench 7 are 3 nm or less. It means that it is a degree. The height of the protrusions 41a and 42a on the side wall of the trench 7 is the distance d from the apex of the protrusions 41a and 42a on the side wall of the trench 7 to the portion of the side wall surface of the trench 7 excluding the protrusions 41a and 42a (see FIG. 3). Is.

The protrusions 41a and 42a on the side wall of the trench 7 project into the inside of the trench 7 in the second direction Y orthogonal to the side wall of the trench 7, and extend in the first direction X along the side wall of the trench 7. The protrusions 41a and 42a on the side walls of the trench 7 have the most protruding points (vertices) on the end portions of the first and second boundaries 41 and 42, respectively, and are directed from the vertices toward both main surfaces of the semiconductor substrate 30. It has a substantially triangular cross-sectional shape that becomes lower as it increases.

A gate insulating film 8 is provided along the inner wall of the trench 7. The gate insulating film 8 is a deposited oxide film such as a high temperature oxidation (HTO: High Temperature Oxide) film. A gate electrode 9 is provided on the gate insulating film 8 inside the trench 7 so as to embed the inside of the trench 7. The MOS gate is composed of the trench 7, the gate insulating film 8, and the gate electrode 9.

The interlayer insulating film 11 is provided on the front surface of the semiconductor substrate 30 and covers the gate electrode 9. The source electrode 12 is provided on the interlayer insulating film 11 so as to be embedded in the contact hole of the interlayer insulating film 11. ^{The source electrode 12 makes ohmic contact with the n +} type source region 5 and the p ⁺ type contact region 6 through the contact hole, and electrically contacts the p type base region 4, the n ⁺ type source region 5 and the p ⁺ type contact region 6. Is connected.

If p ⁺ -type contact region 6 is not provided, the source electrode 12 is in ohmic contact with the p-type base region 4 in place of the p ⁺ -type contact region 6. The drain electrode 13 is provided on the entire back surface of the semiconductor substrate 30 (the back surface of the n ^{+ type starting substrate 31).} The drain electrode 13 is in contact with the n ⁺ type drain region 1 (n ⁺ type starting substrate 31) and is ^{electrically connected to the n +} type drain region 1.

Next, the manufacturing method of the silicon carbide semiconductor device 10 according to the embodiment will be described with reference to FIGS. 1 to 6. FIG. 2 is a flowchart showing an outline of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. FIG. 2 shows only the process of forming the MOS gate. FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 3 shows a cross-sectional structure in which the trench 7 immediately after the processing in step S4 of FIG. 2 is cut along a cutting line parallel to the second direction Y.

FIG. 4 is a perspective view schematically showing the result of detecting the surface shape of the portion (side wall of the trench 7) surrounded by the frame A of FIG. 3 with an atomic force microscope (AFM: Atomic Force Microscope). FIG. 4 schematically shows the surface shape of the side wall of the trench immediately after the treatment of step S1 of FIG. FIG. 5 is a plan view showing a part of the side wall of the trench of FIG. FIG. 6 is a plan view schematically showing the surface shape of the side wall of the trench immediately after the processing of step S4 of FIG.

5 and 6 show the side wall of the trench 7 as viewed from the second direction Y, and show the same location (near the protrusions 41a and 42a) of the side wall of the trench 7. Regarding the graph axes (3 axes) in FIG. 4, the distances x and y are the distances on the parallel lines in the first and second directions X and Y, respectively, and the depth z is the distance (depth) on the parallel lines in the depth direction Z. Is. With respect to the graph axes (2 axes) of FIGS. 5 and 6, the distances x and y are distances on parallel lines in the first and second directions X and Y, respectively. FIGS. 4 to 6 show the height difference in the second direction Y by hatching.

^{First, an n +} type starting substrate 31 serving ^{as an n +} type drain region 1 using silicon carbide as a semiconductor material is prepared. Next, each epitaxial layer 32 to 34 serving as an n-type buffer region 2, an n ^- type drift region 3 and a p-type base region 4 is epitaxially grown ^{on the front surface of the n + type starting substrate 31 to form a semiconductor substrate.} (Semiconductor wafer) 30 is manufactured. The thickness of the n-type epitaxial layer 32 may be, for example, about 1 μm.

^{Next, the n +} type source region 5 and the p ⁺ type contact region 6 are selectively formed in the surface region of the p-type epitaxial layer 34 by ion implantation. Next, a heat treatment is performed to activate the impurities introduced by ion implantation. This heat treatment may be performed once after the formation of all the diffusion regions (n ⁺ type source region 5 and p ⁺ type contact region 6) formed by ion implantation, or each time the diffusion region is formed by ion implantation. You may go to.

Next, by photolithography and etching (trench etching), a trench 7 is formed from the front surface of the semiconductor substrate 30 through the n ⁺ type source region 5 and the p-type base region 4 to ^{reach the n-type drift region 3.} (Step S1: Fourth step). The trench etching is, for example, anisotropic etching using a high-density plasma. A damage layer (not shown) due to trench etching is formed on the inner wall of the trench 7.

In this trench etching, a step is formed on the side wall of the trench 7 by the protrusions 41a'and 42a' (FIGS. 4 and 5). Since the etching rate near the first and second boundaries 41 and 42 of the epitaxial layers 33 and 34 is slower than the etching rate of the portion between the first and second boundaries 41 and 42 of the epitaxial layers 33 and 34, the epitaxial layers 33 and 34 It is presumed that the portion having a slow etching rate remains on the side wall of the trench 7 as protrusions 41a'and 42a'.

Next, the corner portion of the trench 7 is rounded by plasma etching or high temperature annealing of, for example, 1500 ° C. or higher (step S2: fifth step). By the process of step S2, etching of the inner wall of the trench 7 and surface diffusion of silicon (Si) and carbon (C) of the inner wall of the trench 7 occur at the same time, and the corner portion of the trench 7 is rounded. When the treatment of step S2 is performed by high temperature annealing, a precipitation layer (not shown) of a dopant having a high impurity concentration is formed on the inner wall of the trench 7.

Next, after sacrificial oxidation of the inner wall of the trench 7 (step S3), the sacrificial oxide film is removed to remove the damaged layer and the precipitate layer of the dopant generated on the inner wall of the trench 7. Due to the sacrificial oxidation in step S3, an excess carbon precipitation layer (not shown) is formed on the inner wall of the trench 7. The process of step S3 can be omitted. Next, using an etching gas that does not contain the first element that attaches deposits that cause deterioration of characteristics to the inner wall of the trench 7 and does not contain the second element that oxidizes the inner wall of the trench 7, the inner wall of the trench 7 is used. Etching (step S4: 6th step)

The first element is, for example, carbon (C) that produces a carbon-based polymer containing fluorine (for example, CF-based polymer). The second element is, for example, oxygen (O) that combines with silicon (Si) in the silicon carbide portion of the inner wall of the trench 7 to generate excess carbon (C). The etching gas used in the treatment of step S4 may be a gas containing a halogen element such as fluorine (F) or chlorine (Cl) that causes an etching reaction, and does not contain any of the first and second elements. For example, nitrogen trifluoride (NF ₃ ) gas or chlorine trifluoride (ClF ₃ ) gas can be used.

The treatment in step S4 may be isotropic low-damage dry etching by radicals (hereinafter referred to as low-damage etching) such as chemical dry etching or plasma etching. For example, low damage etching can be achieved by performing plasma etching using radicals generated from plasma generated in the chamber. Alternatively, chemical dry etching using radicals generated from plasma generated at another location and transported into the chamber results in lower damage etching.

By performing the process of step S4 under the above conditions, the inner wall of the trench 7 can be etched without using oxygen, so that the SiC surface (etched surface) is not oxidized. The etched surface is the front surface of the semiconductor substrate 30 and the inner wall surface of the trench 7. Further, when the etching gas used for the treatment in step S4 contains fluorine atoms, the fluorine atoms have a small binding energy and are easily decomposed into radicals with low power, so that low damage etching is possible.

Further, since all the reaction products generated in the processing furnace (chamber) of the etching apparatus during the processing in step S4 become gas and are exhausted from the processing furnace to the outside, the reaction products generated during the processing in step S4 are used. There is little surface roughness on the SiC surface. Fluorine atoms contained in the etching gas adhere to the SiC surface, but the fluorine adhering to the SiC surface is removed by a cleaning treatment (not shown) performed between the treatments of steps S1 to S6, so that the treatment in step S4 Fluorine may be contained in the etching gas used.

By the treatment of step S4, the excess carbon precipitation layer on the inner wall of the trench 7 is removed. When the process of step S3 is omitted, the process of step S4 removes the damage layer and the precipitate layer of the dopant generated on the inner wall of the trench 7 in the processes of steps S1 and S2. Since the etching gas containing no first and second elements is used in the process of step S4, the inner wall of the trench 7 is oxidized to reshape the excess carbon precipitation layer, or the trench is formed, as in the conventional method (FIG. 7). Problems such as adhesion of a carbon-based polymer containing fluorine to the inner wall do not occur.

Further, by the process of step S4, the height (distance d) of the protrusions 41a'and 42a' (see FIGS. 4 and 5) generated on the side wall of the trench 7 becomes 3 nm or less. Therefore, there is no step on the side wall of the trench 7 due to the protrusions 41a and 42a, and the side wall of the trench 7 becomes a substantially flat surface over the entire surface of the side wall of the trench 7 (see FIG. 6). In FIGS. 1, 3 and 6, the protrusions on the side wall of the trench 7 after the treatment in step S4 are indicated by reference numerals 41a and 42a. The etching amount (thickness in the second direction Y from the side wall) of the side wall of the trench 7 by the process of step S4 is 100 nm or less.

Next, for example, an HTO film is deposited as the gate insulating film 8 along the front surface of the semiconductor substrate 30 and the inner wall of the trench 7 (step S5: 7th step). Next, for example, polysilicon (poly-Si) is embedded in the trench 7 to form the gate electrode 9 (step S6: 8th step). The MOS gate is composed of the trench 7, the gate insulating film 8 and the gate electrode 9 formed by the treatments of steps S1 to S6. Then, the silicon carbide semiconductor device 10 of FIG. 1 is completed by forming each part other than the MOS gate (not shown) at a predetermined timing by a general method.

As described above, according to the embodiment, after the heat treatment for rounding the corners of the trench, before depositing the gate insulating film along the side wall of the trench, the dopant generated on the inner wall of the trench by the heat treatment. The precipitation layer of the above, or when sacrificial oxidation is performed after the heat treatment, the excess carbon precipitation layer generated on the inner wall of the trench due to the sacrificial oxidation is removed by etching the inner wall of the trench. This etching is dry etching in a plasma atmosphere using an etching gas that does not contain a first element that attaches carbon-containing deposits to the inner wall of the trench and a second element that oxidizes the inner wall of the trench. Therefore, low damage etching is possible on the inner wall of the trench.

Further, according to the embodiment, the etching gas used for etching for removing the dopant precipitation layer or the excess carbon precipitation layer on the inner wall of the trench does not contain the second element that oxidizes the inner wall of the trench. Since the inner wall of the trench is not oxidized during the etching, the excess carbon precipitation layer is not reformed on the inner wall of the trench. Therefore, it is possible to suppress a decrease in channel mobility. In addition to this, the etching gas of the etching does not contain the first element that attaches carbon-containing deposits to the inner wall of the trench, so that the carbon-based polymer containing fluorine on the inner wall of the trench at the time of the etching ( Polymer) does not adhere. Therefore, it is possible to suppress a decrease in reliability of the gate insulating film.

Further, according to the embodiment, at the side wall of the trench during trench etching ^{, the first boundary between the n-} type drift region and the p-type base region and the second boundary between the p-type base region and the n ⁺ type source region are formed. The height of each of the generated protrusions can be lowered by etching to remove the dopant precipitation layer or the excess carbon precipitation layer on the inner wall of the trench. As a result, the side wall of the trench can be made a substantially flat surface by eliminating the step due to the protrusion. The step due to the protrusion is 3 nm or less. _{Since there is no step on the side wall of the trench, the interfacial roughness scattering at the interface (SiO 2} / SiC interface) between the gate insulating film and the silicon carbide portion of the inner wall of the trench can be reduced, so that the channel mobility can be reduced. The decrease can be suppressed.

As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention may be provided with a trench gate structure, and is not limited to MOSFETs, but other devices such as IGBTs (Insulated Gate Bipolar Transistors) in which a p-type collector layer is formed on the back surface of a semiconductor substrate. It can also be applied to MOS type semiconductor devices.

As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for the trench gate type semiconductor device, and are particularly suitable for the trench gate type MOSFET.

1 n ⁺ type drain area 2 n type buffer area 3 n ^- type drift area 4 p type base area 5 n ⁺ type source area 6 p ⁺ type contact area 7 trench 8 gate insulating film 9 gate electrode 10 silicon carbide semiconductor device 11 layers Insulating film 12 Source electrode 13 Drain electrode 30 Semiconductor substrate 31 n ⁺ type starting substrate 32 n-type epitaxial layer 33 n ^- type epitaxial layer 34 p-type epitaxial layer 41 n ^- type first boundary between drift region and p-type base region 41a , the projections 41a of the side surface of the trench after the etching step S4 in 42a Figure 2 ', 42a' second and the protrusion 42 p-type base region and the n ⁺ -type source region generated on the side surface of the trench etch step S1 of FIG. 2 Boundary X First direction in which the trench extends parallel to the front surface of the semiconductor substrate Y Second direction orthogonal to the side wall of the trench Z Depth direction d From the apex of the protrusion on the side wall of the trench to the side wall of the trench between the protrusions Distance to the surface (exposed surface) of the epitaxial layer exposed to

Claims (9)

A semiconductor substrate made of silicon carbide and
A first conductive type first semiconductor region provided inside the semiconductor substrate, and
A second conductive type second semiconductor region provided between the first main surface of the semiconductor substrate and the first semiconductor region, and
A first conductive type third semiconductor region selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region,
A trench that penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region,
A gate insulating film provided along the inner wall of the trench and
A gate electrode provided on the gate insulating film inside the trench and
A first electrode electrically connected to the third semiconductor region and the second semiconductor region,
A second electrode provided on the second main surface of the semiconductor substrate and
With
A silicon carbide semiconductor device characterized in that the protrusion height is 3 nm or less at the interface between different conductive type regions on the side wall of the trench. A first step of forming a first conductive silicon carbide layer, which is a first conductive type first semiconductor region having a lower impurity concentration than the starting substrate, on a first conductive type starting substrate made of silicon carbide.
A second step of forming a second conductive silicon carbide layer, which is a second conductive type second semiconductor region, on the first conductive silicon carbide layer.
A third step of selectively forming a first conductive type third semiconductor region on the surface region of the second conductive type silicon carbide layer, and
A fourth step of forming a trench that penetrates the third semiconductor region and the second conductive silicon carbide layer and reaches the first conductive silicon carbide layer by the first etching.
The fifth step of rounding the corners of the trench by heat treatment and
After the fifth step, a sixth step of second etching the inner wall of the trench in a plasma atmosphere and
After the sixth step, a seventh step of depositing a gate insulating film along the inner wall of the trench and
The eighth step of forming the gate electrode on the gate insulating film inside the trench, and
Including
The etching gas of the second etching is a silicon carbide semiconductor characterized in that it does not contain a first element that attaches carbon-containing deposits to the inner wall of the trench and a second element that oxidizes the inner wall of the trench. Manufacturing method of the device. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the first element is carbon. The method for manufacturing a silicon carbide semiconductor device according to claim 2 or 3, wherein the second element is oxygen. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 2 to 4, wherein the etching gas for the second etching is nitrogen trifluoride gas. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 2 to 4, wherein the etching gas for the second etching is chlorine trifluoride gas. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 2 to 6, wherein the second etching is chemical dry etching. The silicon carbide according to any one of claims 2 to 7, wherein the etching amount of the second etching is 100 nm or less in a direction orthogonal to the side wall of the trench from the side wall of the trench. Manufacturing method for semiconductor devices. In the sixth step, in the first etching of the fourth step, the boundary between the first conductive type silicon carbide layer and the second conductive type silicon carbide layer on the side wall of the trench, and the second conductive type. Since the etching rates of the boundary between the type silicon carbide layer and the third semiconductor region and the surface between the boundaries are different, the height of the protrusions generated at each boundary is lowered by the second etching. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 2 to 8, wherein the thickness is 3 nm or less.

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