JP2010238725A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device suppressing local thinning of a gate insulating film in a trench gate structure and to provide a method for manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device includes first conduction type semiconductor layers 1 and 2, a second conduction type base layer 3 arranged on a first main face of the semiconductor layer 2, a first conduction type source region 4 which is selectively disposed on a surface layer part of the base layer 3, a first main electrode 11 installed on a surface of the source region 4, a second main electrode 12 arranged on a second main face of the semiconductor layer 1, a gate insulating film 5 disposed on a base and a side of a trench T formed from the surface of the source region 4 to depth of the semiconductor layer 2 through the base layer 3 and a gate electrode 6 installed inside the gate insulating film 5 in the trench T. The base and the side of the trench T have the same plane orientation and the curvature radius of the base is not less than 100 nm. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In a device such as a vertical MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) having a trench gate structure, it is important to make the thickness of the gate oxide film formed on the side and bottom surfaces of the trench uniform. In particular, when a portion having a thin oxide film locally exists on the bottom surface of the trench, the breakdown voltage is lowered.

  For example, Patent Document 1 proposes a technique for making the film thickness uniform by making the growth direction of the oxide film on the side surface and the bottom surface the same by making the surface orientations of the side surface and the bottom surface of the trench the same. In this case, the surface orientations of the side surface and the bottom surface of the trench are made the same as the surface orientation of the wafer main surface. Therefore, it is important that a surface inclined with respect to the main surface of the wafer does not appear on the bottom surface of the trench.

Japanese Patent No. 3490857

  The present invention provides a semiconductor device that suppresses local thinning of a gate insulating film in a trench gate structure and a manufacturing method thereof.

According to one aspect of the present invention, a first conductivity type semiconductor layer having a first main surface and a second main surface formed on the opposite side of the first main surface; A second conductivity type base layer provided on the first main surface side, a first conductivity type source region selectively provided on a surface layer portion of the base layer, and a surface of the source region. The first main electrode, the second main electrode provided on the second main surface of the semiconductor layer, and the depth from the surface of the source region to the semiconductor layer through the base layer A gate insulating film provided on the bottom and side surfaces of the trench, and a gate electrode provided inside the gate insulating film in the trench, wherein the bottom surface and the side surface of the trench have the same plane orientation. The curvature radius of the bottom surface is 100 nm or more A semiconductor device is provided.
According to another aspect of the present invention, a step of forming, in the semiconductor layer, a trench having the same bottom and side surface orientation and a curvature radius of the bottom surface of 100 nm or more, and the bottom surface of the trench. And a step of forming a gate insulating film on the side surface, and a step of forming a gate electrode inside the gate insulating film in the trench.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which suppresses local thinning of the gate insulating film in a trench gate structure, and its manufacturing method are provided.

1 is a schematic cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention. 1 is a schematic plan view of a semiconductor wafer on which a semiconductor device according to an embodiment is formed. FIG. 5 is a schematic cross-sectional view showing a method for forming a trench gate structure in the semiconductor device according to the embodiment. The schematic cross section of the state where the oxide film became thin locally at the trench bottom in a comparative example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the first conductivity type will be described as n-type and the second conductivity type will be described as p-type. However, the present invention can also be applied when the first conductivity type is p-type and the second conductivity type is n-type. Further, although silicon is exemplified as the semiconductor, a semiconductor other than silicon (for example, a compound semiconductor such as SiC or GaN) may be used.

  The semiconductor device according to the present embodiment includes a first main electrode provided on the first main surface side in the semiconductor layer, and a second main surface side provided on the opposite side of the first main surface. 2 is a vertical device in which a main current flows in a vertical direction connecting between the two main electrodes, and includes a cell region in which the main current flows and a termination region formed outside the cell region so as to surround the cell region. .

  In the present embodiment, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is exemplified as the trench gate type element structure in the cell region. Enhanced Gate Transistor) may be used.

  FIG. 1A is a schematic cross-sectional view of a part of the cell region of the semiconductor device according to the present embodiment, and FIG. 1B is an enlarged schematic cross-sectional view of the bottom of the trench T.

An n ⁻ type drift layer 2 is provided on the first main surface of the n ⁺ type drain layer (or substrate) 1. A p-type base layer 3 is provided on the drift layer 2. An n ⁺ -type source region 4 and a p ⁺ -type base contact region 7 are selectively provided in the surface layer portion of the base layer 3.

  A first main electrode 11 is provided on the surface of the source region 4, and the source region 4 is electrically connected to the first main electrode 11. Further, a contact trench is formed from the surface of the source region 4 to the base contact region 7, and the first main electrode 11 is embedded in the contact trench, and the first main electrode 11 is connected to the base contact region 7. It touches. Accordingly, the base contact region 7 is electrically connected to the first main electrode 11, and the potential of the first main electrode 11 is applied to the base layer 3 through the base contact region 7. A second main electrode 12 is provided on the back surface (second main surface) of the drain layer 1, and the drain layer 1 is electrically connected to the second main electrode 12.

  A plurality of trenches T are formed from the surface of the source region 4 to the depth reaching the drift layer 2 through the base layer 3. The trench T is formed in a striped planar pattern extending in a direction penetrating the paper surface in FIG. A gate insulating film 5 is formed on the bottom surface Tb of the trench T and the side surface Ts in a direction orthogonal to the stripe extending direction.

  A gate electrode 6 is embedded inside the gate insulating film 5 in the trench T. An insulating layer 8 is provided on the gate electrode 6, and the gate electrode 6 and the first main electrode 11 are insulated by the insulating layer 8. A part of the gate electrode 6 is drawn upward and connected to a gate wiring (not shown). The gate insulating film 5 and the insulating layer 8 are made of, for example, silicon oxide, and the gate electrode 6 is made of, for example, polycrystalline silicon.

  The trench gate structure configured by providing the gate electrode 6 in the trench T through the gate insulating film 5 is provided in a portion adjacent to the source region 4 and the base layer 3, and the gate electrode 6 is similar to the trench T in FIG. In FIG. 1A, the base layer 3 is opposed to the gate insulating film 5 while extending in a direction penetrating the paper surface. Similarly, the source region 4 is also formed in a striped planar pattern extending in a direction penetrating the paper surface in FIG.

  In a state where the second main electrode 12 is at a higher potential than the first main electrode 11, a desired control voltage is applied to the gate electrode 6 from the gate drive circuit via the gate wiring (both not shown). When applied, an n channel (inversion layer) is formed in the portion of the base layer 3 facing the gate electrode 6, and the main electrode 12, 11 is interposed via the drain layer 1, drift layer 2, n channel and source region 4. The main current flows in the vertical direction and the device is turned on.

  In the present embodiment, the bottom surface Tb and the side surface Ts of the trench T are crystal planes having the same plane orientation. For example, the surface orientation of the bottom surface Tb and the side surface Ts of the trench T is the same as the surface orientation of the main surface of the drain layer (or substrate) 1 (100).

  Further, it is possible to prevent the surface other than the (100) plane from appearing on the bottom surface Tb of the trench T as much as possible, that is, to prevent the surface inclined to the main surface of the drain layer 1 and having a plane orientation different from that main surface. Therefore, the curvature radius of the bottom surface Tb of the trench T is set to be 100 nm or more. Alternatively, the round coefficient b / a defined below is set to satisfy 0 <b / a ≦ 0.06.

  Here, as shown in FIG. 1B, a is the width of the trench T (the width in the direction orthogonal to the stripe-shaped extending direction). If a straight line (two-dot chain line) in contact with the bottom surface Tb at a position of 1/2 of the width a is A, the distance from the straight line A to the bottom surface Tb at the position a / 4 from the side surface Ts of the trench T is b. is there.

  When the curvature radius of the bottom surface of the trench T is smaller than 100 nm, or the round coefficient b / a is larger than 0.06, as shown in FIGS. 4 (a) and 4 (b), a plane orientation ( 110) appears. The growth rate of the oxide film on the (110) plane is faster than the growth rate of the oxide film on the (100) plane, which is the plane orientation near the center in the width direction on the side surface and the bottom surface of the trench T. As shown in a) and (b), the oxide film grows locally from the (110) plane that exists so as to sandwich the center of the bottom surface, and locally grows near the center of the bottom surface between the (110) surfaces. As a result, a thin oxide film is produced. This local thinning of the oxide film on the bottom surface can cause a decrease in breakdown voltage.

  However, according to the present embodiment, as described above, the radius of curvature of the bottom surface Tb of the trench T is 100 nm or more, or the round coefficient b / a satisfies 0 <b / a ≦ 0.06. I am doing so. Specifically, the shape control of the bottom surface Tb of the trench T as described above is realized by controlling the etching conditions when forming the trench T described later.

  Therefore, it is possible to suppress the appearance of a surface having a plane orientation different from that of the side surface Ts on the bottom surface Tb of the trench T, thereby suppressing variation in the growth rate of the gate insulating film 5 between the side surface Ts and the bottom surface Tb. The film thickness of the gate insulating film 5 can be made substantially the same between the bottom surface Tb. As a result, it is possible to suppress local thinning of the gate insulating film 5 on the bottom surface Tb of the trench T and prevent a decrease in breakdown voltage due to the thinning.

  Next, with reference to FIGS. 2 and 3, a method for manufacturing the semiconductor device according to the present embodiment will be described.

  The semiconductor device according to the present embodiment is formed on, for example, a silicon wafer W shown in FIG. 2A where the main surface has a surface orientation of (100) and the orientation flat surface OF has a surface orientation of (100). .

  FIG. 2A schematically shows a cell region c in one chip, and the plurality of trenches T are formed to extend in a direction parallel to the orientation flat surface OF.

First, an n ⁻ type drift layer 2 is formed on a main surface of a silicon wafer W (corresponding to the drain layer 1) by an epitaxial growth method, and then a p type base layer 3 is formed on the surface layer thereof. Further, a silicon oxide film is formed on the surface of the base layer 3, and n-type impurities such as arsenic (As) are selectively implanted and diffused into the surface layer of the base layer 3 to form the source region 4.

  Next, as shown in FIG. 3A, the silicon oxide film 21 on the surface of the source region 4 is selectively etched to form an opening 21a. Then, RIE (Reactive Ion Etching) is performed using the silicon oxide film 21 as a mask, and as shown in FIG. 3B, a part of the drift layer 2 penetrates the source region 4 and the base layer 3 under the opening 21a. A trench T reaching to is formed.

  At this time, as described above, by making the extending direction of the trench T parallel to the orientation flat surface OF, the side surface Ts of the trench T becomes parallel to the orientation flat surface OF. The plane orientation of Ts is the same as the plane orientation of the orientation flat plane OF (100). The surface orientation of the bottom surface Tb of the trench T is the same (100) as the main surface of the silicon wafer W (drain layer 1). Therefore, the side surface Ts and the bottom surface Tb in the trench T have the same plane orientation (100).

  Furthermore, when the trench T is formed, the RIE conditions are controlled so that the curvature radius of the bottom surface Tb is 100 nm or more, or the round coefficient b / a satisfies 0 <b / a ≦ 0.06. The

Specifically, the silicon wafer W is supported by the wafer support portion in a processing chamber in a reduced pressure atmosphere with a desired gas. A gas containing SF ₆ is introduced into the processing chamber. High frequency power is applied as a bias power to the wafer support, and the introduced gas is turned into plasma. The positive ions in the plasma are accelerated toward the wafer W and collide with the wafer W, and the source region 4, the base layer 3 and the drift layer 2 below the opening 21a shown in FIG. Is formed.

In the present embodiment, a deposit of SiF ₄ is generated by the above-described plasma formation, and generation of this deposit (film) suppresses isotropic etching due to reaction (bonding) between Si and F radicals, and F ions Anisotropic etching by sputtering is dominant. As a result, it is possible to suppress the appearance of the surface (110) inclined with respect to the main surface of the wafer on the bottom surface Tb by decreasing the radius of curvature of the bottom surface Tb of the trench T or increasing the round coefficient b / a.

In general, HBr gas is used as an etching gas for RIE of silicon, but in this embodiment, a gas mainly containing SF ₆ that does not contain HBr is used, so that in the processing chamber as compared with the case where HBr is used. Generation of dust can be suppressed and contamination in the processing chamber can be reduced.

For example, when RIE was performed under the following conditions, a trench bottom satisfying the above-described desired radius of curvature or round coefficient could be obtained. As the RIE apparatus, an ECR (Electron Cyclotron Resonance) type apparatus was used. Each gas of SF ₆ , SiF ₄ , and O ₂ was introduced into the processing chamber at a flow rate of 25 to 45 sccm, 20 to 40 sccm, and 38 to 52 sccm, respectively, and the pressure in the processing chamber atmosphere was set to 0.3 to 1.3 Pa. The bias power to the wafer side was 120 to 230 W, and the cold cathode temperature was −50 to −20 ° C.

Alternatively, SF ₆ , SiF ₄ , O ₂ , HBr, and NF ₃ gases are introduced into the processing chamber at flow rates of 17 to 33 sccm, 50 to 90 sccm, 38 to 52 sccm, 17 to 33 sccm, and 0 to 10 sccm, respectively. The pressure of the room atmosphere was 0.3 to 1.5 Pa. The bias power to the wafer side was 70 to 130 W, and the cold cathode temperature was −50 to −20 ° C.

  Next, as shown in FIG. 3C, the opening edge portion of the silicon oxide film 21 facing the trench T is selectively etched to widen the opening width to expose the upper end corner portion of the trench T, and then CDE. (Chemical Dry Etching) is performed. Bias power is not applied to the wafer W side. As a result, the upper corner portion and the bottom corner portion of the trench T are isotropically etched, and the corners are removed and rounded. Thereby, local electric field concentration to the trench corner can be suppressed, and the breakdown voltage can be improved. In addition, this CDE can remove a portion damaged by ion bombardment at the time of RIE performed earlier, and can suppress fluctuations in characteristics such as a threshold and a decrease in carrier mobility.

Also during this CDE, the CDE conditions (etching amount) so that the radius of curvature of the bottom surface Tb of the trench T becomes 100 nm or more, or the round coefficient b / a satisfies 0 <b / a ≦ 0.06. , Etching time, etc.) are controlled. For example, each gas of CF ₆ and O ₂ was introduced into the processing chamber at a flow rate of 200 to 370 sccm and 20 to 40 sccm, respectively.

  Next, the entire main surface side of the silicon wafer W is thermally oxidized to form a gate insulating film (silicon oxide film) 5 on the bottom surface Tb and the side surface Ts of the trench T as shown in FIG. In the oxide film growth step at this time, since the surface orientation of the bottom surface Tb and the side surface Ts of the trench T are both (100), the growth rate of the oxide film on the bottom surface Tb and the side surface Ts becomes equal. The shape of the bottom surface Tb is controlled so that the radius of curvature of the bottom surface Tb is 100 nm or more, or the round coefficient b / a satisfies 0 <b / a ≦ 0.06. 110) The appearance of the surface can be suppressed.

  From the above, the film thickness of the gate insulating film 5 on the bottom surface Tb is substantially equal to the film thickness of the gate insulating film 5 on the side surface Ts. In particular, even when the trench width is reduced, the gate insulating film 5 can be formed with a uniform film thickness. As a result, the threshold voltage can be made uniform regardless of the location of the gate insulating film 5, and the local thinning of the gate insulating film 5 on the bottom surface Tb can be suppressed, thereby preventing a decrease in breakdown voltage.

For example, in a 40V power MOSFET, when the breakdown voltage is compared between a trench bottom surface Tb with a curvature radius of 90 nm and 120 nm, the breakdown voltage of the curvature radius of 120 nm is 2 to 3.5 V higher than that of 90 nm. was gotten. Furthermore, a reliability test was conducted on both of them. In this environment, the applied voltage was increased by 2V every 8 minutes from −20V under an environment of 150 ° C., and TDDB (Time Dependent Dielectric Breakdown) was evaluated. As a result, when the radius of curvature was 90 nm, the TDDB was 1.0 × 10 ¹¹ hours, and when the radius was 120 nm, the TDDB was 1.3 × 10 ¹³ hours. That is, the time at which the curvature radius dielectric breakdown is more ones of 120nm is longer approximately 10 ² hours. When the curvature radius of the trench bottom Tb was 100 nm or more, there was almost no difference in the breakdown voltage and TDDB.

  After the formation of the gate insulating film 5, for example, a polycrystalline silicon film is deposited on the entire main surface side of the silicon wafer W, and the trench T is filled with the polycrystalline silicon. A gate electrode 6 shown in a) is formed. Thereafter, the insulating layer 8, the first main electrode 11, the second main electrode 12 and the like are formed, and the structure shown in FIG. 1A is obtained.

  In the above-described embodiment, the trench gate structure is formed after the source region 4 is formed. However, after forming the trench gate structure, the source region 4 is formed by selectively implanting n-type impurities into the surface layer of the base layer 3. You may make it form.

  Further, as shown in FIG. 2B, a silicon wafer W having a main surface orientation of (100) and an orientation flat surface OF of (110) is used, and the extending direction is relative to the orientation flat surface OF. Even if the trench T is formed to be 45 °, both the surface orientations of the bottom surface Tb and the side surface Ts of the trench T can be (100).

  The planar pattern of the trench gate structure and the source region adjacent to the trench gate structure is not limited to a stripe shape, and may be formed in a lattice shape, a staggered shape, a hexagonal shape, or the like.

  DESCRIPTION OF SYMBOLS 1 ... Drain layer, 2 ... Drift layer, 3 ... Base layer, 4 ... Source region, 6 ... Gate electrode, 7 ... Base contact region, 11 ... 1st main electrode, 12 ... 2nd main electrode, T ... Trench

Claims (5)

A first conductivity type semiconductor layer having a first main surface and a second main surface formed on the opposite side of the first main surface;
A second conductivity type base layer provided on the first main surface side of the semiconductor layer;
A source region of a first conductivity type selectively provided in a surface layer portion of the base layer;
A first main electrode provided on a surface of the source region;
A second main electrode provided on the second main surface of the semiconductor layer;
A gate insulating film provided on a bottom surface and a side surface of a trench formed from the surface of the source region to a depth reaching the semiconductor layer through the base layer;
A gate electrode provided inside the gate insulating film in the trench;
With
The bottom surface and the side surface of the trench have the same plane orientation, and the curvature radius of the bottom surface is 100 nm or more.   The semiconductor device according to claim 1, wherein a surface orientation of the bottom surface and the side surface of the trench is (100). Forming in the semiconductor layer a trench having the same surface orientation of the bottom surface and the side surface, and a curvature radius of the bottom surface of 100 nm or more;
Forming a gate insulating film on the bottom and side surfaces of the trench;
Forming a gate electrode inside the gate insulating film in the trench;
A method for manufacturing a semiconductor device, comprising: The method according to claim 3, wherein the forming the trench by dry etching using a raw material gas containing SF ₆ while applying a bias power to the semiconductor wafer side formed with the semiconductor layer. Forming the semiconductor layer, which is a silicon layer, on the main surface of the silicon wafer having a main surface orientation of (100);
5. The extending direction of the trench with respect to the orientation flat surface of the silicon wafer is set so that a (100) plane is exposed on a side surface of the trench formed in the semiconductor layer. The manufacturing method of the semiconductor device of description.

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