CN107359121B - Preparation method of VDMOS power device and VDMOS power device - Google Patents
Preparation method of VDMOS power device and VDMOS power device Download PDFInfo
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- CN107359121B CN107359121B CN201610304825.1A CN201610304825A CN107359121B CN 107359121 B CN107359121 B CN 107359121B CN 201610304825 A CN201610304825 A CN 201610304825A CN 107359121 B CN107359121 B CN 107359121B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 80
- 238000005530 etching Methods 0.000 claims abstract description 56
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 36
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 16
- 238000001259 photo etching Methods 0.000 claims description 13
- 210000000746 body region Anatomy 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 62
- 125000006850 spacer group Chemical group 0.000 abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention provides a preparation method of a VDMOS power device and the VDMOS power device, wherein the preparation method comprises the following steps: growing a gate oxide layer and a polycrystalline grid on a substrate with an epitaxial layer in sequence, and oxidizing the polycrystalline grid to form an oxide layer; generating a silicon nitride layer on the oxide layer to form a target substrate structure; and finishing the preparation of the VDMOS power device on the basis of the target substrate structure. Through the technical scheme of the invention, the production process flow of the traditional VDMOS power device can be effectively optimized, the problem of failure of the electrical parameters of the power device caused by narrow process window in the Spacer process etching process is solved, the high performance of the power device can be ensured, and the process cost can be reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a VDMOS power device and the VDMOS power device.
Background
A Vertical Double-diffused metal Oxide Semiconductor (VDMOS) transistor combines the advantages of a bipolar transistor and a general MOS power device, and the VDMOS power device is an ideal power device regardless of switching application or linear application. The VDMOS power device is mainly used for motor speed regulation, inverters, uninterrupted power supplies, electronic switches, high-fidelity acoustics, automobile electric appliances, electronic ballasts and the like. The VDMOS power device is divided into an enhancement type VDMOS power device and a depletion type VDMOS power device.
With the development of the semiconductor design field and the semiconductor process field, the current VDMOS power device has been developed toward the low-cost and high-performance field, and how to compress the cost as much as possible on the premise of ensuring the high performance is a main subject of each design company and foundry. The production cost of the device is usually calculated according to the number of times of photolithography, so with the development of the process field, it is the mainstream scheme to reduce the number of times of photolithography in the device production process as much as possible.
The current preparation method of the VDMOS power device is shown in fig. 1a to 1i, and specifically includes the following steps:
(1) as shown in fig. 1a, a gate oxide layer and a poly gate of a power device are grown on an N-type epitaxial layer according to a conventional process, wherein the gate oxide layer is typically grown by thermal oxidation and has a thickness of typically 200 a to 2000 a, and the poly gate has a thickness of typically 3000 a to 10000 a, preferably 6000 a.
(2) As shown in fig. 1b, the poly gate is oxidized to obtain an oxide layer with a thickness of 5000 angstroms, and the poly gate is reacted away by about 3000 angstroms during the oxidation process.
(3) As shown in fig. 1c, a photoresist layer is grown on the oxide layer to perform a photolithography process on the oxide layer, the poly gate electrode and the gate oxide layer according to the photoresist layer.
(4) As shown in fig. 1d, the oxide layer, the poly gate and the gate oxide layer are etched under the barrier of the photoresist layer, and the photoresist layer is removed after the etching is completed.
(5) And as shown in fig. 1e, the body self-aligned implantation and drive-in of the power device are completed, and the source region self-aligned implantation is performed.
(6) As shown in fig. 1f, L PTEOS Spacer (L PTEOS is mainly used for Spacer, Spacer process is used for self-alignment of source and drain region implantation and channel effect reduction due to source and drain lateral diffusion) Deposition is performed, and a layer of TEOS (tetraethoxysilane) is deposited on the surface of the device by adopting a L PCVD (L owPressure Chemical Vapor Deposition), and the thickness is usually 3000 a to 4000 a.
(7) As shown in fig. 1g, the TEOS layer is L PTEOS etched, and the TEOS layer on the sidewalls of the oxide layer, the poly gate and the gate oxide layer remains after etching.
The process is the most difficult, if the TEOS layer on the surface of the source region is to be etched cleanly, a certain amount of Over Etch must be added, at this time, because the etching rate of the oxide layer on the surface of the poly-gate is not consistent with the etching rate of the TEOS layer (the TEOS layer is faster), the TEOS layer on the sidewall of the poly-gate will be etched faster, and in the worst case, as shown in fig. 1h, the poly-gate is exposed, and after subsequent metal filling, the short circuit between the gate and the source of the device will be directly caused, and the device will fail.
(8) As shown in FIG. 1i, the L PTEOS etched device was self-aligned via etched and the metal connection was completed.
Therefore, how to optimize the production process flow of the conventional VDMOS power device, and solve the problem of failure of the electrical parameters of the power device due to the narrow process window in the Spacer process etching process, not only can ensure the high performance of the power device, but also can reduce the process cost, and thus the problem to be solved is urgently needed.
Disclosure of Invention
Based on the problems, the invention provides a novel preparation scheme of the VDMOS power device, which can effectively optimize the production process flow of the traditional VDMOS power device, solve the problem of failure of the electrical parameters of the power device caused by narrow process window in the Spacer process etching process, ensure the high performance of the power device and reduce the process cost.
In view of the above, an aspect of the present invention provides a method for manufacturing a VDMOS power device, including: growing a gate oxide layer and a polycrystalline grid on a substrate with an epitaxial layer in sequence, and oxidizing the polycrystalline grid to form an oxide layer; generating a silicon nitride layer on the oxide layer to form a target substrate structure; and finishing the preparation of the VDMOS power device on the basis of the target substrate structure.
In the technical scheme, after a gate oxide layer, a polycrystalline grid and an oxide layer are sequentially grown on an epitaxial layer according to the traditional production process of the VDMOS power device, a silicon nitride layer is grown on the surface of the oxide layer to form a target substrate structure, so that the etching height of the subsequent Spacer process is increased, namely, a process window is widened.
In the foregoing technical solution, preferably, the completing the preparation of the VDMOS power device on the basis of the target substrate structure specifically includes: growing a photoetching layer on the silicon nitride layer; etching the silicon nitride layer, the oxide layer, the polycrystalline grid and the grid oxide layer in sequence according to the photoetching layer; and removing the photoetching layer after the etching treatment is finished.
According to the technical scheme, after the silicon nitride layer is generated on the surface of the oxide layer, the photoetching layer is grown on the silicon nitride layer, so that the silicon nitride layer, the oxide layer, the polycrystalline grid electrode and the grid oxide layer are etched, and the photoetching layer is removed after the etching is finished, so that a better side wall appearance is obtained, and the reliability of the VDMOS power device is ensured.
In any of the above technical solutions, preferably, after removing the photoresist layer, the method further includes: and depositing a TEOS layer on the target substrate structure after etching treatment.
In the technical scheme, after the etching is finished and the photoetching layer is removed, L PTEOS Spacer deposition is carried out to deposit a TEOS layer on the surface of the etched target substrate structure so as to ensure the reliability of the VDMOS power device.
In any of the above technical solutions, preferably, the target substrate structure after the etching process is subjected to a deposition process by L PCVD.
In the technical scheme, a TEOS layer is deposited on the surface of a target substrate structure subjected to etching treatment in an L PCVD mode, so that the reliability of the VDMOS power device is ensured.
In any of the above solutions, preferably, the thickness of the TEOS layer is between 3000 angstroms and 4000 angstroms.
In the technical scheme, the thickness of the TEOS layer deposited on the surface of the target substrate structure subjected to etching treatment is preferably between 3000 angstroms and 4000 angstroms, so that the reliability of preparing the VDMOS power device is ensured.
In any of the above technical solutions, preferably, after the forming the TEOS layer, the method further includes: and etching the TEOS layer, and only reserving the etched TEOS layer at the side walls of the silicon nitride layer, the oxide layer, the polycrystalline grid and the gate oxide layer.
In the technical scheme, the Spacer process etching is carried out on the TEOS layer formed on the surface of the target substrate structure after the etching treatment, so that the TEOS layer on the side wall of the silicon nitride layer, the oxidation layer, the polycrystalline grid and the grid oxide layer is reserved, and the height of the longitudinal TEOS layer is increased by 3000 angstroms to 4000 angstroms due to the existence of the silicon nitride layer, so that the process window equivalent to the etching is increased so much, and the sufficient Over Etch amount of the Spacer process etching is ensured, so that the etching rate is relatively slowed down, and the polycrystalline grid is not exposed after the etching is finished, so that the conditions of short circuit between the grid and the source of a device and failure of the device are caused after metal is filled, the production process is greatly optimized, and the high performance of a power device is ensured.
In any of the above technical solutions, preferably, after the etching treatment is performed on the TEOS layer, the method further includes: and sequentially generating a device body region and a source region in the epitaxial layer, so that the source region is in contact with the TEOS layer.
In any of the above technical solutions, preferably, the method further includes: and after etching the source region, growing a metal layer on the target substrate structure on which the device body region and the source region are formed, and completing metal contact so as to complete the preparation of the VDMOS power device.
In the technical scheme, after the TEOS layer is etched, a device body region, a source region and a metal layer of the VDMOS power device can be sequentially formed according to the traditional process, metal contact is completed, the reliability of the VDMOS power device is guaranteed, and therefore the VDMOS power device is manufactured.
On the other hand, the invention provides a VDMOS power device which is prepared by adopting the preparation method of the VDMOS power device in any one of the technical schemes.
In the technical scheme, the gate oxide layer, the polycrystalline grid electrode and the oxide layer are sequentially generated on the epitaxial layer, and then the silicon nitride layer is formed at first, so that the etching height of the subsequent Spacer process is increased, the process window is widened, the production process flow of the traditional VDMOS power device is effectively optimized, the problem that the electrical parameters of the power device are invalid due to the narrow process window in the Spacer process etching process is solved, the high performance of the power device can be ensured, and the process cost can be reduced.
In the above technical solution, preferably, the thickness of the silicon nitride layer is between 3000 angstroms and 4000 angstroms.
In the technical scheme, the thickness of the silicon nitride layer grown on the oxide layer in the preparation process of the VDMOS power device is preferably between 3000 angstroms and 4000 angstroms so as to ensure the reliability of the preparation of the VDMOS power device.
Through the technical scheme of the invention, the production process flow of the traditional VDMOS power device can be effectively optimized, the problem of failure of the electrical parameters of the power device caused by narrow process window in the Spacer process etching process is solved, the high performance of the power device can be ensured, and the process cost can be reduced.
Drawings
Fig. 1a to 1i are schematic diagrams illustrating a method for manufacturing a VDMOS power device according to the related art;
fig. 2 shows a flow diagram of a method of manufacturing a VDMOS power device according to an embodiment of the invention;
fig. 3 to 7 are schematic diagrams illustrating a method for manufacturing a VDMOS power device according to an embodiment of the present invention.
Detailed Description
So that the manner in which the above recited objects, features and advantages of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.
Fig. 2 shows a flow chart of a method for manufacturing a VDMOS power device according to an embodiment of the invention.
As shown in fig. 2, a method for manufacturing a VDMOS power device according to an embodiment of the present invention includes:
and step 206, finishing the preparation of the VDMOS power device on the basis of the target substrate structure.
In the technical scheme, after a gate oxide layer, a polycrystalline grid and an oxide layer are sequentially grown on an epitaxial layer according to the traditional production process of the VDMOS power device, a silicon nitride layer is grown on the surface of the oxide layer to form a target substrate structure, so that the etching height of the subsequent Spacer process is increased, namely, a process window is widened.
In the above technical solution, preferably, the step 206 specifically includes:
step 2062, growing a photoresist layer on the silicon nitride layer;
step 2064, sequentially etching the silicon nitride layer, the oxide layer, the polycrystalline grid and the grid oxide layer according to the photoetching layer;
at step 2066, the photoresist layer is removed after the etching process is completed.
According to the technical scheme, after the silicon nitride layer is generated on the surface of the oxide layer, the photoetching layer is grown on the silicon nitride layer, so that the silicon nitride layer, the oxide layer, the polycrystalline grid electrode and the grid oxide layer are etched, and the photoetching layer is removed after the etching is finished, so that a better side wall appearance is obtained, and the reliability of the VDMOS power device is ensured.
In any of the above technical solutions, after the step 2066, it is preferable that the method further includes:
and step 208, depositing a TEOS layer on the target substrate structure after the etching treatment.
In the technical scheme, after the etching is finished and the photoetching layer is removed, L PTEOS Spacer deposition is carried out to deposit a TEOS layer on the surface of the etched target substrate structure so as to ensure the reliability of the VDMOS power device.
In any of the above solutions, preferably, in the step 208, the target substrate structure after the etching process is subjected to a deposition process specifically by means of L PCVD.
In the technical scheme, a TEOS layer is deposited on the surface of a target substrate structure subjected to etching treatment in an L PCVD mode, so that the reliability of the VDMOS power device is ensured.
In any of the above solutions, the thickness of the TEOS layer in the step 208 is preferably between 3000 angstroms and 4000 angstroms.
In the technical scheme, the thickness of the TEOS layer deposited on the surface of the target substrate structure subjected to etching treatment is preferably between 3000 angstroms and 4000 angstroms, so that the reliability of preparing the VDMOS power device is ensured.
In any of the above technical solutions, preferably, after the step 208, the method further includes:
step 210, etching the TEOS layer, and only reserving the etched TEOS layer at the sidewalls of the silicon nitride layer, the oxide layer, the poly-crystal gate, and the gate oxide layer.
In the technical scheme, the Spacer process etching is carried out on the TEOS layer formed on the surface of the target substrate structure after the etching treatment, so that the TEOS layer on the side wall of the silicon nitride layer, the oxidation layer, the polycrystalline grid and the grid oxide layer is reserved, and the height of the longitudinal TEOS layer is increased by 3000 angstroms to 4000 angstroms due to the existence of the silicon nitride layer, so that the process window equivalent to the etching is increased so much, and the sufficient Over Etch amount of the Spacer process etching is ensured, so that the etching rate is relatively slowed down, and the polycrystalline grid is not exposed after the etching is finished, so that the conditions of short circuit between the grid and the source of a device and failure of the device are caused after metal is filled, the production process is greatly optimized, and the high performance of a power device is ensured.
In any of the above technical solutions, preferably, after the step 210, the method further includes:
step 212, sequentially generating a device body region and a source region in the epitaxial layer, so that the source region is in contact with the TEOS layer;
step 214, after the source region is etched, a metal layer is grown on the target substrate structure where the device body region and the source region are formed, and metal contact is completed, so that the preparation of the VDMOS power device is completed.
In the technical scheme, after the TEOS layer is etched, a device body region, a source region and a metal layer of the VDMOS power device can be sequentially formed according to the traditional process, metal contact is completed, the reliability of the VDMOS power device is guaranteed, and therefore the VDMOS power device is manufactured.
On the other hand, the invention provides a VDMOS power device which is prepared by adopting the preparation method of the VDMOS power device in any one of the technical schemes.
In the technical scheme, the gate oxide layer, the polycrystalline grid electrode and the oxide layer are sequentially generated on the epitaxial layer, and then the silicon nitride layer is formed at first, so that the etching height of the subsequent Spacer process is increased, the process window is widened, the production process flow of the traditional VDMOS power device is effectively optimized, the problem that the electrical parameters of the power device are invalid due to the narrow process window in the Spacer process etching process is solved, the high performance of the power device can be ensured, and the process cost can be reduced.
In the above technical solution, preferably, the thickness of the silicon nitride layer is between 3000 angstroms and 4000 angstroms.
In the technical scheme, the thickness of the silicon nitride layer grown on the oxide layer in the preparation process of the VDMOS power device is preferably between 3000 angstroms and 4000 angstroms so as to ensure the reliability of the preparation of the VDMOS power device.
The following describes in detail a method for manufacturing a VDMOS power device according to an embodiment of the present invention with reference to fig. 3 to 7, where the correspondence between the reference numbers and the component names in fig. 3 to 7 is:
11 epitaxial layer, 12 gate oxide layer, 13 polycrystalline gate, 14 oxide layer, 15 silicon nitride layer, 16TEOS layer, 17 source region, 18 device body region and 19 metal layer.
As shown in fig. 3, a gate oxide layer 12 and a poly gate 13 are formed on an epitaxial layer 11 (e.g., an N-type epitaxial layer) by conventional processes, the poly gate 13 is oxidized to form an oxide layer 14, and a silicon nitride layer 15 is deposited over the oxide layer 14, typically to a thickness in the range of 3000 a to 4000 a.
As shown in fig. 4, the silicon nitride layer 15, the oxide layer 14, the poly gate 13, and the gate oxide layer 14 are etched, so that the silicon nitride layer with one step thickness is added in this step, which means that the height of the subsequent spacer is increased in a direction-changing manner, and the process window is widened.
As shown in FIG. 5, L PTEOS spacer deposition by L PCVD was used to deposit a TEOS layer 16, typically 3000-4000 angstroms thick, on the surface of the device.
As shown in fig. 6, the TEOS layer 16(Spacer) is etched, and in this step, since the height of the vertical TEOS is increased by 3000 angstroms to 4000 angstroms, which is equivalent to that the process window is increased, that is, there can be enough Over Etch amount during Spacer etching, and the problem of electrical parameter failure will not occur.
As shown in fig. 7, the device fabrication is completed according to the conventional process, which includes the following specific steps: and generating a source region and a device body region, and producing a metal layer 18 on the surface to finish the preparation of the diode.
In conclusion, on the basis of the traditional VDMOS power device preparation process, the process flow is optimized, the problems of narrow process window and failure of device electrical parameters caused by the Spacer process etching process are solved, and the low cost is ensured.
The technical scheme of the invention is explained in detail in the above with the help of the attached drawings, and by the technical scheme of the invention, the production process flow of the traditional VDMOS power device can be effectively optimized, the problem of failure of the electrical parameters of the power device caused by narrow process window in the Spacer process etching process is solved, the high performance of the power device can be ensured, and the process cost can be reduced.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A preparation method of a VDMOS power device is characterized by comprising the following steps:
growing a gate oxide layer and a polycrystalline grid on a substrate with an epitaxial layer in sequence, and oxidizing the polycrystalline grid to form an oxide layer;
generating a silicon nitride layer on the oxide layer to form a target substrate structure;
finishing the preparation of the VDMOS power device on the basis of the target substrate structure;
the preparation of the VDMOS power device is completed on the basis of the target substrate structure, and specifically includes:
growing a photoetching layer on the silicon nitride layer;
etching the silicon nitride layer, the oxide layer, the polycrystalline grid and the grid oxide layer in sequence according to the photoetching layer;
removing the photoetching layer after the etching treatment is finished;
depositing a TEOS layer on the target substrate structure after etching treatment;
and carrying out deposition treatment on the target substrate structure after etching treatment in an L PCVD mode.
2. The method of claim 1, wherein the TEOS layer is between 3000 and 4000 angstroms thick.
3. The method for manufacturing a VDMOS power device according to claim 1, further comprising, after forming the TEOS layer:
and etching the TEOS layer, and only reserving the etched TEOS layer at the side walls of the silicon nitride layer, the oxide layer, the polycrystalline grid and the gate oxide layer.
4. The method for manufacturing a VDMOS power device according to claim 3, further comprising, after the etching treatment is performed on the TEOS layer:
and sequentially generating a device body region and a source region in the epitaxial layer, so that the source region is in contact with the TEOS layer.
5. The method for preparing the VDMOS power device according to claim 4, further comprising:
and after etching the source region, growing a metal layer on the target substrate structure on which the device body region and the source region are formed, and completing metal contact so as to complete the preparation of the VDMOS power device.
6. A VDMOS power device, characterized in that, it is prepared by the method of any claim 1 to 5.
7. The VDMOS power device of claim 6,
the silicon nitride layer has a thickness of between 3000 angstroms and 4000 angstroms.
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