JP4088031B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a structure of a semiconductor device having a MOS FET structure in which an N-type region and a P-type region formed in a vertical direction in a unit element region are laterally adjacent to each other The present invention relates to a method, and is used for a power switching element that requires low on-resistance and high breakdown voltage.
[0002]
[Prior art]
Power switching elements using MOS FETs are required to have low on-resistance and high withstand voltage. However, conventional planar power MOS FETs have low on-resistance and low on-resistance. Have a conflicting relationship.
[0003]
That is, in the planar structure power MOS FET as shown in FIG. 5, the MOS structure is formed on the surface of the N-epi layer 62 having a relatively low impurity concentration formed on the N + substrate 61 having a relatively high impurity concentration. The current path from the back surface of the substrate to the MOS FET through the N-epi layer 62 is taken.
[0004]
For this reason, the resistance (ON resistance) during the ON operation of the MOS FET depends on the thickness of the N-epi layer 62. Further, since the depletion layer extends in the N-epi layer 62, the breakdown voltage maintenance is determined by the thickness of the N-epi layer 62. Thus, since the current path and the region for maintaining the withstand voltage are the same, increasing the thickness of the N-epi layer 62 to increase the withstand voltage increases the on-resistance, and conversely, the N-epi layer 62 If the on-resistance is reduced by reducing the thickness of the substrate, there is a conflicting relationship that the breakdown voltage also decreases, and it is difficult to satisfy both.
[0005]
To eliminate the conflicting relationship between low on-resistance and high breakdown voltage in the conventional planar structure power MOS FET described above, for example, "Cool mos-a new milestone in high voltage" Power MOSFET "by L. Lorenz, G. Deboy (Reference 1) proposes a MOS FET (Cool MOS; registered trademark of Siemens) having a Super Junction structure.
[0006]
As shown in FIG. 6, this super-junction structure power MOS FET has an N pillar region 71 serving as a current path and a P pillar layer 72 for maintaining a reverse breakdown voltage between the drain and source in the vertical direction. Forming.
[0007]
With this structure, the on-resistance depends on the concentration of the N pillar layer 71, and the withstand voltage is determined by the concentration and width of the N pillar layer 71 and the P pillar layer 72 because the depletion layer extends in the lateral direction. As a result, the drain-source reverse breakdown voltage (for example, 600 V) equivalent to that of the conventional planar structure power MOS FET shown in FIG. 5 is ensured and the on-resistance is about 1/3 to 1/1 /. 4 can be reduced.
[0008]
[Problems to be solved by the invention]
However, the MOS FET manufacturing process disclosed in Document 1 is complicated because it is necessary to repeat silicon epitaxial growth, patterning, and ion implantation a plurality of times. With such a very long process, cost and time are required, the manufacturing price increases significantly, and there are few advantages in terms of the cost of the semiconductor chip.
[0009]
In order to improve this point, the applicant of the present invention is a highly productive deep trench MOS (DTMOS) that can manufacture a power MOS FET that satisfies both low on-resistance and high breakdown voltage at low cost. The structure and its manufacturing method were proposed.
[0010]
This DTMOS structure has a low on-resistance characteristic comparable to that of a superjunction structure, with a relatively short manufacturing process (deep trench formation, simultaneous ion implantation and thermal diffusion of B and As, insulation isolation region formation, planarization). This makes it possible to realize a MOS FET with the above-mentioned medium and high breakdown voltage, enabling a significant reduction in the number of processes and reducing the manufacturing price by half.
[0011]
Here, an outline of the basic structure of the DTMOS FET according to the above proposal and the manufacturing method thereof will be described.
[0012]
FIG. 7 is a cross-sectional view showing a part of the basic structure of the DTMOS FET currently proposed.
[0013]
Each unit element (cell) of this DTMOS FET is formed by arsenic (As) diffusion on both sides (both sides) of a strip-shaped P + pillar layer 83 formed in a longitudinal direction with a width of 10 μm by boron (B) diffusion. It has an NPN pillar layer in which an N + pillar layer 84 having a strip-like cross section formed in a vertical direction with a width of about 2.5 μm exists. A trench (groove) is provided surrounding the NPN pillar layer, and an insulator 85 is embedded therein.
[0014]
The total amount of (As−B) in the two N + pillar layers 84 and the total amount of (B−As) in the P + pillar layer 83 are set to be equal with a difference within ± 5%. This highly accurate control of the amount of impurities can be achieved by ion implantation of As and B into the trench sidewall.
[0015]
A P + base region 87 is formed on the P + pillar layer 83, and an N + source region 86 is selectively formed on the surface of the P + pillar layer 83, so that a channel region (N + source region 86 and N + pillar layer is formed). A gate electrode 89 is formed via a gate oxide film 88 on the surface of the P region sandwiched between 84 and the N + source region 86 through an opening of an interlayer insulating film formed thereon. Thus, a source metal wiring 90 is formed. As a result, a power MOSFET structure in which the N + substrate 80 is a drain and the N + pillar layer 84 is a current path is realized.
[0016]
FIG. 8 is a perspective view showing a part of a planar pattern and a sectional structure of a stripe pattern type DTMOSFET as an example of the DTMOS FET shown in FIG.
[0017]
In this structure, the NPN pillar layer and the trench portion of each unit element are arranged in a planar stripe pattern.
[0018]
FIG. 9 is a perspective view showing a part of a planar pattern and a sectional structure of an offset mesh type DTMOS FET as another example of the DTMOS FET shown in FIG.
[0019]
In this structure, in order to increase the channel density of DTMOS, the NPN pillar layers of each unit element are arranged in a plane offset mesh shape.
[0020]
FIG. 10 is a cross-sectional view showing an example of the structure of the DTMOS FET according to the improvement example of the structure of the N + pillar layer of the DTMOS FET shown in FIGS.
[0021]
In the structure shown in FIGS. 7 to 9, since a depletion layer spreads on the surface of the N + pillar layer 84 when a voltage is applied, it becomes easy to be affected by surface charge, and if there are Na + ions or the like, depletion is partially prevented. There is a risk that electric field concentration will occur in that part, leading to breakdown.
[0022]
On the other hand, in the structure shown in FIG. 10, a depletion layer is formed on the surface of the N + pillar layer 84 when a voltage is applied by forming the N + region 84a in a part of the surface of the N + pillar layer 84 connected to the trench sidewall. It is trying not to reach. In this case, since the N + region 84a can be formed simultaneously with the formation of the N source region, the number of processes is not increased.
[0023]
FIG. 11 is a cross-sectional view showing an example of the structure of a DTMOS FET according to an improved example of the structure of the insulator 85 inside the trench shown in FIGS.
[0024]
In the structure shown in FIGS. 7 to 9, the inside of the trench is filled with the insulator 85, but it takes a long time to completely fill the inside of the trench with the insulator 85 such as an oxide film (SiO ₂ film). I need. Also, in the thermal process after filling, a large thermal stress is applied to the silicon at the bottom of the trench due to the difference in thermal expansion coefficient between the silicon of the N + pillar layer 84 and the P + pillar layer 83 and the insulator 85 such as the SiO ₂ film. Crystal defects may occur intensively and leakage current may increase.
[0025]
On the other hand, in the structure shown in FIG. 11, an insulating film 85a is formed on the side surface of the trench, and then the trench is filled with polysilicon (Poly Si) 85b. The polysilicon 85b inside the trench is not a current path and does not need to be completely buried, and can therefore be formed (buried) at a high growth rate (short time).
[0026]
In addition, since the thermal expansion coefficients of the silicon in the N + pillar layer 84 and the P + pillar layer 83 and the polysilicon 85b in the trench are equal, a large thermal stress is applied to the silicon at the bottom of the trench even after a thermal process after filling the polysilicon 85b. Absent. Therefore, it is possible to prevent the occurrence of crystal defects in the portion and increase in leakage current.
[0027]
FIG. 12 shows a part of the cross-sectional structure of the DTMOS FET in order to schematically explain a part of the manufacturing process of the DTMOS FET shown in FIG.
[0028]
First, a trench 82 reaching the N + substrate 80 from the surface of the N-epi layer 81 formed on the N + substrate 80 is formed by reactive ion etching (RIE). At this time, the portion other than the trench on the surface of the N-epi layer 81 is covered with the oxide film 91.
[0029]
Next, As and B ions are implanted into the trench sidewall at an implantation angle of about 7 °, for example, by the rotary ion implantation method. Next, simultaneous diffusion of As and B is performed by thermal diffusion at 1150 ℃ for 24 hours or more.
[0030]
At this time, as the diffusion coefficient of B is sufficiently larger than the diffusion coefficient of As, As diffuses from the trench side wall by approximately 2.5 μm to become the N + pillar layer 84, and B diffuses by approximately 7.5 μm and from both sides. P + pillar layer 83 is formed by overlapping the diffusion of the P + pillar layer 83. That is, the structure after the heat treatment completes an NPN pillar layer in which the N + pillar layer 84 is present on the trench side wall with the internal P + pillar layer 83 interposed therebetween.
[0031]
Next, an oxide film (SiO ₂ film) is formed on the side surface of the trench by thermal oxidation, and further, a SiO ₂ film or a SiN film is formed by a chemical vapor deposition (CVD) method. At this time, in order to realize the structure of the insulator as shown in FIG. 11, an insulating film, for example, an oxide film (SiO ₂ film) 85a is formed on the side surface of the trench, and then the inside of the trench is backfilled with polysilicon 85b. You may do it. At this time, since the polysilicon 85b in the trench is grown from both sides of the trench side surface, it can be buried in a short time.
[0032]
Next, the substrate surface is planarized by chemical mechanical polishing (CMP). Subsequent processes are performed in the same manner as the planar MOS FET manufacturing process. As shown in FIG. 7, a P + base region is formed on the P + pillar layer 83, and an N + is partially formed on the P + base region. By forming a gate electrode through a gate oxide film on the source region and the channel region (the P region surface portion sandwiched between the N + source region and the N + pillar layer), the N + substrate 80 serves as the drain, and the N + pillar layer 84 A power MOS FET structure with a current path as the current path is realized.
[0033]
In the above manufacturing method, the P + pillar layer 83 and the N + pillar layer 84 are formed, and the process until the surface is flattened is one N-epitaxial growth, one trench filling, and few implantations of B ions and As ions. .
[0034]
By the way, in the structure shown in FIG. 7, in order to secure the threshold voltage Vth of the MOS FET, the P + base region 87 on the upper surface of the P + pillar layer 83 is formed so as to have a higher concentration than the P + pillar layer 83. B ions must be implanted and thermally diffused.
[0035]
Therefore, the boundary between the P + base region 87 having a high impurity concentration and the P + pillar layer 83 has a problem that the concentration gradient becomes steep, electric field concentration tends to occur under the P + base region 87, and the breakdown voltage is disadvantageous.
[0036]
As described above, the power MOS FET having the super junction structure currently proposed has a problem that the electric field is concentrated in the base region under the source region, which is disadvantageous for the reverse breakdown voltage between the drain and the source.
[0037]
The present invention has been made to solve the above problems, and prevents the electric field concentration in the base region under the source region, stably ensuring a higher reverse breakdown voltage between the drain and the source, and having a low on-resistance. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.
[0038]
[Means for Solving the Problems]
Semi conductor arrangement of the present invention includes a semiconductor substrate having a low resistance epitaxial layer, said having a depth reaching the surface of the low-resistance epitaxial layer to said semiconductor substrate, wider opening than bottom, rounded opening edge And a trench having a tapered surface formed therein, and a first conductivity type impurity and a second conductivity type impurity are ion-implanted from the sidewall of the trench into the low resistance epilayer and formed by thermal diffusion, and are opposed to adjacent trenches. A second conductivity type pillar layer formed in a vertical direction along each side wall surface, a first conductivity type pillar layer formed in a vertical direction adjacent to the second conductivity type pillar layer, and embedded in the trench An insulator; a second conductivity type source region selectively formed on a surface of the first conductivity type pillar layer; and a channel between the second conductivity type source region and the second conductivity type pillar layer. A gate insulating film over the region A gate electrode formed as a base, the first conductivity type pillar layer as a base, the second conductivity type pillar layer as a current path, and the semiconductor substrate as a drain. wherein the gradient of the concentration distribution is in a certain concentration is near zero at the surface from 4.0 [mu] m or more depth position of the first conductive type pillar layer.
[0040]
A method of manufacturing a semi-conductor device of the present invention has a depth from the surface of the low-resistance epitaxial layer of a semiconductor substrate having a low resistance epitaxial layer reaches the semiconductor substrate, wider opening than bottom, the opening peripheral edge Forming a trench having a tapered surface with a rounded portion, and performing thermal diffusion by ion implantation of a first conductivity type impurity and a second conductivity type impurity into the sidewall of the trench, thereby performing first diffusion impurity concentration in the depth direction from the surface with by utilizing a difference in impurity diffusion coefficient of the second conductivity type impurity is adjacent along the second conductive type pillar layer along the longitudinal direction and therewith in the vertical direction to the trench side wall forming a first conductive type pillar layer decreases predetermined with depth position until in depth from the surface, planarizing the surface after embedding the inside insulator of said trench, said first conductivity type Pillar layer Selectively forming a second conductivity type source region part surface to form a gate electrode through a gate insulating film on a channel region between the second conductivity type source region and the second conductive type pillar layer comprising a step, wherein a semiconductor substrate as a drain, and forming a MOS FET to a current path between the second conductive type pillar layer between the drain and the second conductivity type source region .
[0041]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0042]
<First Embodiment>
FIG. 1 shows a part of a cross-sectional structure of a DTMOS FET according to the first embodiment of the present invention.
[0043]
This DTMOS FET is formed on a Si wafer and separated into chips. In the N-epi layer formed on the N ++ substrate 1, the width of arsenic (As) diffused about 2.5 μm on both sides (both sides) of a P + pillar layer 3 having a strip-like cross section with a width of 10 μm diffused with boron (B) The NPN pillar layer (width is about 15 μm) in which the N + pillar layer 4 having a strip-like cross section exists is repeatedly present in the left-right direction. In this case, a trench (groove) having a depth (50 μm or more) reaching the inside of the N ++ substrate 1 from the N-epi layer surface and having a width of about 8 μm is provided surrounding the NPN pillar layer, and the insulating layer 5 Is embedded to form a large number of unit elements (cells) separated from each other. In this case, the trench has a depth reaching the N ++ substrate 1 from the surface of the N-epi layer, has an opening wider than the bottom, and has a tapered surface with a rounded periphery at the opening.
[0044]
In the above NPN pillar layer, the total amount of (As−B) in the two N + pillar layers 4 and the total amount of (B−As) in the P + pillar layer 3 are set equal to each other with a difference within ± 5%. ing. That is, the P + pillar layer 3 and the N + pillar layer 4 have substantially the same concentration, and such high-precision control of the impurity amount can be achieved by ion implantation of B and As into the trench sidewall. Further, the distribution of the impurity concentration in the depth direction from the surface in the P + pillar layer 3 is set and controlled as described later.
[0045]
An N + source region 6 is selectively formed on the surface of the P + pillar layer 3, and a gate electrode is formed on the channel region between the N + source region 6 and the N + pillar layer 4 via a gate insulating film 8. 9 is formed, and the source metal wiring 10 is formed so as to contact the N + source region 6 through the opening of the interlayer insulating film formed thereon. Thus, an NMOS FET is formed between the N + source region 6 and the N ++ substrate (drain region) 1 using the N + pillar layer 4 as a current path.
[0046]
A portion having a high impurity concentration near the upper surface of the P + pillar layer 3 can be used as a base region. However, in order to secure a desired threshold voltage Vth, a dotted line in the figure near the upper surface of the P + pillar layer 3 is used. As shown in the figure, even when the P + base region 7 is formed, it is possible to give a gentle gradient in the depth direction even near the boundary between the P + base region 7 and the P + pillar layer 3 as the impurity concentration distribution as described above. it can.
[0047]
As shown in FIG. 11, a dielectric film (eg, Si ₃ N ₄ or SiO ₂ ) is formed on the inner wall of the trench, and then an insulator (polysilicon or SiO ₂ ) is buried in the trench. Good. As the gate insulating film 8 , a thermal oxide film (SiO ₂ ) is used to maintain the strength of the substrate. The gate electrode 9 is made of polysilicon or metal silicide.
[0048]
Similarly to the case shown in FIG. 10, a depletion layer is formed on the surface of the N + pillar layer 4 when a voltage is applied by forming an N + region in a part of the surface of the N + pillar layer 4 that continues to the trench side wall. May not be reached.
[0049]
Further, the planar pattern of the DTMOS FET having the above-described cross-sectional structure may be a stripe pattern as shown in FIG. 8 or an offset mesh type pattern as shown in FIG.
[0050]
FIG. 2 shows an example of the impurity concentration distribution in the vertical cross section (BB line) in the P + pillar layer 3 of the DTMOS FET shown in FIG.
[0051]
In this example, the distribution of the impurity concentration from the upper surface to the depth direction in the P + pillar layer 3 located at the center of the NPN pillar layer of each unit element is the depth direction from the portion where the surface portion concentration is high (base region). Concentration decreases with a gentle gradient toward the surface, and the concentration distribution is almost constant at a depth of about 4.0 μm or more from the surface (deeper than the base region). .
[0052]
3 shows the depth position (P base depth) where the slope of the concentration distribution on the upper surface of the P + pillar layer 3 of the DTMOS FET shown in FIG. It is a graph which shows an example of the result of having verified reverse breakdown voltage between sources by simulation.
[0053]
From this result, if the present invention is applied to a 400 V type DTMOS FET in which a withstand voltage of 400 V is obtained when the P base depth is 3.5 μm, and the P base depth is about 4.0 μm or more, the withstand voltage is 408 V. It can be seen that the breakdown voltage is improved to 413 V or more (3% or more) when the P base depth is about 4.5 μm or more. Even if the present invention is applied to a 600 V DTMOS FET, it can be easily assumed that the same effect can be obtained.
[0054]
That is, according to the structure of the DTMOS FET of the above embodiment, the on-resistance can be greatly reduced as compared with the conventional planar type MOS FET as in the proposed example described above with reference to FIG. Further, the vicinity of the upper surface of the P + pillar layer 3 is used as a base region having a high impurity concentration, so that a desired threshold voltage Vth can be ensured, and the impurity concentration from the upper surface to a predetermined depth portion can be maintained. Since the distribution has a gentle slope, the electric field concentration under the source region can be reduced. As a result, a higher reverse breakdown voltage between the drain and the source can be realized.
[0055]
In the above description, an N-type DTMOS FET is shown, but the present invention can be similarly applied to a P-type DTMOS FET.
[0056]
4A to 4D show a cross-sectional structure of a half of a unit element (cell) taken out as an example of the manufacturing process of the DTMOS FET shown in FIG.
[0057]
That is, first, as shown in FIG. 4A, a low resistance epilayer (N-epi layer) 2 is formed on a semiconductor substrate (N ++ substrate) 1 and then an etching mask is formed on the surface of the N-epi layer 2. 11 is formed, and a trench 12 is formed so as to reach the N ++ substrate 1 from the surface of the N-epi layer 2 and has a wider opening than the bottom surface.
[0058]
At this time, in order to obtain the effect described later, a tapered surface having a roundness is formed at the peripheral edge of the trench opening. As an example of the step of forming the peripheral edge of the trench opening, the vicinity of the peripheral edge of the trench opening of the etching mask (for example, SiO ₂ film) 11 on the substrate used for opening the trench is made to recede after the opening of the trench. Processing (for example, isotropic etching using ammonium fluoride) and etching using CDE may round the trench opening periphery.
[0059]
Further, as another example of the process of forming the peripheral edge of the trench opening as described above, when using an etching machine that opens to taper the side surface of the trench, the supply time of the RIE gas and the supply of the deposit gas You may make it round a trench opening peripheral part by repeating changing time according to a predetermined pattern.
[0060]
Next, as shown in FIG. 4B, for example, by a rotary ion implantation method, a P-type impurity (B 2 in this example) and an N-type impurity (As in this example) are implanted into the trench sidewall at an implantation angle of about 7 °. Ion implantation. At this time, As ions are implanted under the conditions of, for example, an acceleration voltage of 60 KeV and a dose of 4.1 × 10 ¹³ cm ⁻² , and B ions are implanted with an acceleration voltage of 60 KeV and a dose of 4 × 10 ¹³ cm 2, for example. Perform under the condition of ^-2 .
[0061]
Next, simultaneous diffusion of As and B is performed by thermal diffusion at 1150 ℃ for 2000 minutes or more. At this time, since the diffusion coefficient of the diffusion coefficient of B 2 is sufficiently larger than the diffusion coefficient of As, as shown in FIG. 4C, the strip-shaped N pillar layer 4 along the longitudinal direction along the trench side wall and P-pillar layers 3 having a strip-like cross section adjacent to each other in the lateral direction and overlapping from both sides are formed at substantially the same concentration. That is, in the structure after the heat treatment, an NPN pillar layer in which the N pillar layers 4 are present on both sides (trench side wall portions) sandwiching the inner P pillar layer 3 is completed.
[0062]
Further, the total amount of (As−B) in the two N pillar layers 4 and the total amount of (B−As) in the P pillar layer 3 are equal to each other with a difference within ± 5%. This highly accurate control of the impurity amount can be achieved by simultaneous implantation of As and B ions into the trench sidewall as described above.
[0063]
In addition, paying attention to the fact that the dose amount of ion implantation is determined by the direction (angle) of the surface incident by ion implantation, since the tapered surface of the peripheral edge of the trench is rounded in advance, it is incident by ion implantation. The direction (angle) of the surface changes depending on the roundness of the tapered surface, and it becomes possible to control the gradient of the impurity concentration distribution from the upper surface to the depth direction in the P pillar layer 3 to be gentle.
[0064]
Next, as shown in FIG. 4D, after the insulator 5 is buried in the trench, the surface is flattened by, for example, the CMP method or etching. In this example, an oxide film (SiO ₂ film) is formed on the trench surface by thermal oxidation, and a SiO ₂ film or a SiN film is formed by a vapor deposition (CVD) method.
[0065]
At this time, Si ₃ After the N ₄ film or the SiO ₂ film is formed, polysilicon (Poly Si) may be preferentially grown and filled in the trench. Since the polysilicon inside the trench is not a current path, it is not necessary to completely bury it, and it can be buried at a high growth rate by growing from both sides of the trench.
[0066]
Next, the gate electrode 9 is formed on the channel region on the upper surface of the P pillar layer 3 via the gate insulating film 8 , and the N + source region 6 is selectively formed on the surface of the P pillar layer 3. As a result, a DTMOS FET having the N ++ substrate 1 as a drain and the N + pillar layer 4 as a current path between the N + source region 6 and the drain is obtained.
[0067]
That is, according to the method of manufacturing the DTMOS FET of the above embodiment, a trench having a depth reaching the substrate from the epilayer surface, a wider opening than the bottom, and a tapered surface with a rounded periphery at the opening. The N pillar layer 4 along the vertical direction on the side wall of the trench and the P pillar layer adjacent thereto along the vertical direction are formed by ion implantation of the P type impurity and the N type impurity into the trench side wall and performing thermal diffusion. Form 3
[0068]
By such a process, it is possible to form the P pillar layer 3 in which the impurity concentration distribution in the depth direction from the surface gradually changes from the surface to a predetermined depth position. At this time, it is possible to form a portion with a high impurity concentration (P base layer) on the upper surface of the P pillar layer 3 at the same time, thereby reducing the number of steps for forming the P base layer later. However, it goes without saying that the P base layer forming step may be performed later.
[0069]
In the above description, a method for manufacturing an N-type DTMOS FET has been described. However, the present invention can also be applied to a method for manufacturing a P-type DTMOSFET.
[0070]
<Second Embodiment>
In the first embodiment, a rounded taper surface is provided at the periphery of the trench opening of the DTMOS FET. By adopting the structure having the impurity concentration distribution as shown in 2 (second embodiment), the same effect as described above can be obtained.
[0071]
<Third Embodiment>
Second Embodiment In the first embodiment, a DTMOS FET is shown. However, even in a planar-structure MOS FET, the P base region has the impurity concentration distribution as shown in FIG. It can be easily guessed that the same effect as described above can be obtained by adopting the embodiment.
[0072]
【The invention's effect】
As described above, according to the present invention, a semiconductor device capable of preventing a concentration of an electric field in the base region under the source region, stably securing a higher reverse breakdown voltage between the drain and the source, and realizing a MOS FET having a low on-resistance. A manufacturing method thereof can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a part of the structure of a DTMOS FET according to a first embodiment of the present invention.
2 is a diagram showing an example of an impurity concentration distribution in a vertical section (BB ′ line) in a P + pillar layer of the DTMOS FET shown in FIG. 1;
FIG. 3 is a graph showing an example of the result of verifying the reverse breakdown voltage between the drain and source by simulation using the P base depth of the DTMOS FET shown in FIG. 1 as a parameter;
4 is a cross-sectional view showing a half of a unit element (cell) as an example of a manufacturing process of the DTMOS FET shown in FIG.
FIG. 5 is a cross-sectional view showing a part of a conventional planar structure power MOS FET.
FIG. 6 is a cross-sectional view showing a part of a conventional super-junction power MOS FET.
FIG. 7 is a cross-sectional view showing a part of the basic structure of a DTMOS FET currently being proposed.
8 is a perspective view showing a part of a planar pattern and a cross-sectional structure of a stripe pattern type DTMOS FET as an example of the DTMOS FET shown in FIG. 7;
9 is a perspective view showing a part of a planar pattern and a sectional structure of an offset mesh type DTMOS FET as another example of the DTMOS FET shown in FIG. 7;
10 is a cross-sectional view showing an example of the structure of a DTMOS FET according to an improvement example of the structure shown in FIGS. 7 to 9. FIG.
11 is a cross-sectional view showing an example of the structure of a DTMOS FET according to an improvement example of the structure of the insulator 85 inside the trench shown in FIGS. 7 to 9. FIG.
12 is a cross-sectional view showing a part of the structure of the DTMOS FET in order to schematically explain a part of the manufacturing process of the DTMOS FET shown in FIG. 7;
[Explanation of symbols]
1… N ++ board,
2… N-epi layer,
3… P + pillar layer,
4… N + pillar layer,
5… insulator layer,
6… N + source region,
7 … P + base region,
8 … Gate insulation film,
9 : Gate electrode .

Claims (15)

A semiconductor substrate having a low resistance epilayer;
A trench having a depth reaching the semiconductor substrate from the surface of the low-resistance epilayer, having a wider opening than the bottom, and a tapered surface having a rounded periphery at the opening;
The first conductivity type impurity and the second conductivity type impurity are ion-implanted from the sidewall of the trench into the low resistance epilayer and formed by thermal diffusion, and are formed in the vertical direction along the opposing sidewall surfaces of adjacent trenches. A second conductivity type pillar layer and a first conductivity type pillar layer formed vertically adjacent to and sandwiched between them,
An insulator embedded in the trench;
A second conductivity type source region selectively formed on a surface of the first conductivity type pillar layer;
A gate electrode formed on a channel region between the second conductivity type source region and the second conductivity type pillar layer via a gate insulating film;
Forming a MOS FET having the first conductivity type pillar layer as a base, the second conductivity type pillar layer as a current path, and the semiconductor substrate as a drain;
Wherein a gradient of the concentration distribution is in a certain concentration is near zero at the surface from 4.0 [mu] m or more depth position of the first conductive type pillar layer. Dose of ion implantation of the first conductivity type impurity is controlled by a tapered surface having a rounded opening edge, the impurity concentration in the depth direction from the surface of the first conductive type pillar layer first conductivity type the semiconductor device according to claim 1, characterized in that it decreases with a predetermined depth position until in depth from the surface of the pillar layer.   3. The semiconductor device according to claim 1, wherein an upper surface portion of the first conductivity type pillar layer is a base region having a high first conductivity type impurity concentration.   The total amount of (second conductivity type impurity amount−first conductivity type impurity amount) in the second conductivity type pillar layer and (first conductivity type impurity amount−second conductivity type impurity amount) in the first conductivity type pillar layer. 4. The semiconductor device according to claim 1, wherein the semiconductor device is set to have a difference within ± 5% with respect to the total amount. 5. A second conductivity type region having the same impurity concentration as that of the source region of the second conductivity type is selectively formed in a part of the upper surface of the second conductivity type pillar layer that continues to the trench sidewall. The semiconductor device according to any one of claims 1 to 4. 2. The semiconductor substrate having the low resistance epitaxial layer is an N + substrate having an N-epi layer, wherein the first conductivity type impurity is B and the second conductivity type impurity is As. 6. The semiconductor device according to any one of 5 above. The insulator embedded in the trench is
7. The semiconductor device according to claim 1, wherein polysilicon is embedded in an inner wall of the trench via a SiO ₂ film or a Si ₃ N ₄ film. The semiconductor device according to claim 1, wherein the gate insulating film is made of SiO ₂ , and the gate electrode is made of polysilicon or metal silicide. A trench having a depth reaching the semiconductor substrate from the surface of the low-resistance epilayer of the semiconductor substrate having a low-resistance epilayer, having an opening wider than the bottom, and a rounded tapered surface at the periphery of the opening Forming, and
The first conductivity type impurity and the second conductivity type impurity are ion-implanted into the sidewall of the trench and thermal diffusion is performed, thereby utilizing the difference in the diffusion coefficient between the first conductivity type impurity and the second conductivity type impurity to the trench side. the first conductive second conductive type pillar layer along the longitudinal direction and the impurity concentration in the depth direction from the surface with an adjacent it along the longitudinal direction decreases with a predetermined depth position until in depth from the front surface to the wall surface Forming a mold pillar layer; and
Flattening the surface after embedding an insulator inside the trench;
A second conductivity type source region is selectively formed on an upper surface of the first conductivity type pillar layer, and a gate insulating film is formed on a channel region between the second conductivity type source region and the second conductivity type pillar layer. Forming a gate electrode through
A method of manufacturing a semiconductor device, comprising: forming a MOS FET using the semiconductor substrate as a drain and using the second conductivity type pillar layer as a current path between the drain and the source region of the second conductivity type.   10. The impurity concentration distribution is realized by controlling a dose amount of the ion implantation of the first conductivity type impurity by a tapered surface having a rounded periphery of the opening at the time of the ion implantation. A method for manufacturing a semiconductor device.   During the ion implantation, the dose of ion implantation of the first conductivity type impurity is increased on the upper surface portion of the first conductivity type pillar layer, and the second conductivity type base is formed on the upper surface portion of the first conductivity type pillar layer by the diffusion. The method of manufacturing a semiconductor device according to claim 10, wherein a region is formed.   12. The method of manufacturing a semiconductor device according to claim 9, wherein the planarizing step uses CMP or etching. 10. The semiconductor substrate having the low resistance epitaxial layer is an N + substrate having an N-epi layer, wherein the first conductivity type impurity is B and the second conductivity type impurity is As. 13. A method for manufacturing a semiconductor device according to any one of 12 above. When embedding an insulator inside the trench,
After forming the Si0 ₂ film or the Si ₃ N ₄ film on the inner wall of the trench, the method of manufacturing a semiconductor device according to any one of claims 9 to 13, wherein the growing the polysilicon in the trench . The gate insulating layer is SiO _2, the gate electrode manufacturing method of a semiconductor device according to any one of claims 9 to 14, wherein the polysilicon or metal silicide.

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