JP2011018694A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress gate input capacitances of trench gate electrodes from changing to negative capacitance in vertical IGBTs which includes trench-type gates.SOLUTION: The IGBT100 includes an emitter region 8, a body region 12 and a drift region 19. The body region 12 abuts on the emitter region 8. The drift region 19 is separated from the emitter region 8 by the body region 12. The drift region 19 includes a heavily-doped region 14 thickly including impurities, and a lightly-doped region 18, including impurities as compared with the heavily-doped region 14. At least one portion of the heavily-doped region 14 abuts against the trench-type gate 5, and at least one portion of the lightly-doped region abuts against the body region 12.

Description

  The present invention relates to a vertical IGBT having a trench gate.

  A vertical IGBT (Insulated Gate Bipolar Transistor) having a trench-type gate has been developed, and an example thereof is disclosed in Patent Document 1. When the IGBT is turned on, electrons are injected from the n-type emitter region into the n-type drift region (also referred to as the n-type base) through the channel formed in the p-type body (also referred to as the p-type base), and the p-type collector. Holes are injected from the region into the n-type drift region.

JP 11-274484 A

  When the IGBT is on, a positive voltage is applied to the trench gate electrode of the trench type gate, so that electrons accumulate around the trench type gate. For this reason, the holes injected into the n-type drift region are also attracted to the electrons and accumulated around the trench gate. When holes are accumulated around the trench type gate, negative charges are induced in the trench gate electrode of the trench type gate, and the gate input capacitance of the trench type gate becomes small (negative capacitance). When the gate input capacitance of the trench gate becomes negative, the voltage applied to the trench gate electrode of the trench gate may be disturbed, or an excessive current may flow through the IGBT. The technology disclosed in this specification is intended to suppress negative gate input capacitance of a trench-type gate.

  The technology disclosed in this specification suppresses the gate input capacitance of the trench gate from becoming negative by suppressing the amount of holes accumulated around the trench gate when the IGBT is on. It is characterized by doing. In order to suppress the amount of holes accumulated around the trench-type gate, the technology disclosed in this specification includes a high-concentration region containing impurities in the drift region and a low concentration containing impurities thinner than the high-concentration regions. A region is provided, and at least part of the high concentration region is in contact with the trench gate, and at least part of the low concentration region is in contact with the body region. The holes injected into the drift region move from the low concentration region into the body region while avoiding the high concentration region. As a result, the amount of holes accumulated around the trench gate is reduced, and the gate input capacitance of the trench gate is stabilized.

  The technology disclosed in this specification can be embodied in a vertical IGBT having a trench gate. The IGBT includes a first conductivity type emitter region, a second conductivity type body region, and a first conductivity type drift region. The body region is in contact with the emitter region. The drift region is separated from the emitter region by the body region, and has a high concentration region containing the first conductivity type impurity deeply and a low concentration region containing the first conductivity type impurity thinner than the high concentration region. In this IGBT, at least a part of the high concentration region is in contact with the trench gate, and at least a part of the low concentration region is in contact with the body region. In the vertical IGBT, holes injected from the collector region into the drift region pass through the body region and move to the emitter region. In the drift region, holes are more likely to move in a low concentration region where the n-type impurity concentration is lower than in the high concentration region where the n-type impurity concentration is high. For this reason, if the technique disclosed in this specification is used, it is possible to make it difficult to move holes around the trench gate electrode. Since holes are less likely to be accumulated around the trench gate electrode, negative capacitance of the gate input capacitance of the trench gate can be suppressed.

  In the semiconductor device disclosed in this specification, the high-concentration region is preferably in contact with at least part of the bottom surface of the trench gate. In a vertical IGBT having a trench gate, the bottom surface of the trench gate faces the collector region. Therefore, holes injected from the collector region are most likely to accumulate on the bottom surface of the trench gate. By suppressing the accumulation of holes on the bottom surface of the trench type gate, the negative input capacitance of the trench type gate can be remarkably suppressed.

  In the semiconductor device disclosed in this specification, the high concentration region is preferably provided in the entire region where the drift region is in contact with the trench gate. That is, it is preferable that the high concentration region is in contact with all of the side surface of the trench gate located in the drift region and the bottom surface of the trench gate. According to the IGBT of this aspect, the corner between the bottom surface and the side surface of the trench gate is covered with the high concentration region. For this reason, according to the IGBT of this aspect, in addition to the negative capacitance of the gate input capacitance, the electric field concentration at the corner is also reduced, so that the breakdown tolerance of the trench gate can be improved.

  The technology disclosed in this specification can suppress the negative capacitance of the gate input capacitance of the trench gate in a vertical IGBT having a trench gate.

FIG. 3 is a cross-sectional view of main parts of the semiconductor device of Example 1; FIG. 5 is a cross-sectional view of a principal part of a semiconductor device of Example 2. The relationship between the density | concentration of a high concentration area | region and the proof pressure of a semiconductor device is shown. The change of the collector current after applying a voltage to a trench gate electrode is shown. The relationship between the impurity concentration of the n-type floating region and the change rate of the collector current is shown.

Some features of the embodiment are listed.
(First Feature) An n-type floating region is provided in the p-type body region.
(Second Feature) A contact region containing a higher concentration of p-type impurities than the p-type body region is provided in the p-type body region.
(Third feature) The concentration of the n-type impurity in the high concentration region is preferably 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less.

  Embodiments will be described below with reference to the drawings. In the following embodiments, a semiconductor device using silicon as a material for a semiconductor substrate will be described as an example. However, the techniques disclosed in the following embodiments can also be applied to semiconductor devices using other semiconductor materials. For example, the technology disclosed in the following embodiments can be applied to a semiconductor device using a compound semiconductor such as gallium nitride, silicon carbide, or gallium arsenide.

  FIG. 1 is a cross-sectional view of a main part of the IGBT 100. The IGBT 100 is a vertical semiconductor device having a trench type gate 5. When the IGBT 100 is viewed in plan, the trench type gate 5 extends in a stripe shape. The “trench gate 5” means a structure in which the trench gate electrode 6 and the gate insulating film 4 are combined. In FIG. 1, the emitter electrode provided on the front surface of the semiconductor substrate 2 and the collector electrode provided on the back surface of the semiconductor substrate 2 are omitted. Hereinafter, the IGBT 100 will be described in order from the back surface.

A p ⁺ -type collector region 22 is provided on the back side of the silicon single crystal semiconductor substrate 2. The collector region 22 is electrically connected to a collector electrode (not shown). The collector electrode is connected to the high potential side of the power source. The collector region 22 is formed by ion implantation of p-type impurities from the back surface of the semiconductor substrate 2. The impurity concentration of the collector region 22 is approximately 1 × 10 ¹⁸ cm ⁻³ on the back surface side of the semiconductor substrate 2. The thickness of the collector region 22 is approximately 0.5 μm. On the surface of the collector region 22, an n ⁺ type buffer region 20 is provided. The buffer region 20 is formed by ion-implanting n-type impurities from the back surface of the semiconductor substrate 2. The impurity concentration of the buffer region 20 is approximately 2 × 10 ¹⁷ cm ⁻³ at the interface between the buffer region 20 and the collector region 22. The thickness of the buffer region 20 is approximately 0.5 μm.

  An n-type drift region 19 is provided on the surface of the buffer region 20. The drift region 19 has a high concentration region 14 and a low concentration region 18. The thickness of the drift region 19 is approximately 130 μm. The IGBT 100 of the present embodiment is a non-punch through (NPT) type, but the technology disclosed in the present embodiment can also be applied to a punch through (PT) type IGBT. In the case of a punch-through (PT) type IGBT, the buffer region 20 is omitted, and the drift region 19 is provided on the surface of the collector region 22.

A p-type body region 12 is provided on the surface of the drift region 19. Body region 12 is formed by ion-implanting p-type impurities from the surface of semiconductor substrate 2. The impurity concentration of the body region 12 is approximately 2 × 10 ¹⁷ cm ⁻³ on the surface side of the semiconductor substrate 2. The thickness of the body region 12 is approximately 4.5 μm. An n ⁺ type floating region 16 is provided in the body region 12. The floating region 16 is formed by ion-implanting n-type impurities from the surface of the semiconductor substrate 2. The floating region 16 extends between the opposing trench gates 5. The body region 12 is divided by the floating region 16 into an upper body region 12a and a lower body region 12b. The impurity concentration of the floating region 16 is approximately 4 × 10 ¹⁶ cm ⁻³ and the thickness is approximately 0.5 μm. The floating region 16 is provided in an intermediate portion of the body region 12. Therefore, the thicknesses of the upper body region 12a and the lower body region 12b are approximately 2.0 μm, respectively. The impurity concentration of the lower body region 12b is approximately 1 × 10 ¹⁶ at the interface between the lower body region 12b and the floating region. The floating region 16 is separated from the drift region 18 by the lower body region 12b. The floating region 16 is also separated from the emitter region 8 described later by the upper body region 12a.

An n ⁺ -type emitter region 8 is provided on the surface side of the semiconductor substrate 2. The emitter region 8 is formed by ion-implanting n-type impurities from the surface of the semiconductor substrate 2. The impurity concentration of the emitter region 8 is approximately 1 × 10 ²⁰ cm ⁻³ on the surface side of the semiconductor substrate 2. The emitter region 8 has a thickness of approximately 0.5 μm. The emitter region 8 is in contact with the upper body region 12 a and the trench type gate 5. Emitter region 8 is separated from drift region 18 by body region 12. Emitter region 8 is also separated from floating region 16 by upper body region 12a. A p ⁺ -type body contact region 10 is provided between the emitter regions 8. Body contact region 10 is formed by ion-implanting p-type impurities from the surface of semiconductor substrate 2. The impurity concentration of the body contact region 10 is approximately 1 × 10 ²⁰ cm ⁻³ on the surface side of the semiconductor substrate 2. The thickness of the body contact region 10 is approximately 0.7 μm. The emitter region 8 and the body contact region 10 are electrically connected to an emitter electrode (not shown). The emitter electrode is grounded.

The trench gate 5 protrudes from the surface of the semiconductor substrate 2 into the drift region 19 through the emitter region 8, the body region 12 (upper body region 12 a and lower body region 12 b), and the floating region 16. The trench gate 5 has a trench gate electrode 6 and a gate insulating film 4. The trench gate electrode 6 faces the emitter region 8, the body region 12 and the drift region 19 with the gate insulating film 4 interposed therebetween. The material of the trench gate electrode 6 is polysilicon. The material of the gate insulating film 4 is silicon oxide (SiO ₂ ). In the drift region 19, the high concentration region 14 is provided on the bottom surface of the trench gate 5. The high-concentration region 14 is formed by forming a trench (not shown) in the surface layer portion of the semiconductor substrate 2 to form the trench-type gate 5 and then ion-implanting n-type impurities toward the bottom surface of the trench. The The impurity concentration on the trench gate 5 side in the high concentration region 14 is approximately 1 × 10 ¹⁵ cm ⁻³ . The thickness T14 of the high concentration region 14 is approximately 1 μm. The low concentration region 18 is a range in which n-type impurities are not ion-implanted into the semiconductor substrate 2. The impurity concentration of the low concentration region 18 is approximately 1 × 10 ¹⁴ cm ⁻³ . Of the drift region 19, the high concentration region 14 is not in contact with the body region 12, and only the low concentration region 18 is in contact with the body region 12.

  The operation of the IGBT 100 will be described. When a positive voltage is applied to the trench gate electrode 6 with a voltage applied between the emitter electrode and the collector electrode, a channel is formed in the body region 12 on the side surface of the trench gate 5. Electrons supplied from the emitter region 8 pass through the channel and are injected into the drift region 18. Further, holes are injected from the collector region 22 into the drift region 18. The holes injected into the drift region 18 recombine with electrons or are discharged from the body contact region 10. An arrow 24 indicates a path along which the holes 26 in the drift region 18 move to the body contact region 10.

  As indicated by an arrow 24, the holes 26 move into the body region 12 so as to avoid the bottom surface of the trench gate 5 where the high concentration region 14 is provided. That is, the holes 26 move from the low concentration region 18 into the body region 12 while avoiding the high concentration region 14. Since the bottom surface of the trench-type gate 5 faces the collector region 22, the holes 26 are most easily accumulated. Since the IGBT 100 is provided with the high concentration region 14, accumulation of holes 26 on the bottom surface of the trench gate 5 can be suppressed. Therefore, the negative capacity of the gate input capacity of the trench gate 5 can be remarkably suppressed. In the IGBT 100, the negative capacitance of the gate input capacitance of the trench gate 5 is suppressed, so that the voltage applied to the trench gate electrode 6 is prevented from being disturbed or excessive current is prevented from flowing.

As described above, in the IGBT 100, the n-type floating region 16 is provided in the p-type body region 12. For this reason, in the IGBT 100, a potential barrier is generated at the interface between the floating region 16 and the body region 12, so that holes 26 can be accumulated in the body region 12. In the IGBT 100, since the holes 26 can be stored in the body region 18, the on-voltage can be reduced. Further, in the IGBT 100, an n ⁺ type high concentration region 14 is provided on the bottom surface of the trench type gate 5. Therefore, even if many holes 26 are accumulated in the element, the amount of holes accumulated around the trench gate 5 can be suppressed. Since the technique of providing the floating region 16 in the body region 12 increases the amount of accumulated holes in the element, negative capacitance is likely to occur. By providing both the floating region 16 and the high concentration region 14, the IGBT 100 can reduce the on-voltage and suppress the negative capacitance of the trench gate.

FIG. 2 shows a cross-sectional view of the main part of the IGBT 200. In the IGBT 200, the high concentration region 214 covers the periphery of the trench gate 5. It can also be said that the trench gate 5 is separated from the low concentration region 218 by the high concentration region 14. In the case of the IGBT 200, the high concentration region 214 is also provided on the side surface of the trench gate 5 in the drift region 219. Therefore, the holes 26 injected into the drift region 219 move into the body region 12 while avoiding not only the bottom surface of the trench gate 5 but also the side surface of the trench gate 5. Accumulation on the side surface of the trench type gate 5 can be more reliably suppressed. The IGBT 200 can significantly suppress the negative capacity of the gate input capacity of the trench gate 5. Further, since the high concentration region 214 covers the periphery of the trench type gate 5, it is possible to suppress the concentration of the electric field at the corner of the trench type gate 5 when the IGBT 200 is turned off. Therefore, the IGBT 100 can also improve the breakdown tolerance of the trench type gate 5. The thickness T214 of the high concentration region 214 provided on the side surface of the trench gate 5 is equal to the thickness of the bottom surface of the trench gate 5 and is approximately 1 μm. The impurity concentration on the trench gate 5 side of the high concentration impurity region 214 is approximately 1 × 10 ¹⁶ cm ⁻³ .

  In the case of the IGBT 200, the high concentration region 214 not only covers the side surface of the trench type gate 5 but also contacts the body region 12. However, the range in which the high concentration region 214 is in contact with the body region 12 is a part of the range in which the drift region 219 and the body region 12 are in contact. In other words, the IGBT 200 has a portion where the low concentration region 218 and the body region 12 are in contact, and a portion where the high concentration region 214 and the body region 12 are in contact. Therefore, the holes 26 moving from the drift region 219 to the body region 12 selectively move at the portion where the low concentration region 218 and the body region 12 are in contact, and hardly move at the portion where the high concentration region 214 and the body region 12 are in contact. . Therefore, accumulation of holes 26 around the trench gate 5 can be suppressed.

(Experimental example 1)
With respect to the IGBT 100 and the IGBT 200, the concentration of the n-type impurity contained in the high concentration regions 14 and 214 was changed, and the device breakdown voltage was measured. In this experiment, the voltage applied to the collector electrode was raised with the IGBTs 100 and 200 turned off, and the voltage when each IGBT was broken was measured. FIG. 3 shows the relationship between the n-type impurity concentration in the high concentration regions 14 and 214 and the element breakdown voltage of the IGBTs 100 and 200. The horizontal axis of the graph represents the concentration (unit: cm ⁻³ ) of the n-type impurity in the high concentration region, and the vertical axis represents the breakdown voltage. A curve 30 indicates the breakdown voltage of the IGBT 100, and a curve 32 indicates the breakdown voltage of the IGBT 200.

As shown by the curve 30, the IGBT 100 can maintain the element breakdown voltage until the concentration of the high concentration region 14 reaches 1.0 × 10 ¹⁵ cm ⁻³ . Further, as indicated by the curve 32, the IGBT 200 can maintain the device breakdown voltage until the concentration of the high concentration region 214 reaches 1.0 × 10 ¹⁶ cm ⁻³ . This result indicates that if the high concentration region covers the periphery of the trench type gate 5, the electric field applied to the corner of the trench type gate 5 can be relaxed and the device breakdown voltage can be improved. In both IGBTs 100 and 200, when the impurity concentration of the high concentration regions 14 and 214 becomes too high, the breakdown voltage tends to be lowered. These results indicate that if the impurity concentration of the high concentration regions 14 and 214 becomes too high, a high electric field is applied to the trench gate 5 and the gate insulating film 4 is destroyed. Therefore, in the case of the IGBT 100, the impurity concentration of the high concentration region 14 is preferably 1.0 × 10 ¹⁵ cm ⁻³ or less, and in the case of the IGBT 200, the impurity concentration of the high concentration region 214 is 1.0 × 10 ¹⁶ cm ^−. It is preferable that it is ³ or less.

However, if the concentration of the n-type impurity in the high-concentration regions 14 and 214 is too low, it is difficult to obtain the effect of suppressing the amount of holes 26 accumulated around the trench gate 5. Therefore, the impurity concentration of the high concentration regions 14 and 214 is preferably 1.0 × 10 ¹⁵ cm ⁻³ or more and 1.0 × 10 ¹⁶ cm ⁻³ or less. As described above, the impurity concentration of the low-concentration regions 18 and 218 is approximately 1 × 10 ¹⁴ cm ⁻³ . Therefore, if the concentration of the n-type impurity in the high-concentration regions 14 and 214 is 10 times or more that of the low-concentration regions 18 and 218, the accumulation of the holes 26 around the trench gate 5 is sufficiently suppressed. Can do.

(Experimental example 2)
With respect to the IGBT 200, an elapsed time after starting to apply a voltage to the trench gate electrode 6 and a current flowing through the IGBT 200 (hereinafter referred to as a collector current) were measured. Moreover, the same measurement was performed also about IGBT which does not have the high concentration area | region 214 (conventional IGBT: Comparative Example 1). The results are shown in FIG. The horizontal axis of the graph represents the elapsed time from the start of applying a voltage to the gate electrode, and the vertical axis represents the collector current. A curve 34 represents the collector current of the IGBT 200, and a curve 36 represents the collector current of Comparative Example 1.

  As shown by a curve 36, in the conventional IGBT, an excessive collector current flows immediately after being turned on. Further, in the conventional IGBT, the collector current is disturbed. This result shows that the gate input capacitance of the trench type gate becomes a negative capacitance, and the voltage between the gate and the emitter is greatly disturbed. If an excessive collector current flows through the IGBT, the IGBT may be destroyed. On the other hand, as shown by a curve 34, the IGBT 200 does not flow excessive collector current immediately after being turned on, as compared with the conventional IGBT. Also, the collector current is hardly disturbed. This result indicates that the amount of the holes 26 accumulated around the trench gate 5 is suppressed by the high concentration region 214. That is, the IGBT 200 can remarkably suppress the negative capacity of the gate input capacity of the trench gate 5 as compared with the conventional IGBT.

(Experimental example 3)
As shown in FIG. 4, immediately after the IGBT is turned on, the slope of the curve 36 is larger than the slope of the curve 34. The slopes of the curves 36 and 34 correspond to a value obtained by differentiating the collector current with respect to time (change rate of the collector current). As described above, the conventional IGBT (the rate of change of the collector current is larger than that of the IGBT 200) is more likely to have a negative gate input capacitance than the IGBT 200. Therefore, the rate of change of the collector current can be used as an index for making the gate input capacitance negative. In this experimental example, using the change rate of the collector current as an index, the IGBT 200, the IGBT not having the high concentration region 214 (conventional IGBT: Comparative Example 2), and the n-type impurity in the high concentration region 214 are p-type impurities. For the IGBT (Comparative Example 3) replaced with, the easiness of making the gate input capacitance negative was compared.

  In this experimental example, the concentration of the n-type impurity contained in the floating layer 16 was changed, and the change rate of the collector current was measured. FIG. 5 shows the relationship between the impurity concentration of the floating layer 16 and the change rate of the collector current. The horizontal axis of the graph indicates the concentration of the floating layer 16, and the vertical axis indicates the change rate of the collector current. A curve 40 shows the change rate of the collector current of the IGBT 200, a curve 42 shows the change rate of the collector current of Comparative Example 2, and a curve 44 shows the change rate of the collector current of Comparative Example 3.

  As shown in FIG. 5, when the impurity concentration of the floating layer 16 increases, the change rate of the collector current increases. However, as shown by curves 40 and 42, even if the impurity concentration of the floating layer 16 is the same, the IGBT 200 has a smaller change rate of the collector current than the conventional IGBT. In particular, as the impurity concentration of the floating layer 16 increases, the difference in the change rate of the collector current increases. The difference between the curve 40 and the curve 42 corresponds to the difference in the likelihood of the gate input capacitance becoming negative capacitance. Further, as shown by curves 42 and 44, when the n-type impurity in the high concentration region 214 is replaced with a p-type impurity, the change rate of the collector current becomes larger than that of the conventional IGBT. The IGBT of Comparative Example 3 is more likely to have a negative gate input capacitance than the conventional IGBT. In the IGBT of Comparative Example 3, holes are more easily accumulated around the trench gate 5 than in the conventional IGBT. That is, when p-type impurities are provided around the trench gate 5, holes are likely to be accumulated around the trench gate 5 and the gate input capacitance is likely to be negative.

  As the impurity concentration of the floating layer 16 is increased, the amount of holes accumulated in the body region 12 can be increased. For this reason, in both the curves 40, 42 and 44, when the impurity concentration of the floating layer 16 increases, the change rate of the collector current increases. The technology disclosed in this specification can suppress the amount of holes accumulated around the trench gate 5 even when the concentration of the floating layer 16 is increased.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

5: Trench type gate 8: Emitter region 12: Body region 14, 214: High concentration region 18, 218: Low concentration region 19: Drift region 100, 200: IGBT (semiconductor device)

Claims (3)

A vertical IGBT having a trench-type gate,
An emitter region of a first conductivity type;
A body region of a second conductivity type in contact with the emitter region;
A drift region that is separated from the emitter region by the body region, and that has a high concentration region that contains the first conductivity type impurity deeply, and a low concentration region that contains the first conductivity type impurity thinner than the high concentration region; , And
A semiconductor device in which at least a part of the high concentration region is in contact with the trench gate, and at least a part of the low concentration region is in contact with the body region.   The semiconductor device according to claim 1, wherein the high concentration region is in contact with at least a part of a bottom surface of the trench gate.   The semiconductor device according to claim 2, wherein the high concentration region is provided in an entire region where the drift region and the trench gate are in contact with each other.

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