JP4830877B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a semiconductor equipment manufacturing method which includes a transistor of the plurality (third plurality in this specification). In particular, a method of manufacturing a semiconductor equipment the third plurality of transistors are connected in parallel.

A semiconductor device typified by a MOS or IGBT is often used for switching on and off of a current. In order to switch a large current, a plurality of transistors are often connected in parallel. The “semiconductor device” in this specification refers to a device in which a plurality of transistors are connected in parallel and a current that cannot be switched by one transistor is switched. Such a semiconductor device is sometimes called a power transistor.
In a power transistor, it is preferable that a uniform current flows through each of the plurality of transistors when the transistor is turned on. This is because each transistor has a low tolerance, so that if an excessive current flows through a specific transistor, the transistor may be destroyed. If one or several transistors are destroyed, the power transistor itself may be destroyed.
An event in which current concentrates on a specific transistor among a plurality of transistors connected in parallel occurs when the ON resistance of the specific transistor is lower than the ON resistances of other transistors. Even if a plurality of transistors are formed in the same semiconductor substrate due to manufacturing errors of the semiconductor device, it is inevitable that the on-resistance of the transistors varies from transistor to transistor.

  Patent Document 1 discloses a semiconductor device capable of suppressing current from being concentrated on a transistor having an on-resistance smaller than that of other transistors. In this semiconductor device, a plurality of transistors are divided into a plurality of transistor blocks each having a plurality of transistors. That is, the collector electrode is a collector electrode commonly connected to all the transistors, while the emitter electrode is a divided electrode divided for each transistor block. The divided electrodes divided for each transistor block are commonly connected to the transistors in the transistor block. In Patent Document 1, each divided electrode divided for each transistor block is grounded with a bonding wire having an inductance component.

In the prior art of Patent Document 1, the emitter electrode is also shared. For this reason, the current flowing through each transistor is directly inversely proportional to the on-resistance of each transistor, and the variation in the on-resistance of each transistor is directly the variation in the magnitude of the energization current.
In the technique of Patent Document 1, a bonding wire that connects an emitter electrode and a ground point is divided for each transistor block. For this reason, the current flowing through each transistor block is not directly inversely proportional to the on-resistance of each transistor block, but is inversely proportional to the impedance of the entire circuit connecting the collector electrode and the ground point. In the technique of Patent Document 1, the impedance of the entire circuit connecting the collector electrode and the ground point is obtained by adding the impedance of the bonding wire that grounds the emitter electrode of each transistor block to the on-resistance of each transistor block. . In the technique of Patent Document 1, since it is used in a high frequency region, the impedance of the bonding wire is remarkably higher than the on-resistance of each transistor block. In the technique of Patent Document 1, each emitter block divided for each transistor block is grounded with a bonding wire to reduce the influence of variation due to the on-resistance of each transistor block, and the current flowing through each transistor block is reduced. Reduce variation.

This can be described mathematically as follows. In the prior art of Patent Document 1, when the on-resistance R1 of the first transistor is set to the on-resistance R2 of the second transistor, a current of 1 / R1 flows through the first transistor, and 1 / R1 flows through the second transistor. R2 current flows. If the on-resistances R1 and R2 vary, the magnitude of the energization current also varies.
In the technique of Patent Document 1, when the impedance of each bonding wire is Z, a current of 1 / (R1 + Z) flows through the first transistor block, and a current of 1 / (R2 + Z) flows through the second transistor block. Flowing. Here, since R1 and R2 are smaller than Z, even if the on-resistances R1 and R2 vary, the variation in energization current can be suppressed to a small value.
The semiconductor device of Patent Document 1 is based on the principle that, when the impedance Z of the bonding wire having a large value compared to the on-resistance R of the transistor is used, the variation in energization current can be suppressed to be small. Connect with bonding wires with common characteristics. It should be noted that the type of bonding wire used is not changed by the divided emitter electrodes.

JP 2003-17946 A

Since the semiconductor device of Patent Document 1 is scheduled to be used in a high frequency region, the inductance component of the bonding wire can be used. When the switching frequency is slow, when trying to use the technique of Patent Document 1, the emitter electrode divided for each transistor block is grounded with a high-resistance bonding wire. However, in the case of a power transistor, there is a strong demand to suppress resistance, suppress heat generation, and reduce wasteful energy consumption, and high resistance bonding wires cannot be used.
For a power transistor that cannot use a bonding wire having a resistance larger than the on-resistance of the transistor, there is a need for a technique that can suppress the variation in energization current against the non-uniformity of the on-resistance of each transistor.

  In the present invention, the resistance of the bonding wire connected to the transistor is positively changed in order to prevent the on-resistance of the transistor from varying between the transistors and the current from being concentrated in the transistor having a low on-resistance as it is. It is completely different from the technique of Patent Document 1 in that the resistance of the bonding wire is positively changed. As described above, the semiconductor device of Patent Document 1 is based on the principle that the variation of the conduction current is suppressed by using the impedance Z having a larger value than the on-resistance R of the transistor. It should be noted that the idea is not to change the type of bonding wire for each electrode.

  A normal power transistor includes a very large number of transistors, and it is not practical to connect a bonding wire to each transistor. Therefore, in the present invention, a very large number of transistors are divided into a plurality of (second plurality in the present specification) transistor blocks, and at the same time, the resistance of the bonding wire connected to each transistor block is positively changed. Bonding wires with high resistance are connected to transistor blocks with low on-resistance, and bonding wires with low resistance are connected to transistor blocks with high on-resistance. Then, the substantial resistance that determines the current flowing through each transistor block is made uniform for all the transistor blocks, and it is possible to effectively suppress the current from flowing intensively to a specific transistor block.

  Also according to the present invention, the magnitude of the energization current cannot be avoided between a plurality of (first plurality of transistors referred to in this specification) transistors present in the same transistor block. However, for example, compared to the magnitude of the variation in the energization current that occurs when 1000 transistors are simply connected in parallel, the energization current that is generated when the transistor is divided into 10 transistor blocks including 100 transistors. The magnitude of variation is small. This is because the magnitude of the variation in the energization current generated in the 100 transistors is smaller than the magnitude of the variation in the energization current generated in the 1000 transistors.

The semiconductor device of the present invention includes a second plurality of transistor blocks, and each transistor block includes a first plurality of transistors. The entire semiconductor device includes a third plurality of transistors. The third plurality is a product of the first plurality and the second plurality.
The transistor may be unipolar or bipolar. In the case of a unipolar transistor, a third plurality of transistor structures each having a “source region and a drain region” are formed in a semiconductor substrate. In the case of a bipolar transistor, a third plurality of transistor structures each having an “emitter region or collector region” are formed in a semiconductor substrate. Since the transistor of the present invention may be unipolar or bipolar, it has a third plurality of transistor structures each having “emitter region and collector region” or “source region and drain region”. It can be said that it has. A third plurality of transistor structures are formed in the semiconductor substrate.
In the semiconductor device of the present invention, one of the main electrodes is common to all transistor structures. The common main electrode may be the source electrode of the unipolar transistor, the drain electrode of the unipolar transistor, the emitter electrode of the bipolar transistor, or the collector electrode of the bipolar transistor. Also good.
In the semiconductor device of the present invention, the other main electrode is divided corresponding to the transistor block. The split electrode is a pair of electrodes with the common electrode. If the common electrode is the source electrode of the unipolar transistor, the drain electrode is split. If the common electrode is the drain electrode of the unipolar transistor, the source electrode is split. If the common electrode is the emitter electrode of the bipolar transistor, the collector electrode is divided, and if the common electrode is the collector electrode of the bipolar transistor, the emitter electrode is divided. Each divided electrode is commonly connected to the transistor structure in the corresponding transistor block.
From the above, the semiconductor device of the present invention includes a common electrode commonly connected to one of the “emitter region or source region” and the “collector region or drain region” of the third plurality of transistor structures, and the transistor block. The first plurality of transistor structures have a divided electrode that is commonly connected to the other of the “emitter region or source region” and the “collector region or drain region” and is divided for each transistor block. It can be expressed as
The semiconductor device of the present invention includes a common lead electrode and a second plurality of bonding wires connecting the second plurality of divided electrodes and the common lead electrode. In the semiconductor device of the present invention, a bonding wire having a low resistance value is used for a transistor block having a high on-resistance between the common electrode and the divided electrode, and a resistance block is used for a transistor block having a low on-resistance between the common electrode and the divided electrode. High value bonding wires are used. Note that the bonding wire here may be a simple bonding wire or a bonding wire into which a resistance element is inserted.

A typical power transistor includes a large number of transistors ranging from several hundred to several hundred thousand, for example, and it is not practical to connect a bonding wire to each transistor. However, one of the main electrodes of the power transistor can be divided into a plurality of pieces, and a bonding wire can be connected to each of the divided electrodes.
In the semiconductor device of the present invention, a bonding wire having a low resistance value is used for a transistor block having a high on-resistance between the common electrode and the divided electrode, and a resistance block is used for a transistor block having a low on-resistance between the common electrode and the divided electrode. Since high-value bonding wires are used, the substantial resistance that determines the magnitude of the current flowing through each transistor block is made uniform for all transistor blocks, and the current concentrates on a specific transistor block. Can be effectively suppressed.

  Even in the semiconductor device of the present invention, the magnitude of the energization current varies between transistors belonging to the same transistor block. However, in a transistor block including many transistors with low on-resistance, a bonding wire with high resistance is used, so that the average conduction current per transistor is lower than that of other transistor blocks, and the transistor has low on-resistance. The current flowing through the battery does not increase so much. The magnitude of variation in energization current that occurs between transistors belonging to the same transistor block is also suppressed, and further, the magnitude of variation in energization current that occurs between the plurality of third transistors is also suppressed.

The variation in the total resistance value obtained by adding the resistance value of the bonding wire to the on resistance between the common electrode and the divided electrode is smaller than the variation between the transistor blocks in the on resistance between the common electrode and the divided electrode. Is preferred.
The total resistance value obtained by adding the resistance value of the bonding wire to the ON resistance between the common electrode and the divided electrode is a substantial resistance that determines the magnitude of the current flowing through each transistor block. If the relationship that the variation between the transistor blocks of the total resistance value is smaller than the variation between the transistor blocks of the on-resistance by adjusting the resistance value of the bonding wire is obtained, the magnitude of the current flowing through the transistor block It is possible to effectively suppress variations in the length of each transistor block.

The present invention comprises a second plurality of transistor blocks, each comprising a first plurality of transistors, comprising a third plurality of transistors equal to the product of the first plurality and the second plurality. The present invention can also be embodied in a semiconductor device manufacturing method.
The manufacturing method includes a step of forming a third plurality of transistor structures each having an “emitter region and a collector region” or a “source region and a drain region” in a semiconductor substrate; Forming a common electrode commonly connected to one of the "emitter region or source region" and "collector region or drain region" of the transistor structure; and "emitters of the first plurality of transistor structures in the transistor block" A step of forming a divided electrode that is commonly connected to the other of the `` region or source region '' and the `` collector region or drain region '' and is divided for each transistor block; and a step of forming a common lead electrode; Measuring the on-resistance between the common electrode and the divided electrode for each transistor block, and the transistor block having a high on-resistance. And connecting the common lead electrode and the divided electrode with a bonding wire having a low resistance value, and connecting the common lead electrode and the divided electrode with a bonding wire having a high resistance value to the transistor block having a low on-resistance. Yes.

A typical power transistor includes a large number of transistors ranging from several hundred to several hundred thousand, for example, and it is not practical to connect a bonding wire to each transistor. However, one of the main electrodes of the power transistor is divided into a plurality of pieces, the on-resistance of each of the divided electrodes divided into a plurality of pieces is measured, and a bonding wire is individually applied to each of the divided electrodes divided into a plurality of pieces. You can connect.
In the manufacturing method of the present invention, the on-resistance of each transistor block is measured. Further, the divided electrode of the transistor block and the common lead electrode are connected by a bonding wire having a resistance value corresponding to the measured resistance. Specifically, the smaller the measured on-resistance is, the larger the resistance value is connected by a bonding wire. By doing so, the magnitude of the current flowing through each transistor block can be made uniform.

"Step of connecting" above, determined Me a resistance difference by subtracting the on-resistance measured every transistor blocks from a predetermined resistance value, from among the plurality of types of bonding wires having different resistance values were determined Me Selecting a bonding wire having a resistance value closest to the resistance difference . Alternatively includes selecting at least one of a thickness and length and the number of bonding wires to select the bonding wire results in a substantially equal resistance value determined Me was resistance difference process.

  With the above steps, the substantial resistance that determines the magnitude of the current flowing through each transistor block, that is, the total resistance value of the on-resistance and bonding wire resistance for each transistor block is the same for all transistor blocks. It is possible to effectively suppress the current from flowing intensively to a specific transistor block.

  According to the present invention, in the semiconductor device in which the third plurality of transistors are connected in parallel, current concentration to a specific transistor is suppressed, and the magnitude of the current flowing through each transistor is reduced with respect to all the transistors. Can be made uniform.

A semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a schematic perspective view of the semiconductor device 100. The semiconductor device 100 includes a semiconductor substrate 10 and a frame 12 that fixes the semiconductor substrate 10. The semiconductor substrate 10 and the frame 12 are molded or soldered with a resin or the like, but the mold is not shown in FIG.
As will be described later with reference to FIG. 3, twelve IGBTs (bipolar transistors) are formed in the semiconductor substrate 10. Four emitter electrodes 14 a, 14 b, 14 c, 14 d and a gate pad 16 are formed on the upper surface of the semiconductor substrate 10. A collector electrode 34 (see FIG. 2) is formed on the lower surface of the semiconductor substrate 10. As will be described later with reference to FIG. 3, the emitter electrode 14a is conducted to three emitter regions of the 12 IGBTs, and the emitter electrode 14b is conducted to the other three emitter regions. The emitter electrode 14c is further conducted to the other three emitter regions, and the emitter electrode 14d is conducted to the remaining three emitter regions. In the semiconductor device of FIG. 1, twelve IGBTs are divided into four transistor blocks each having three IGBTs.

A first lead electrode 20, a second lead electrode 22, and a third lead electrode 24 are formed on the frame 12. The four emitter electrodes 14a, 14b, 14c, and 14d are individually connected to the first lead electrode 20 by bonding wires 26a, 26b, 26c, and 26d, respectively. The gate pad 16 is connected to the second lead electrode 22 by a bonding wire 18. Although not shown, the collector electrode 34 formed on the lower surface of the semiconductor substrate 10 is connected to the third lead electrode 24.
Although not shown, each lead electrode 20, 22, and 24 extends to the outside of the package of the semiconductor device 100, and each electrode formed on the semiconductor substrate 10 is an electronic component outside the semiconductor device 100. The function to connect with. That is, the first lead electrode 20 connected to the four emitter electrodes 14 a to 14 d corresponds to the emitter terminal of the semiconductor device 100, and the second lead electrode 22 connected to the gate pad 16 is the semiconductor device 100. The third lead electrode 24 connected to the collector electrode 34 corresponds to the collector terminal of the semiconductor device 100.

The structure of the semiconductor substrate 10 will be described with reference to FIG. FIG. 2 is a schematic cross-sectional view of the semiconductor substrate 10 when viewed along line II-II in FIG. 2 shows only a cross section of a portion corresponding to the two emitter electrodes 14a and 14b shown in FIG. 1, and a cross section of a portion corresponding to the other two emitter electrodes 14c and 14d is omitted. is doing. The structure of the cross section of the portion corresponding to the other two emitter electrodes 14c and 14d is the same as the structure shown in FIG.
A low-concentration p-type body layer 28, a low-concentration n-type drift layer 30, and a p-type collector layer 32 are formed on the semiconductor substrate 10 from the upper side of FIG. A collector electrode 34 is formed on the lower surface of the collector layer 32.
A plurality of trenches 36a to 36f that penetrate through the body layer 28 and reach the drift layer 30 are formed on the surface of the body layer 28. The wall surfaces of the trenches are covered with an insulating film, and the gates are formed inside the gate layer 28. The electrode is filled. Each gate electrode is connected to the gate pad 16 shown in FIG.
High-concentration n-type emitter regions 38a are formed on both sides of the trench 36a on the surface of the body layer 28. Similarly, emitter regions 38b-38f are formed on both sides of each trench 36b-36f.

  A semiconductor structure constituting the IGBT is formed by the gate electrode filled in the trench 36, the emitter region 38 formed on both sides of the trench 36, the body layer 28, the drift layer 30, and the collector layer 32. ing. One transistor (transistor structure) is formed by the gate electrode filled in the trench 36a and the emitter regions 38a formed on both sides of the trench 36a. Similarly, one transistor is formed by emitter regions 38b and the like formed on both sides of the trench 36b. In FIG. 2, six transistors are depicted.

An emitter electrode 14a is formed on the surfaces of the three emitter regions 38a, 38b, and 38c. The emitter electrode 14a is in common contact with the three emitter regions (emitter regions 38a, 38b, and 38c) constituting the three transistors. The emitter electrode 14a forms a transistor block 40a in which three transistors are connected in parallel. Similarly, the emitter electrode 14b is formed so as to be in contact with the surfaces of the three emitter regions 38d, 38e, and 38f. The emitter electrode 14b forms a transistor block 40b in which three transistors are connected in parallel.
Although not shown in FIG. 2, the cross section of the portion corresponding to the emitter electrodes 14c and 14d has the same structure as that in FIG. A transistor block (transistor block 40c shown in FIG. 3) in which three transistors are connected in parallel is formed by the emitter electrode 14c, and a transistor block (FIG. 3) in which three transistors are connected in parallel by the emitter electrode 14d. The transistor block 40d) shown in FIG. That is, the semiconductor substrate 10 has 12 transistors. The twelve transistors are divided into four transistor blocks each having three IGBTs.

A schematic equivalent circuit diagram of the semiconductor device 100 is shown in FIG. As shown in FIG. 3, the semiconductor device 100 has a circuit configuration in which 12 transistors are connected in parallel. Four emitter blocks 14a-14d form four transistor blocks 40a-40d, each consisting of three transistors.
Each emitter electrode 14a-14d is individually connected to the first lead electrode 20 by a bonding wire 26a-26d. Since each bonding wire has a resistance, the bonding wires 26a to 26d are represented by resistance symbols in FIG.
Since the third lead electrode 24 is connected to the collector electrode 34, the third lead electrode 24 is equal to the collector electrode 34 in the circuit diagram of FIG. 3. The collector electrode 34 is commonly connected to 12 transistors.

  Each bonding wire 26a-26d has a resistance value corresponding to the on-resistance of the corresponding transistor block 40a-40d. Specifically, the bonding wires 26a to 26d have resistance values that set the resistance value of each path from the collector electrode 34 to the first lead electrode 20 through the emitter electrodes 14a to 14d to a predetermined value. have. That is, “ON resistance of transistor block 40a + resistance value of bonding wire 26a” = “ON resistance of transistor block 40b + resistance value of bonding wire 26b” = “ON resistance of transistor block 40c + resistance value of bonding wire 26c” = The relationship of “ON resistance of transistor block 40d + resistance value of bonding wire 26d” = predetermined value is satisfied.

The predetermined value is based on the voltage applied between the emitter terminal (first lead electrode 20) and the collector terminal (third lead electrode 24) of the semiconductor device 100, and the design value of the current that flows in the semiconductor device 100 when turned on. It has been decided.
The resistance between the emitter terminal and the collector terminal can be calculated from the voltage applied between the emitter terminal and the collector terminal and the design value of the current flowing through the semiconductor device 100 when it is turned on. The aforementioned predetermined value is a value obtained by dividing the calculated resistance by the number of transistor blocks.

The on-resistance of the transistor block differs depending on the transistor block. That is, the on resistance of the transistor block 40a, the on resistance of the transistor block 40b, the on resistance of the transistor block 40c, and the on resistance of the transistor block 40d are different.
Contrary to the difference, “ON resistance of transistor block 40a + resistance value of bonding wire 26a” = “ON resistance of transistor block 40b + resistance value of bonding wire 26b” = “ON resistance of transistor block 40c + bonding wire 26c” In order to obtain a relationship of “resistance value of the transistor block 40d + resistance value of the bonding wire 26d”, the resistance value of the bonding wire 26a, the resistance value of the bonding wire 26b, and the resistance value of the bonding wire 26c are obtained. Each of the resistance values of the bonding wire 26d must be selected to an appropriate value.

  In order to adjust the resistance value of the bonding wire, the length of the bonding wire may be adjusted. The longer the length of the bonding wire, the greater the resistance. Alternatively, bonding wires having different thicknesses may be used to adjust the resistance of the bonding wire. The thinner the thickness, the greater the resistance. By selecting at least one of the length, thickness, and number, the resistance value of the bonding wire 26a, the resistance value of the bonding wire 26b, the resistance value of the bonding wire 26c, and the resistance value of the bonding wire 26d are each set. It is adjusted to an appropriate value, and “the on-resistance of the transistor block + the resistance value of the bonding wire” is made uniform for all the blocks 40a to 40d.

Hereinafter, the procedure for determining the resistance value of the bonding wire will be exemplified.
(1) From a design value of the semiconductor device 100, a voltage V _des applied between the emitter terminal and the collector terminal of the semiconductor device 100, and a current (collector current) flowing through the emitter terminal and the collector terminal when the semiconductor device 100 is turned on. I _des is decided.
(2) The resistance R _des between the emitter terminal and the collector terminal of the semiconductor device 100 is obtained from the design condition that the current I _des flows at the voltage V _des . In order for the current to flow evenly through the four transistor blocks, the resistance of the respective paths from the collector electrode 34 to the first lead electrode 20 via the emitter electrodes 14a to 14d should be R _des / 4. That's fine. The resistance R _des / 4 corresponds to the predetermined value described above.
(3) The on-resistance R _block of each transistor _block is measured. A method for measuring the on-resistance of the transistor block will be described later.
(4) The resistance R _bw of each bonding wire is obtained by R _bw = R _des / 4−R _block .
The emitter electrodes 14a to 14d and the first lead electrode 20 are individually connected by the bonding wires having the resistance determined through the above-described process, whereby the emitter electrode 14a is connected to the emitter electrode 14a from the collector electrode 34 (third lead electrode 24). The resistances of the respective paths to the first lead electrode 20 through ˜14d can be made equal to R _des / 4. Thus, when the collector current I _des flows through the semiconductor device 100, the current I _des / 4 flows evenly through the transistor blocks.
In this case, even when a transistor having a smaller on-resistance than the other transistors is included in any of the transistor blocks, the current I _des / 4 flows through each transistor block evenly.

According to the semiconductor device 100 described above, the bias of the current flowing through each transistor can be reduced. This is due to the following reason.
In a semiconductor device in which a plurality of transistors are simply connected in parallel, when a transistor having an on-resistance smaller than the on-resistance of another transistor is present, a current larger than the design value flows in the transistor having a small on-resistance, A current smaller than the design value flows through the other transistors. The amount by which the current flowing through the other transistors is smaller than the design value is concentrated on the transistors with low on-resistance. The design value of the current flowing through each transistor is the magnitude of the current flowing through each transistor when it is assumed that all the transistors have the same on-resistance. In other words, the design value of the current flowing through each transistor is a value obtained by dividing the collector current I _des by the total number of transistors.
In the semiconductor device of this embodiment, the current flowing through each transistor block is uniform. Accordingly, in a transistor block that does not include a transistor with a low on-resistance, a current as designed flows through each transistor.
On the other hand, in a transistor block including a transistor having a low on-resistance, a current smaller than the design value flows through a transistor having an on-resistance as designed. On the other hand, a current larger than the designed value flows through a transistor having a low on-resistance. However, a bonding wire having a large resistance value is connected to this transistor block, and the average current flowing through each transistor is smaller than that of the other blocks. Even if a current flows concentrated on a transistor having a small on-resistance, the current is smaller than a current value that flows when the transistors are simply connected in parallel. Compared to a case where a large number of transistors are simply connected in parallel, a transistor having a smaller resistance than other transistors by dividing into a plurality of blocks and compensating for variations in on-resistance by the resistance value of the bonding wire The current concentration on the can be reduced.

  Next, a process for manufacturing the semiconductor device 100 will be described. The semiconductor device 100 is manufactured by (1) a semiconductor substrate processing step, (2) a transistor block on-resistance measurement step, and (3) a wire bonding step.

(1) Semiconductor substrate manufacturing process In this process, a semiconductor substrate having the cross-sectional structure shown in FIG. 2 and having a plurality of transistor structures is manufactured. Since the semiconductor substrate can be manufactured by a generally well-known manufacturing method, a detailed description is omitted. However, as shown in FIG. 2, the emitter electrode is divided into a plurality of parts. The divided emitter electrode can also be formed by a conventional method of manufacturing a semiconductor substrate.

(2) On-resistance measurement step of transistor block In this step, the resistance is measured for each transistor block divided by the emitter electrode. Specifically, the on-resistance is not directly measured, but the cut-off voltage (or on-voltage) is measured for each transistor block, and between the collector and emitter of the transistor block at the measured cut-off voltage (or on-voltage). The on-resistance is calculated from the voltage and current values. The cut-off voltage is a gate voltage when a collector current of a predetermined value flows in a state where a constant voltage is applied between the collector and the emitter. The on-voltage is a voltage between the collector and the emitter when a collector current of a predetermined value flows with a constant gate voltage applied. The measurement of the cut-off voltage (or on-voltage) has heretofore been performed for confirming the performance of the entire semiconductor device, but has not been performed for each transistor block. By measuring the cut-off voltage (or on-voltage), the relationship between the voltage and current between the collector electrode and the emitter electrode for each transistor block can be specified. From this relationship, the on-resistance of the transistor block can be obtained.
The cut-off voltage (or on-voltage) for each transistor block can be easily measured by applying a measurement probe to each emitter electrode 14a-14d and collector electrode 34.

(3) Wire Bonding Step As shown in FIG. 1, the semiconductor substrate 10 is fixed to the frame 12, and the emitter electrodes 14a-14d and the first lead electrode 20 are individually connected with bonding wires. The wire bonding method itself is the same as the known method. However, in the case of the present embodiment, the bonding wires connecting the respective emitter electrodes 14a to 14d and the first lead electrode 20 have their own resistances. The resistance of the bonding wire is determined as described above.
Through the above steps, a semiconductor device that suppresses current concentration on a transistor with low resistance can be manufactured.

In the above, the specific example of this invention was demonstrated in detail. Here, some points to be noted regarding the above embodiment are described.
The structure of the semiconductor substrate may not be the structure of FIG. The semiconductor substrate may be a type in which a collector region, an emitter region, and a gate electrode are formed on one surface side of the semiconductor substrate. Alternatively, it may be a unipolar type semiconductor device having a source region and a drain region. Also in this case, a vertical type having main electrodes on both the front and back sides may be used, or a horizontal type having a pair of main electrodes on one side may be used.
The electrode divided into blocks is not limited to the emitter electrode. The collector electrode, the source electrode, or the drain electrode may be divided into a plurality of electrodes.
Each transistor block only needs to be divided into units having approximately the same number of transistors, and may not be exactly the same number. In the case of having 1000 or more transistors as a whole, if the number of transistors in the block is almost the same, the present invention can be applied as it is even if the number is not exactly the same.
Note that each transistor block may be composed of a significantly different number of transistors. If the following equation, that is, (block on-resistance + bonding wire resistance) × number of transistors in the block is uniform for all blocks, the magnitude of the current flowing through each transistor is uniform. .

It is also preferable to set the resistance of each bonding wire for individually connecting the emitter electrode and the lead electrode of each transistor block as follows.
The resistance of the bonding wire is set to a value in which the current flowing through the transistor block is smaller than the designed current value when the on resistance of the transistor block is smaller than the designed on resistance. The case where the on-resistance of the transistor block is smaller than its designed resistance occurs when the transistor block includes a transistor having an on-resistance smaller than the designed on-resistance of the transistor. In such a transistor block, the resistance value of the bonding wire is set so that a current smaller than a set current value that should be flowed flows. As a result, current concentration on a transistor having a small resistance can be suppressed. On the other hand, a current larger than the designed current value flows through the other transistor blocks. The current flowing through the other transistor blocks is evenly distributed to a large number of transistors having an on-resistance as designed. As a whole semiconductor device, a current as designed can be flowed, and current concentration on a transistor having a small on-resistance can be suppressed.
Note that the design resistance of the transistor block is determined from the on-resistance of the transistor included in the transistor block. The on-resistance in design of a transistor block composed of n transistors whose design resistance is r is r / n.
The design current value of the transistor block is determined from the design current value of the transistors included in the transistor block. The design current value of a transistor block composed of n transistors whose design current value is i is n × i.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1 is a schematic perspective view of a semiconductor device according to an embodiment of the present invention. It is typical sectional drawing of a semiconductor substrate when it sees along the II-II line | wire of FIG. FIG. 2 is a schematic equivalent circuit diagram of the semiconductor device of FIG. 1.

Explanation of symbols

10: Semiconductor substrate 12: Frames 14a, 14b, 14c, 14d: Emitter electrode 18: Bonding wire 20: First lead electrode 22: Second lead electrode 24: Third lead electrodes 26a, 26b, 26c, 26d: Bonding wire 28 : Body layer 30: Drift layer 30
32: Collector layer 34: Collector electrode 40: Transistor block 100: Semiconductor device

Claims (2)

A semiconductor device comprising a second plurality of transistor blocks, each comprising a first plurality of transistors, and comprising a third plurality of transistors equal to the product of the first plurality and the second plurality of transistors. Manufacturing method,
Forming a third plurality of transistor structures each having an “emitter region and a collector region” or a “source region and a drain region” in a semiconductor substrate;
Forming a common electrode commonly connected to one of the “emitter region or source region” and the “collector region or drain region” of the third plurality of transistor structures;
A divided electrode that is commonly connected to the other of the “emitter region or source region” and the “collector region or drain region” of the first plurality of transistor structures in the transistor block and is divided for each transistor block. Forming, and
Forming a common lead electrode;
Measuring the on-resistance between the common electrode and the divided electrode for each transistor block;
The common lead electrode and the split electrode are connected to the transistor block having a high on-resistance by a bonding wire having a low resistance value, and the common lead electrode and the split electrode are connected to the transistor block having a low on-resistance by a bonding wire having a high resistance value. And a process of
Equipped with a,
In the connecting step, a resistance difference is obtained by subtracting an on-resistance measured for each transistor block from a predetermined resistance value, and a resistance value closest to the resistance difference is selected from a plurality of types of bonding wires having different resistance values. A method for manufacturing a semiconductor device, comprising: a step of selecting a bonding wire having : A semiconductor device comprising a second plurality of transistor blocks, each comprising a first plurality of transistors, and comprising a third plurality of transistors equal to the product of the first plurality and the second plurality of transistors. Manufacturing method,
Forming a third plurality of transistor structures each having an “emitter region and a collector region” or a “source region and a drain region” in a semiconductor substrate;
Forming a common electrode commonly connected to one of the “emitter region or source region” and the “collector region or drain region” of the third plurality of transistor structures;
A divided electrode that is commonly connected to the other of the “emitter region or source region” and the “collector region or drain region” of the first plurality of transistor structures in the transistor block and is divided for each transistor block. Forming, and
Forming a common lead electrode;
Measuring the on-resistance between the common electrode and the divided electrode for each transistor block;
The common lead electrode and the split electrode are connected to the transistor block having a high on-resistance by a bonding wire having a low resistance value, and the common lead electrode and the split electrode are connected to the transistor block having a low on-resistance by a bonding wire having a high resistance value. And a process of
With
In the connecting step, the on-resistance measured for each transistor block is subtracted from a predetermined resistance value to obtain a resistance difference, and at least one of the thickness, length, and number of bonding wires that brings about a resistance value substantially equal to the resistance difference. A method for manufacturing a semiconductor device, comprising the step of selecting

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