JP2020088239A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of relaxing the temperature distribution in an element formation region and coping with high-speed switching by controlling the transient current distribution due to the switching operation.SOLUTION: A semiconductor device 1 includes a cell region 3 in which a plurality of transistor cells T are arranged in parallel on the main surface 21 side of a semiconductor substrate 2, a gate wiring portion 4 connected to a gate electrode 10 of a transistor cell T, and a gate pad portion GP that applies a gate potential to the gate electrode 10 via the gate wiring portion 4. The gate wiring portion 4 includes a low-resistance wiring portion 4A and a high-resistance wiring portion 4B having higher electrical resistance than low-resistance wiring portion 4A, and the high-resistance wiring portion 4B is arranged in a region along the outer peripheral edge of the cell region 3, and the low-resistance wiring portion 4A is arranged inside a region in which the high-resistance wiring portion 4B is arranged, which includes the center of the cell region 3.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device used for a switching element or the like.

For example, a semiconductor device used for a power switching element has a relatively large chip area for controlling a large current. In this case, the temperature difference between the central portion and the peripheral portion is likely to be large and the temperature distribution is likely to occur in the cell region where the transistor cell serving as the heat generating portion is formed. On the other hand, the chip size of the semiconductor device is limited so that the maximum temperature of the heat generation region does not exceed the heat resistant temperature. Be done.

In Patent Document 1, in order to reduce the temperature imbalance in the chip surface, the unit cells arranged in stripes are arranged sparsely in the central portion of the chip where the heat generation amount is large and the heat dissipation is poor, and the heat generation amount is set. A semiconductor device has been proposed in which the heat dissipation of the central part of the chip is improved by arranging them densely in the peripheral part of the chip which has small heat dissipation and good heat dissipation. In Patent Document 1, such a cell arrangement is intended to reduce the temperature imbalance in the chip surface and improve the uniformity of temperature distribution.

JP-A-2004-363327

In the configuration of Patent Document 1, the intervals at which the unit cells are arranged are varied to adjust the distribution of current flowing in the chip surface. However, although the current flowing through the central portion is suppressed with respect to the peripheral portion, the heat generation amount in the central portion is suppressed, but a larger amount of current flows in the peripheral portion, so that the conduction loss is biased. This is because the loss is generated in proportion to the square of the current (that is, I ² ×R), and the conduction loss in the peripheral portion is larger than that in the central portion, and as a result, the entire chip is reduced. Will increase the conduction loss.

On the other hand, at the time of switching, a transient current due to the switching operation flows and switching loss occurs. At that time, if the temperature distribution exists in the cell region, the threshold voltage that defines the switching operation varies, and the threshold voltage decreases in the higher temperature region, and the turn-on current or turn-off current is likely to concentrate. In particular, when the switching speed is increased by devising the gate wiring structure, etc., the ratio of turn-off loss relatively increases, so the temperature tends to rise in the region where turn-off loss is concentrated, and the temperature distribution is further accelerated. May cause

The present invention has been made in view of the above problems, and aims to provide a semiconductor device capable of coping with high-speed switching by controlling the transient current distribution due to the switching operation, thereby relaxing the temperature distribution in the cell region. Is.

One aspect of the present invention is
On the main surface (21) side of the semiconductor substrate (2), a cell region (3) in which a plurality of transistor cells (T) are arranged side by side, and a gate wiring part (10) connected to the gate electrode (10) of the transistor cell (3). A semiconductor device (1) comprising: 4) and a gate pad portion (GP) for applying a gate potential to the gate electrode via the gate wiring portion,
The gate wiring portion has a low resistance wiring portion (4A) and a high resistance wiring portion (4B) having higher electric resistance than the low resistance wiring portion,
The high resistance wiring part is arranged in a region along the outer peripheral edge of the cell region, the low resistance wiring part is inside the region in which the high resistance wiring part is arranged, and in the center of the cell region. The semiconductor device is arranged in a region including a portion.

By configuring the gate wiring portion as in the above semiconductor device, the high resistance wiring portion arranged outside the low resistance wiring portion arranged in the region including the central portion of the cell region has a delay. And turn on or off. Therefore, at the time of turn-off, the turn-off current is concentrated in the region on the outer peripheral side of the cell region and the temperature easily rises, while the temperature increase is suppressed in the region including the central portion of the cell region, and as a whole, It becomes possible to relax the temperature distribution in the cell region.

As described above, according to the above aspect, by controlling the transient current distribution due to the switching operation, the temperature distribution in the cell region can be relaxed, and a semiconductor device capable of high-speed switching can be provided.
In addition, the reference numerals in parentheses described in the claims and the means for solving the problems indicate the correspondence with the specific means described in the embodiments described later, and limit the technical scope of the present invention. Not a thing.

FIG. 2 is a plan view showing a schematic configuration of a semiconductor device according to the first embodiment and a sectional view taken along the line I-I thereof. FIG. 2 is a diagram showing a configuration example of a semiconductor element formed in a cell region of the semiconductor device in the first embodiment, and an enlarged cross-sectional view of a II portion in FIG. 1 and a circuit diagram symbol of the semiconductor element. FIG. 6 is an operation waveform diagram showing the basic switching characteristics of the semiconductor device for test in Test Example 1 by comparing the characteristics at low speed switching and at high speed switching. In Test Example 1, a double pulse test circuit diagram for evaluating the basic switching characteristics of a semiconductor device for testing. 6 is a plan view showing an example of a wiring structure in a test semiconductor device in Test Example 1. FIG. FIG. 6 is a diagram showing an in-plane temperature distribution of a cell region and a temperature (thermal resistance) distribution in an AA cross section in a test semiconductor device in Test Example 1. 6 is a schematic cross-sectional view showing an example of a cooling structure of a test semiconductor device in Test Example 1. FIG. 7 is a diagram showing a temperature distribution in a plane of a cell region and a temperature characteristic of a threshold voltage in a test semiconductor device in Test Example 1. FIG. 10 is an operation waveform diagram showing switching characteristics of cell regions in a semiconductor device for testing in a test example 1 in comparison in regions having different threshold voltages. FIG. In Test Example 1, a graph showing the effect of relaxing the temperature distribution by the semiconductor device of Embodiment 1, showing the relationship between the position in the cell region and turn-off loss and temperature. FIG. 6 is an operation waveform diagram showing a comparison of switching characteristics depending on the in-plane position of the cell region in the semiconductor device of Embodiment 1 in Test Example 1; FIG. 10 is a diagram showing an effect in the semiconductor device of the first embodiment in Test Example 1, and is a diagram showing a relationship between a position in the BB cross section of the cell region, turn-off loss, and temperature. FIG. 6 is a plan view showing a schematic configuration of a semiconductor device according to the second embodiment. FIG. 6 is a plan view showing a schematic configuration of a semiconductor device according to a third embodiment. FIG. 10 is a diagram showing a comparison between the wiring pitch in the cell region of the semiconductor device, the drain current, and the turn-off loss in the third embodiment. FIG. 6 is a plan view showing a schematic configuration of a semiconductor device according to a fourth embodiment. FIG. 10 is a plan view showing a schematic configuration of a semiconductor device according to the fifth embodiment. FIG. 13 is a plan view showing a schematic configuration of a semiconductor device according to the sixth embodiment. FIG. 16 is a plan view showing a schematic configuration of a semiconductor device according to the seventh embodiment. FIG. 16 is a plan view showing a schematic configuration of a semiconductor device according to an eighth embodiment. FIG. 16 is a plan view showing a schematic configuration of a semiconductor device according to a ninth embodiment.

(Embodiment 1)
An embodiment according to a semiconductor device will be described with reference to the drawings.
The semiconductor device of the present embodiment is used, for example, as a switching element for a large current in a power conversion device or the like, and is configured to be able to suppress the temperature distribution due to high speed switching.
The outline is shown below.
As shown in FIGS. 1 and 2, the semiconductor device 1 is connected to the main surface 21 side of the semiconductor substrate 2 to a cell region 3 in which a plurality of transistor cells T are arranged in parallel and a gate electrode 10 of the transistor cell T. The gate wiring portion 4 and the gate pad portion GP are provided. The gate wiring portion 4 is formed on the surface of the cell region 3 and connected to the gate electrode 10 of the transistor cell T, and the gate pad portion GP applies a gate potential to the gate electrode 10 via the gate wiring portion 4. Is configured to.

As will be described later in detail, the gate wiring portion 4 has a low resistance wiring portion 4A and a high resistance wiring portion 4B having a higher electric resistance than the low resistance wiring portion 4A. The high resistance wiring part 4B is arranged in a region along the outer peripheral edge of the cell region 3, and the low resistance wiring part 4A is inside the region in which the high resistance wiring part 4B is arranged and in the center of the cell region 3. It is arranged in a region including a part. The low-resistance wiring portion 4A can be made of, for example, a low-resistance wiring material containing metal, and the high-resistance wiring portion 4B can be made of a high-resistance wiring material having a higher electric resistance than the low-resistance wiring material.

With such an arrangement, the gate control signal input from the gate pad section GP to the gate wiring section 4 propagates to the high resistance wiring section 4B with a delay with respect to the low resistance wiring section 4A. Accordingly, switching of the transistor cell T is delayed in the vicinity of the high resistance wiring portion 4B, and the turn-off current flowing in the cell region 3 is locally concentrated, so that the temperature distribution in the cell region 3 can be relaxed. It will be possible.

The gate wiring part 4 is, for example, a combination of an outer peripheral side gate wiring 40 arranged in the peripheral part of the cell region 3 and a plurality of inner peripheral side gate wirings 41, 42 connected inside the outer peripheral side gate wiring 40. It can be formed into a wiring shape. The inner peripheral side gate wirings 41 and 42 are configured as the low resistance wiring portion 4A except at least a part connected to the outer peripheral side gate wiring 40, and the outer peripheral side gate wiring 40 is at least adjacent to the gate pad portion GP. Except for the region, it can be configured as the high resistance wiring portion 4B.

Specifically, the inner peripheral side gate wirings 41 and 42 are connected to the gate pad portion GP, and the strip-shaped main gate wiring 41 arranged in the central portion of the cell region 3 and a plurality of main gate wirings 41 in the longitudinal direction. A plurality of branch wirings 42 branching from a location and connected to the outer peripheral side gate wiring 40 can be provided. The main gate wiring 41 is connected to the gate pad portion GP via the gate connecting portion 4C, for example.

The gate control signal input from the gate pad portion GP is rapidly propagated from the main gate wiring 41 which is the low resistance wiring portion 4A to the branch wiring 42, while the outer peripheral side gate wiring 40 which is the high resistance wiring portion 4B. Is propagated with a delay. At this time, in the cell region 3, in the transistor cell T, the central portion where the main gate wiring 41 is arranged is turned on and turned off first, and the peripheral portion where the outer peripheral side gate wiring 40 is arranged is turned on and turned off later.
As a result, for example, at the time of turn-off, the turn-off current tends to concentrate in the region where the high-resistance wiring portion 4B is arranged, so that the turn-off current concentration area A (that is, the shaded area shown in FIG. 1) is formed in the peripheral portion of the cell region 3. Region) is formed and contributes to the relaxation of the temperature distribution in the cell region 3.

Next, the configuration of each part of the semiconductor device 1 will be specifically described.
In FIG. 1, a semiconductor device 1 has a substantially rectangular semiconductor substrate 2, and a semiconductor layer 20 having a cell region 3 is laminated on the main surface 21 side thereof. In the present embodiment, the semiconductor layer 20 has a substantially rectangular region along the outer peripheral shape of the semiconductor substrate 2 as the cell region 3 in which the transistor cell T having the trench structure shown in FIG. 2 is formed, and surrounds the outside of the cell region 3. The rectangular annular region is the peripheral region 30 in which the gate pad portion GP and the Kelvin/source pad KSP are arranged.
The plurality of transistor cells T are electrically connected in parallel so that, for example, the direction along one side of the cell region 3 and the extending direction of the trench (for example, the X direction shown in the upper diagram of FIG. 1) are parallel to each other. They are arranged in stripes.
The main surface 21 of the semiconductor substrate 2 is one surface in the thickness direction of the semiconductor substrate 2 (for example, the Y direction shown in the lower diagram of FIG. 1), and thereafter, the surface opposite to the main surface 21 is the surface of the semiconductor substrate 2. The back surface 22 is used.

A gate wiring portion 4 electrically connected to the gate pad portion GP is arranged on the surface of the cell region 3, and the wiring shapes of the gate wiring portion 4 are the outer peripheral side gate wiring 40 and the inner peripheral side gate wiring 41. , 42 in combination. The outer peripheral side gate wiring 40 is a substantially rectangular wiring portion arranged so as to surround the outer peripheral edge portion of the cell region 3, and the inner peripheral side gate wirings 41 and 42 are arranged inside thereof. It consists of a strip-shaped wiring part.
The gate pad portion GP is arranged outside the cell region 3 adjacent to the central portion of one side thereof, and the gate connecting portion 4C extending from the gate pad portion GP is connected to the inner peripheral side gate wirings 41 and 42. The gate connecting portion 4C is, for example, a part of the outer peripheral side gate wiring 40 adjacent to the gate pad portion GP, and includes a rectangular portion 401 made of a low resistance wiring material containing metal.

Specifically, the inner peripheral side gate wiring has a strip-shaped main gate wiring 41 and a plurality of pairs of strip-shaped branch wirings 42 branching to both sides of the main gate wiring 41. The main gate wiring 41 is arranged in the central portion of the cell region 3 with the extending direction of the trench (that is, the X direction) as the longitudinal direction, and one end side thereof is connected to the gate wiring 40 at the outer peripheral side gate wiring 40. It is connected to the gate pad portion GP via the portion 4C, and the other end side extends to the vicinity of one side facing the one side on which the gate pad portion GP is arranged.
The plurality of pairs of branch wirings 42 branch to both sides from a plurality of locations (for example, five locations in FIG. 1) including the extended end of the main gate wiring 41, and extend in a direction orthogonal to the X direction, respectively. The end portion 421 is electrically connected to the inner circumference of the outer peripheral side gate wiring 40 located in the extending direction.

In the present embodiment, in the gate wiring portion 4, the main gate wiring 41 and main portions of the plurality of pairs of branch wirings 42 branched from the main gate wiring 41 are configured as the low resistance wiring portion 4A. The low resistance wiring portion 4A is formed using a conductive material having a relatively low electric resistance. The gate connecting portion 4C that connects the gate pad portion GP and the main gate wiring 41 is also formed by using a conductive material having the same low electric resistance.
In addition, the outer peripheral side gate wiring 40 is configured as the high resistance wiring portion 4B except for a portion where the rectangular portion 401 serving as the gate connecting portion 4C is arranged. The branch ends 421 of the plurality of pairs of branch wirings 42 connected to the outer peripheral side gate wiring 40 are also configured as the high resistance wiring portion 4B. The high resistance wiring part 4B is formed using a conductive material having a relatively high electric resistance as compared with the constituent material of the low resistance wiring part 4A.

That is, in the peripheral portion of the cell region 3, the high resistance wiring portion 4B having a higher electric resistivity than the low resistance wiring portion 4A is arranged except for the region where the gate connection portion 4C is arranged. The low resistance wiring portion 4A is arranged in a region including the central portion of the cell region 3 which is located inside the peripheral portion where the high resistance wiring portion 4B is arranged. The wiring width is, for example, the same in the entire gate wiring portion 4, and the wirings in the gate wiring portion 4 are arranged in a line-symmetrical shape with the main gate wiring 41 as the axis of symmetry.

Here, as the conductive material having a relatively low electric resistance which constitutes the low resistance wiring portion 4A, for example, a metal wiring material containing a metal such as aluminum or copper or a metal alloy (for example, aluminum Electric resistivity: up to 3×10 ⁻⁸ Ωm).
Further, the conductive material having a relatively high electric resistance that constitutes the high resistance wiring portion 4B is a conductive material having a higher electric resistivity than a metal-based wiring material containing a metal or a metal alloy, and is, for example, polysilicon. Examples of such materials include high-resistance wiring materials containing a polycrystalline semiconductor (for example, electrical resistivity of polysilicon: 1×10 ⁻⁵ Ωm).
The low-resistance wiring portion 4A may be adjusted to have a desired low electric resistance by using a conductive material having a low electric resistance. For example, a metal wiring material may have a multi-layer structure. Further, the underlying layer may have a structure in which, for example, a polysilicon layer or the like is laminated.

As shown in FIG. 2, examples of the semiconductor element forming the transistor cell T include a transistor such as a MOSFET (that is, a metal oxide semiconductor field effect transistor) and an IGBT (that is, an insulated gate bipolar transistor). For the semiconductor substrate 2, a semiconductor such as SiC or GaN can be used.

As an example, as shown a vertical MOSFET structure example and schematic symbol in FIG. 2, the main surface 21 of the n-type semiconductor substrate 2, n ^- -type drift layer 200 is provided, n ^- -type The p-type base region 11 is provided in the surface layer portion of the drift layer 200. An n ⁺ type source region 12 is provided in the surface layer portion of the p type base region 11. A trench 13 that penetrates the p-type base region 11 and the n ⁺ -type source region 12 and reaches the n ⁻ -type drift layer 200 is provided, and an inner surface thereof and a part of the surface of the n ⁺ -type source region 12 are formed, for example. , A gate oxide film 14 made of silicon oxide is provided.

A gate electrode 10 made of, for example, polysilicon is embedded in the trench 13, and an insulating film 15 made of, for example, silicon oxide is provided so as to cover the gate electrode 10. A source electrode 16 is provided so as to cover the insulating film 15 and the surfaces of the p-type base region 11 and the n ⁺ -type source region 12, and a drain electrode 17 is provided on the back surface 22 side of the semiconductor substrate 2. The gate electrode 10, the source electrode 16 and the drain electrode 17 are connected to the gate terminal G, the source terminal S and the drain terminal D, respectively.

In the MOSFET having the above structure, the gate terminal G is provided corresponding to, for example, the gate pad portion GP in FIG. 1, and is connected to the gate electrode 10 via the gate pad portion GP and the gate wiring portion 4. The source terminal S and the drain terminal D are connected to the source electrode 16 and the drain electrode 17 via a source pad and a drain pad (not shown).
Then, a gate control signal output from an external driving device (not shown) is input to the gate electrode 10 via the gate pad section GP and the gate wiring section 4, so that the source terminal S and the drain terminal D are connected to each other. Is controlled. That is, when a predetermined gate voltage is supplied to the gate electrode 10, the MOSFET is turned on, and the MOSFET is turned on between the source electrode 16 and the drain electrode 17 in the vertical direction (that is, Y in FIG. 1). Current flows in the direction.
In the circuit diagram of FIG. 2, the end of the wiring drawn out between the source electrode 16 and the source terminal S is connected to the Kelvin source terminal KS via the Kelvin source pad KSP (see FIG. 1, for example). To be done.

In FIG. 1, in the cell region 3 of the semiconductor layer 20, a large number of transistor cells T each having the MOSFET of the configuration shown in FIG. 2 as a basic unit are arranged in parallel.
In the gate wiring portion 4 arranged on the surface of the cell region 3, the main gate wiring 41, which is the low resistance wiring portion 4A, is arranged in the X direction in parallel with the trench of the transistor cell T, passing through the central portion of the cell region 3. Further, the branch wiring 42 extends in the direction orthogonal to the X direction and is electrically connected to the gate electrode 10 of each transistor cell T located in the lower layer. Outside the low-resistance wiring portion 4A, a branch end portion 421 of the branch wiring 42 that is the high-resistance wiring portion 4B and an outer peripheral side gate wiring 40 connected to the branch end portion 421 are arranged, and are located in lower layers. It is electrically connected to the gate electrode 10 of the transistor cell T.

At this time, the gate control signal is input to the cell region 3 from the gate pad portion GP, so that the transistor cells T are sequentially turned on or off. In addition, the cell region 3 becomes a heat generation region where heat is generated due to the current flowing through the transistor cell T with switching, and the larger the amount of current flowing, the easier the temperature rises due to heat generation.

Therefore, in the present embodiment, the arrangement of the gate wiring portion 4 is devised in order to adjust the heat generation amount, and the low resistance wiring portion 4A is arranged in the region including the central portion of the cell region 3 having a large thermal resistance. A high resistance wiring portion 4B having a higher electric resistivity than the low resistance wiring portion 4A is arranged in the peripheral portion of the cell region 3 having a low resistance.
With such an arrangement, the gate control signal input from the gate pad section GP is rapidly propagated from the gate connection section 4C to the low resistance wiring section 4A, whereas the signal propagation to the high resistance wiring section 4B is delayed. Occurs. At this time, in a region outside the cell region 3 in which the high resistance wiring portion 4B is arranged, turn-on and turn-off are delayed after the low resistance wiring portion 4A, and particularly the turn-off current is concentrated, so that the temperature relatively rises. , Has the effect of relaxing the temperature distribution.

(Test Example 1)
Next, the effect of the configuration of the first embodiment will be described with reference to FIGS.
FIG. 3 shows basic switching characteristics when the gate wiring portion 4 of the semiconductor device 1 is formed uniformly, and is measured using the double pulse test circuit 100 shown in FIG. As shown in FIG. 5, in the test semiconductor device 1, the gate wiring portion 4 is a low resistance wiring portion 4A in the entire cell region 3. Specifically, the gate wiring part 4 is composed of a rectangular outer peripheral side gate wiring 40 and a plurality of strip-shaped gate wirings 410 inside thereof, and the gate wiring 410 is located between two opposite sides of the outer peripheral side gate wiring 40. Are arranged in a direction orthogonal to the X direction in which the trench of the transistor cell T extends.
In that case, as indicated by an arrow in the figure, the gate control signal input from the gate pad portion GP propagates substantially uniformly from the entire gate wiring portion 4.

In FIG. 4, a double pulse test circuit 100 includes a semiconductor module having MOSFETs 101 constituting the semiconductor device 1 as upper and lower arms of a half-bridge circuit, and the semiconductor module is connected in parallel with a capacitor 103 between positive and negative electrodes of a DC power supply 102. It is connected to the.
An inductance load 104 is connected in parallel between the drain and source of the MOSFET 101 serving as the lower arm, and a pulsed voltage signal as a gate control signal is applied to the gate of the MOSFET 101 serving as the upper arm via the gate resistor Rg. Is entered. At this time, the switching speed can be adjusted by the gate resistance Rg.

Here, as shown in the operation waveform at the time of low-speed switching in the upper part of FIG. 3, the gate source voltage Vgs starts to rise (time t1) by the application of the pulse signal to the MOSFET 101, and reaches the predetermined threshold voltage Vth. Then, at time t2, each transistor cell T is turned on. As a result, the drain and source of the MOSFET 101 become conductive, the drain current Id gradually increases, and the drain-source voltage Vds gradually decreases until reaching the on-voltage Von (time point t3). After that, when the gate-source voltage Vgs drops due to the stop of the pulse signal, the drain-source voltage Vds starts to rise (time point t4). Next, when the drain current Id gradually decreases and the gate-source voltage Vgs reaches the threshold voltage Vth (time point t5), each transistor cell T is turned off.

During a transition period such as switching, an induced voltage Ls×di/dt represented by a product of the drain current Id and the current change rate di/dt is generated by the parasitic inductance Ls of the loop between the capacitor 103 and the semiconductor module. And acts in the direction of hindering current change. That is, the drain-source voltage Vds decreases by that amount at the time of turn-on, and the drain-source voltage Vds increases by that amount at the time of turn-off.

At this time, the loss P of the MOSFET 101 is represented by the product of the drain current Id and the drain source voltage Vds, and the turn-on loss or turn-off loss generated at the time of switching is compared with the conduction loss (Id×Von) during the conduction period. growing.
In particular, as shown in the lower part of FIG. 3, the turn-off loss ratio tends to increase during high-speed switching. This is because the gate source voltage Vgs rises or falls faster than in the low speed switching, and the current change rate di/dt increases. As a result, the induced voltage Ls×di/dt also becomes large, and the voltage drop at turn-on becomes large, so that the turn-on loss becomes relatively small. On the other hand, at the time of turn-off, the voltage superimposed on the drain-source voltage Vds becomes large, so the turn-off loss becomes relatively large with respect to the turn-on loss.
In that case, heat generation due to the loss P also increases, and thus it is important to suppress switching loss.

Further, as shown in the upper diagram of FIG. 6, under the condition that the loss P is constant, the temperature (thermal resistance) distribution in the plane of the cell region 3 of the semiconductor device 1 is in the central portion including the plane center C of the cell region 3. The distribution is such that the temperature is high and the temperature decreases as the distance from the central part increases. That is, in the AA cross section passing through the center C of the surface of the cell region 3, as shown in the lower diagram of FIG. Shows a mountain-shaped distribution with low heat resistance and small thermal resistance.
When measuring the temperature (thermal resistance) distribution in FIG. 6, for example, the thermal resistance is determined based on the temperature difference between the cooling unit and a predetermined cooling temperature in consideration of the cooling structure of the semiconductor device 1 shown in FIG. Can be calculated.

Specifically, in FIG. 7, the semiconductor device 1 is mounted on the heat sink 6 serving as a cooling unit via the substrate 5. The substrate 5 is, for example, a laminated plate in which a copper plate 52 is bonded to both surfaces of an insulating ceramic plate 51, and is bonded to the back surface 22 of the semiconductor device 1 and the mounting surface of the heat sink 6 using solder 61, respectively. It The outer shape of the substrate 5 is larger than that of the semiconductor device 1, and the outer shape of the mounting surface of the heat sink 6 is larger than that of the substrate 5. At this time, as indicated by the dotted line in FIG. 7, heat is radiated from the back surface 22 side of the semiconductor device 1 to the heat sink 6 via the substrate 5 so that the heat radiation path is expanded outward, so that the center of the semiconductor device 1 is radiated. The thermal resistance becomes smaller on the outer peripheral side where heat is radiated more easily than on the part.

Further, as shown in FIG. 8, in the cell region 3 of the semiconductor device 1, the threshold voltage Vth that determines the on/off timing of the transistor cell T varies with temperature. Specifically, as shown in the lower diagram of FIG. 8, the higher the temperature is, the lower the threshold voltage Vth tends to be. When the temperature distribution temperature is as shown in the upper diagram of FIG. The threshold voltage Vth is high in the peripheral portion where the Vth is low and the temperature is low. In that case, the turn-on and turn-off timings deviate depending on the magnitude of the threshold voltage Vth.

Therefore, as shown in FIG. 9, at the time of turn-on, the central portion having a low threshold voltage Vth is turned on first (time point t11), and the peripheral portion having a high threshold voltage Vth is turned on later (time point t12). Further, at the time of turn-off, the peripheral portion having a high threshold voltage Vth is turned off first (time point t13), and the central portion having a low threshold voltage Vth is turned off later (time point t14).

At this time, in the central portion where the threshold voltage Vth is low, the turn-on becomes faster, so that the drain current Id flows more at the time of turn-on, and the turn-off becomes slower, and the drain current Id also flows at the time of turn-off. .. That is, the turn-on current and the turn-off current concentrate in the region where the temperature rises.
As described above, it is not easy to make the current flowing through the cell region 3 uniform. For example, even if the gate control signal is propagated evenly from the gate wiring portion 4, the difference in thermal resistance causes When the threshold voltage Vth varies, the current easily concentrates on a part of the cell region 3. In particular, the concentration of turn-off current, which increases in proportion during high-speed switching, concentrates more easily, and as a result, the temperature distribution may be accelerated.

On the other hand, as shown in FIG. 10, in the configuration of the first embodiment, by controlling the signal propagation from the gate wiring portion 4 arranged in the cell region 3, the turn-off loss in the peripheral portion of the cell region 3 is controlled. Is increased with respect to the central portion to relax the temperature distribution.
Specifically, as shown in FIG. 11, the gate wiring portion 4 is provided with the low resistance wiring portion 4A and the high resistance wiring portion 4B, and the high resistance wiring is provided in the peripheral portion of the cell region 3 where thermal resistance tends to be small. The turn-off current concentration area A is formed by disposing the portion 4B. The low resistance wiring portion 4A is arranged in the central portion where the thermal resistance tends to increase. At this time, the gate control signal input from the gate pad portion GP is sequentially applied to the gate electrodes 10 of the transistor cells T located on both sides of the branch wiring 42 from the central portion where the main gate wiring 41 is arranged, through the branch wiring 42. To be done. Further, the gate control signal propagates to the transistor cell T located near the high resistance wiring portion 4B after the low resistance wiring portion 4A.

Therefore, at the time of turn-off, the drain-source voltage Vds rises due to the decrease in the gate-source voltage Vgs (time point t21), then the drain current Id starts to decrease (time point t22), and the gate-source voltage Vgs decreases to the threshold voltage Vth (time point). At t23), the drain current Id becomes almost zero. At this time, the signal propagation to each transistor cell T in the cell region 3 is deviated, which causes a difference in the drain current Id flowing in each region of the cell region 3 due to the deviation of the turn-off timing of each transistor cell. For example, if the currents at three points B1 to B3 at different distances from the plane center C of the cell region 3 are drain currents Id1 to Id3, the drain current Id1 at the center point B1 near the plane center C rapidly decreases. On the other hand, the peak currents of the drain currents Id2 and Id3 increase in the order of the point B2 in the intermediate portion and the point B3 in the peripheral portion, which are farther from the surface center C.
The point B1 in the central portion is located between the two branch wirings 42 close to the center C of the plane, and the point B2 in the middle portion is located between the two branch wirings 42 outside thereof. In addition, the point B3 in the peripheral portion is located between the branch wiring 42 and the gate wiring 40 on the outer periphery of the point B3.

As a result, the turn-off current concentration area A is formed in the peripheral portion of the cell region 3 where the high resistance wiring portion 4B is arranged. Then, as shown in FIG. 12, with respect to the central portion where current concentration is suppressed, the turn-off loss increases toward the outer peripheral side, and the amount of heat generation increases. Along with this, the temperature of the central portion becomes lower and the temperature of the outer peripheral side becomes higher, so that the effect of relaxing the temperature distribution in the cell region 3 can be obtained. In the figure, the dotted line shows the case of uniform heat generation.

At that time, as shown in FIG. 12, the distribution of the turn-off loss can be positively formed by adjusting the wiring pitch of the gate wiring portion 4. Specifically, the wiring pitch P1 of the two branch wirings 42 in the central portion is made smaller than the wiring pitch P2 of the two branch wirings 42 in the outer intermediate portion, and P1<P2. Further, the wiring pitch P3 between the outer branch wiring 42 and the outer peripheral side gate wiring 40 is set so that P1/2<P2/2<P3. This is because signals can be propagated from both sides of the two branch wirings 42 that are the low resistance wiring portions 4A in the central portion and the intermediate portion.
As a result, in the central portion, the gate control signal can be more quickly propagated to the gate electrode 10 of the corresponding transistor cell, the turn-off loss can be reduced, and the turn-off loss can be concentrated in the outer peripheral portion. Become.

Further, as described above, since the drain currents Id1 to Id3 flowing through the respective parts of the cell region 3 are different from each other, the current change rate di/dt at the timing when the drain current Id becomes 0 is relaxed (for example, FIG. 11). reference). Therefore, the effect of suppressing the application of the surge voltage and the occurrence of ringing due to the current change rate di/dt can be obtained.

Therefore, according to the configuration of this embodiment, by controlling the transient current distribution during high-speed switching, it is possible to increase the current while relaxing the temperature distribution and ensuring the heat resistance of the semiconductor device 1.

(Embodiment 2)
A second embodiment of the semiconductor device 1 will be described with reference to FIG.
The basic configuration of the semiconductor device 1 of the present embodiment is the same as that of the above-described first embodiment, but the configuration of the main gate wiring 41 or the branch wiring 42 that becomes the low resistance wiring portion 4A of the gate wiring portion 4 is different. The difference will be mainly described below.
In addition, among the reference numerals used in the second and subsequent embodiments, the same reference numerals as those used in the already-described embodiments represent the same components and the like as those in the already-described embodiments, unless otherwise specified.

As shown in FIG. 13, also in this embodiment, the gate wiring portion 4 connected to the gate pad portion GP at the gate connection portion 4C is formed on the surface of the cell region 3 of the semiconductor device 1. The gate wiring portion 4 has a low resistance wiring portion 4A and a high resistance wiring portion 4B, and the turn-off current concentrated area A is formed by disposing the high resistance wiring portion 4B around the cell region 3. The same effect as that of the first embodiment, which relaxes the temperature distribution, is obtained.

Here, in the first embodiment, the wiring width is the same for the entire gate wiring portion 4, but in the present embodiment, the wiring width W1 of the main gate wiring 41, which is the low resistance wiring portion 4A, is the same as that for the other wirings. It is formed wider than the wiring width W2 of the certain branch wiring 42 and the outer peripheral side gate wiring 40 (that is, W1>W2). The gate connection portion 4C, which is a low-resistance wiring connected to one end of the main gate wiring 41, is also formed with the wiring width W1 equivalent to that of the main gate wiring 41.

By doing so, the wiring resistance of the main gate wiring 41 connected to the gate pad portion GP can be reduced, and heat generation due to energization can be suppressed. Therefore, the above effect due to the arrangement of the gate wiring portion 4 can be further improved.

(Embodiment 3)
A third embodiment of the semiconductor device 1 will be described with reference to FIGS.
The present embodiment is a modification of the second embodiment, and the wiring pitch P of the gate wiring portion 4 is constant. The wiring width W1 of the main gate wiring 41 is formed wider than the wiring width W2 of the branch wiring 42 and the outer peripheral side gate wiring 40. The other basic configuration of the semiconductor device 1 is the same as that of the second embodiment, and the description thereof is omitted. The difference will be mainly described below.

In the first and second embodiments, the branch wirings 42 of the gate wiring portion 4 are arranged such that the wiring pitch P1 at the central portion and the wiring pitch P2 at the intermediate portion are different, but it is not always necessary to make them variable. As shown, the branch wirings 42 may be arranged at a constant wiring pitch P. Here, the wiring pitch P is set so that, for example, P1<P<P2. For example, the wiring pitch between the branch wiring 42 and the outer peripheral side gate wiring 40 may be made equal.

As shown in FIG. 15, compared to the case where the wiring pitch is different, when the wiring pitch is the same, there is almost no difference between the drain current Id1 in the central portion of the cell region and the drain current Id2 in the middle portion. Therefore, the effect of reducing the turn-off loss in the central portion is smaller than that in the case where the wiring pitch is different, but the reducing effect of the turn-off loss in the peripheral portion is the same as that when the wiring pitch is different.
Therefore, by arranging the high-resistance wiring portion 4B in the peripheral portion of the cell region 3, the same effect of relaxing the temperature distribution by forming the turn-off current concentrated area A can be obtained.

(Embodiment 4)
A fourth embodiment of the semiconductor device 1 will be described with reference to FIG.
The present embodiment is a modification of the first embodiment, and the entire branch wiring 42 of the gate wiring portion 4 is configured as the low resistance wiring portion 4A. The other basic configuration of the semiconductor device 1 is the same as that of the first embodiment, and the description thereof is omitted. The difference will be mainly described below.

In the first to third embodiments, the branch end 421 of the branch wiring 42 connected to the outer peripheral side gate wiring 40 is configured as the high resistance wiring section 4B, but the entire branch wiring 42 including the branch end 421 is It may be configured as the low resistance wiring portion 4A. In that case, the low resistance wiring portion 4A is arranged up to the connection position with the outer peripheral side gate wiring 40, and the switching timing is accelerated in this area. On the other hand, on the two sides where the low resistance wiring portion 4A is not connected to the outer peripheral side gate wiring 40, since the high resistance wiring portion 4B is arranged in the peripheral portion of the cell region 3, the turn-off current concentrated area A is formed. The same effect of relaxing the temperature distribution can be obtained.

(Embodiment 5)
A fifth embodiment of the semiconductor device 1 will be described with reference to FIG.
In this embodiment, a plurality of sub gate wirings 43 are provided in parallel with the main gate wiring 41 of the gate wiring portion 4. The other basic configuration of the semiconductor device 1 is the same as that of the first embodiment, and the description thereof is omitted. The difference will be mainly described below.

In the above-described first to fourth embodiments, the main gate wiring 41 and the branch wiring 42 are provided as the inner peripheral side gate wiring of the gate wiring section 4, but the branch wiring 42 is not provided and a plurality of gate wirings are connected to the gate pad section GP. Alternatively, the wiring may be provided. Specifically, the inner peripheral side gate wiring has a main gate wiring 41 arranged in the central portion of the cell region 3 and a plurality (for example, two) strip-shaped symmetrically arranged on both sides of the main gate wiring 41. The sub gate wiring 43 is included.
In the present embodiment, the main gate wiring 41 and the sub gate wiring 43 have the same shape, and both are configured as the low resistance wiring portion 4A.

The gate pad portion GP is arranged outside the cell region 3 and adjacent to the central portion of one side thereof, and the gate connection portion 4C is provided adjacent to the gate pad portion GP. The gate connection portion 4C is composed of, for example, a strip portion 402 which is a part of one side of the outer peripheral side gate wiring 40 adjacent to the gate pad portion GP. The gate connecting portion 4C is connected to one end sides of the main gate wiring 41 and the sub gate wiring 43, respectively. The other end sides of the main gate wiring 41 and the sub gate wiring 43 extend toward one side of the outer peripheral side gate wiring 40 facing the gate pad portion GP, and are connected to the inner sides thereof.

In the present embodiment, the direction of one side where the gate pad portion GP is arranged is the X direction, and the trench of the transistor cell T formed in the cell region 3 is arranged to extend in this direction. That is, the extending direction of the main gate wiring 41 and the sub gate wiring 43 is a direction orthogonal to the X direction.
The gate connecting portion 4C is made of a metal-based wiring material having a low electric resistance, and the outer peripheral side gate wiring 40 is configured as the high resistance wiring portion 4B except for the strip portion 402 where the gate connecting portion 4C is provided. There is.

In this configuration, the gate control signal input from the gate pad portion GP is rapidly propagated from the gate connection portion 4C to the main gate wiring 41 and the sub gate wiring 43, which are the low resistance wiring portion 4A, and is located in each lower layer. It is input to the gate electrode 10 of the transistor cell T. At this time, as shown in the figure, since the signal can be sequentially propagated from the main gate wiring 41 and the sub gate wiring 43 to both sides, the switching timing is advanced in the central portion of the cell region 3.
On the other hand, since the low resistance wiring portion 4A is not connected to the outer peripheral side gate wiring 40 on the two sides located outside the sub gate wiring 43, a delay occurs in the switching timing in the peripheral portion of the cell region 3. As a result, the turn-off current concentration area A is formed in the peripheral portion of the cell region 3, and the same effect of relaxing the temperature distribution is obtained.

(Embodiment 6)
A sixth embodiment of the semiconductor device 1 will be described with reference to FIG.
This embodiment is a modification of the fifth embodiment, and one end of the main gate wiring 41 and the plurality of sub-gate wirings 43 is configured as a high resistance wiring portion 4B. The other basic configuration of the semiconductor device 1 is the same as that of the fifth embodiment, and the description thereof is omitted. The difference will be mainly described below.

In the fifth embodiment, the entire main gate wiring 41 is configured as the low resistance wiring portion 4A, but the extended end portion 411 connected to the outer peripheral side gate wiring 40 may be configured as the high resistance wiring portion 4B. Good. Similarly, with respect to the sub gate wiring 43, the extended end portion 431 connected to the outer peripheral side gate wiring 40 can be configured as the high resistance wiring portion 4B.

With this configuration, the signal propagation is delayed even on one side where the main gate wiring 41 and the sub gate wiring 43 are connected to the outer peripheral side gate wiring 40. As a result, the turn-off current concentrated area A having a substantially U shape is formed in the peripheral portion of the cell region 3, and the same effect of relaxing the temperature distribution can be obtained.

(Embodiment 7)
A seventh embodiment of the semiconductor device 1 will be described with reference to FIG.
The present embodiment is a modification of the fifth embodiment, and the arrangement of the gate pad portion GP is changed, and both ends of the main gate wiring 41 and the plurality of sub gate wirings 43 are configured as the high resistance wiring portion 4B. .. The other basic configuration of the semiconductor device 1 is the same as that of the fifth embodiment, and the description thereof is omitted. The difference will be mainly described below.

In the fifth embodiment, the gate pad portion GP is arranged outside the cell region 3 and adjacent to the center portion of one side, but it may be arranged in the center of the cell region 3. In that case, in the main gate wiring 41, a pair of extended end portions 411 extending from both sides of the gate pad portion GP in a direction orthogonal to the X direction are connected to the outer peripheral side gate wirings 40 facing each other. The pair of extending end portions 411 is configured as the high resistance wiring portion 4B. Similarly, with respect to the plurality of sub gate wirings 43, the extended end portions 431 on both end sides connected to the outer peripheral side gate wiring 40 can be configured as the high resistance wiring portion 4B.

Further, the plurality of sub gate wirings 43 are respectively provided with branch wirings 44 that branch from an intermediate portion on the side facing the main gate wiring 41. Each branch wiring 44 extends in the X direction toward the gate pad portion GP and is directly connected to both sides of the gate pad portion GP. Each branch wiring 44 can be configured as a low resistance wiring portion 4A.

With this structure, a signal propagation delay occurs on the two sides where the main gate wiring 41 and the sub gate wiring 43 are connected to the outer peripheral side gate wiring 40. As a result, the turn-off current concentration area A is formed over the entire periphery of the cell region 3, and the same effect of relaxing the temperature distribution can be obtained.

(Embodiment 8)
An eighth embodiment of the semiconductor device 1 will be described with reference to FIG.
This embodiment is a modification of the first embodiment, and the arrangement of the gate pad portion GP and the arrangement direction of the gate wiring portion 4 are changed. The other basic configuration of the semiconductor device 1 is the same as that of the first embodiment, and the description thereof is omitted. The difference will be mainly described below.

In the first embodiment, the gate pad portion GP is arranged outside the cell region 3 adjacent to the center portion of one side thereof, but may be arranged outside the corner portion of the cell region 3. In that case, the main gate wiring 41 is arranged in the diagonal direction of the cell region 3, and the direction of the trench of the transistor cell T is also the diagonal direction. The main gate wiring 41 becomes a part of the outer peripheral side gate wiring 40, and is connected to the gate pad portion GP via the gate connecting portion 4C composed of the corner portion 403 made of a metal-based wiring material having a low electric resistance.
Branch wirings 42 are provided on both sides of the main gate wiring 41 and are connected to the inside of the outer peripheral side gate wiring 40. The outer peripheral side gate wiring 40 and the branch end portion 421 of the branch wiring 42 are configured as a high resistance wiring portion 4B, and the branch wiring 42 and the main gate wiring 41 excluding the branch end portion 421 are configured as a low resistance wiring portion 4A. ..

With such a configuration as well, the turn-off current concentration area A is formed over the entire peripheral portion of the cell region 3, so that the same effect of relaxing the temperature distribution can be obtained.

(Embodiment 9)
A ninth embodiment of the semiconductor device 1 will be described with reference to FIG.
The present embodiment is a modification of the second embodiment, and the outer shape of the semiconductor device 1 is changed. The other basic configuration of the semiconductor device 1 is the same as that of the second embodiment, and the description thereof is omitted. The difference will be mainly described below.

In the second embodiment, the semiconductor layer 20 of the semiconductor device 1 and the semiconductor substrate 2 below the semiconductor layer 20 have a rectangular shape. However, the substrate shape is not limited to a rectangular shape, and may be an arbitrary shape, for example, a quadrangle or larger polygon. It can be shaped. Here, for example, the semiconductor device 1 has a semiconductor layer 20 formed on an octagonal semiconductor substrate 2, and the cell region 3 also has an octagonal shape.

Also in the present embodiment, the gate pad portion GP is arranged adjacent to the central portion of one side of the octagon, and the main gate wiring 41 is connected via the gate connecting portion 4C. The branch wirings 42 branching on both sides of the main gate wiring 41 extend in parallel to each other in the direction orthogonal to the main gate wiring 41, and the branch end portions 421 of the branch wirings 42 are on two sides of the facing outer side gate wiring 40. Connected to the inside. The outer peripheral side gate wiring 40 and the branch end portion 421 of the branch wiring 42 are configured as a high resistance wiring portion 4B, and the branch wiring 42 and the main gate wiring 41 excluding the branch end portion 421 are configured as a low resistance wiring portion 4A. ..

With such a configuration as well, the turn-off current concentration area A is formed over the entire peripheral portion of the cell region 3, so that the same effect of relaxing the temperature distribution can be obtained.

The present invention is not limited to the above-described embodiments, and can be applied to various embodiments without departing from the spirit of the invention. For example, although an example in which a semiconductor device is applied to a power conversion device as a switching element has been shown, the semiconductor device can be used for any application other than this.
Further, in each of the above-described embodiments, the example in which the trenches of the transistor cells T are arranged in a stripe shape in the cell region 3 of the semiconductor device 1 has been described, but the present invention is not limited to this, and the trenches may be arranged in a lattice shape. Good. Although the transistor cell T is configured as a vertical MOSFET having a trench, it may be an IGBT or may be a planar lateral MOSFET or IGBT.
Further, the wiring shape of the gate wiring portion 4 is not limited to the illustrated example, and the shape, positional relationship, etc. in which the main gate wiring 41 and the branch wiring 42 or the sub gate wiring 43 are combined can be changed as appropriate. Further, the sub gate wiring 43 may be connected to the main gate wiring 41.

DESCRIPTION OF SYMBOLS 1 semiconductor device 2 semiconductor substrate 21 main surface 3 cell region 4 gate wiring portion 40 outer peripheral side gate wiring 41 main gate wiring 42 branch wiring 4A low resistance wiring portion 4B high resistance wiring portion

Claims (9)

On the main surface (21) side of the semiconductor substrate (2), a cell region (3) in which a plurality of transistor cells (T) are arranged side by side, and a gate wiring part (10) connected to the gate electrode (10) of the transistor cell (3). A semiconductor device (1) comprising: 4) and a gate pad portion (GP) for applying a gate potential to the gate electrode via the gate wiring portion,
The gate wiring portion has a low resistance wiring portion (4A) and a high resistance wiring portion (4B) having higher electric resistance than the low resistance wiring portion,
The high resistance wiring part is arranged in a region along the outer peripheral edge of the cell region, the low resistance wiring part is inside the region in which the high resistance wiring part is arranged, and in the center of the cell region. A semiconductor device arranged in a region including a portion. The gate wiring portion includes an outer peripheral side gate wiring (40) arranged in the peripheral portion of the cell region and a plurality of inner peripheral side gate wirings (41, 42) connected inside the outer peripheral side gate wiring. Becomes
The inner peripheral side gate wiring is configured as the low resistance wiring portion except at least a part connected to the outer peripheral side gate wiring,
The semiconductor device according to claim 1, wherein the outer peripheral side gate wiring is configured as the high resistance wiring portion except at least a region adjacent to the gate pad portion. The inner peripheral side gate wiring is branched from a strip-shaped main gate wiring (41) connected to the gate pad portion and arranged in the central portion of the cell region and a plurality of locations in the longitudinal direction of the main gate wiring. The semiconductor device according to claim 2, further comprising a plurality of branch wirings (42) connected to the outer peripheral side gate wiring. The semiconductor device according to claim 3, wherein the plurality of branch wirings have branch end portions (421) connected to the outer peripheral side gate wiring as the high resistance wiring portions. The plurality of branch wirings are arranged in parallel in a direction orthogonal to the longitudinal direction of the main gate wiring, and the wiring pitch (P1) of the plurality of branch wirings adjacent to each other in the central portion of the cell region is outside thereof. It is formed smaller than the wiring pitch (P2),
The semiconductor device according to claim 3, wherein a wiring width (W1) of the main gate wiring is formed wider than a wiring width (W2) of the branch wiring and the outer peripheral side gate wiring. The inner peripheral side gate wiring is connected to the gate pad portion and is connected to the strip-shaped main gate wiring (42) arranged in the central portion of the cell region and the gate pad portion or the main gate wiring, The semiconductor device according to claim 2, further comprising one or more sub-gate wirings (43) arranged in parallel with the main gate wirings. 7. The semiconductor substrate has a polygonal shape of a quadrangle or more, and the outer peripheral side gate wiring and the inner peripheral side gate wiring are arranged line-symmetrically with respect to the main gate wiring. The semiconductor device according to item 1. 8. The gate pad portion is arranged inside the outer peripheral side gate wiring in the cell region, and the inner peripheral side gate wiring is directly connected to the gate pad portion. 2. The semiconductor device according to item 1. The gate pad portion is arranged outside the cell region and is connected to the inner peripheral side gate wiring via a gate connecting portion (4C) adjacent to the gate pad portion and made of a low resistance wiring material. The semiconductor device according to claim 2, which is connected.