JP2010010401A - Horizontal igbt and motor controller using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the point at issue that in a multi-emitter horizontal IGBT, a gate at a central part is farther at a distance from a collector than an outer peripheral part, a transport factor of a hole is small, and a reduction of an on-voltage is difficult. <P>SOLUTION: When a distance between the collector and an emitter is L<SB>CE</SB>, and a diffusion coefficient of minority carriers is D, a conditional expression of a lifetime τ is set to τ>L<SB>CE</SB><SP>2</SP>/(5.29×D), and also a surface concentration of a collector layer is set to ≤5×10<SP>17</SP>/cm<SP>3</SP>. The holes implanted from a p collector can come to reach a p channel layer along a current path from all emitter n<SP>+</SP>layers without impairing a high-speed property of a turn-off required for an inverter IC, and a current flows uniformly inside the IGBT, thereby reducing the on-voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a lateral IGBT (Insulated Gate Bipolar Transistor) having a collector, an emitter, and a gate on the same plane, and a motor control device using the IGBT.

  In various electronic devices such as home appliances and OA devices, it is important to realize a small size and high functionality of the power control unit at low cost. In response to these demands, an intelligent power IC has been developed. The intelligent power IC integrates a power element at the output stage, a drive circuit thereof, a protection function such as overcurrent and overtemperature, and an interface function with a microcomputer. This makes it possible to reduce the size and cost by significantly reducing the number of parts as compared with a circuit combining conventional disk components.

  One-chip inverter ICs, which are one type of intelligent power ICs, can be built in a controlled motor by reducing the size and the number of parts by making them into one chip.

  By the way, in DC140V or more which rectified alternating current AC100V, it is desirable to use IGBT in order to reduce the voltage (ON voltage) which generate | occur | produces when an electric current is sent through a switching element, and to reduce conduction | electrical_connection loss. Further, when a plurality of IGBTs are integrated on one chip, it is necessary to adopt an SOI (Silicon On Insulator) structure or a dielectric isolation structure in which each element is surrounded by an oxide film.

  In general, an IGBT manufactured as an individual device has a vertical structure in which a gate and an emitter are formed on the same plane, but a collector is formed on the opposite surface (back surface). On the other hand, the IGBT integrated in the IC adopts a lateral structure having a collector, an emitter, and a gate on the same plane. The structure of the lateral IGBT is disclosed in, for example, Patent Documents 1 to 3 and the like.

JP-A-3-226291 JP-A-8-32059 JP-A-9-121046

  A switching element for an inverter is required to have low switching loss as well as conduction loss. Patent Document 1 describes that lifetime control is performed by an electron beam as a means for reducing the turn-off loss among the switching losses.

  By the way, in order to reduce the on-voltage of the IGBT, a structure in which the source width of the emitter is increased, that is, a plurality of gates may be provided. However, since current flows in the lateral direction in the lateral IGBT, the gate at the central portion is farther from the collector than the outer peripheral portion and the hole arrival rate is small in the case of conventional electron beam irradiation. For this reason, even if a plurality of gates are provided, the central portion does not operate, and the on-voltage cannot be improved.

  An object of the present invention is to improve the on-voltage by making the current flowing inside the lateral IGBT uniform and allowing the current equivalent to that of the left and right gate regions to flow in the central gate region.

In one aspect of the present invention, a first semiconductor layer of a first conductivity type and a plurality of second semiconductors of a second conductivity type provided in the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer. And a plurality of first conductivity type third semiconductor layers having an impurity concentration higher than that of the second semiconductor layer, and provided on the surfaces of the first, second, and third semiconductor layers. And a plurality of second conductivity type fourth semiconductors provided in the first semiconductor layer and spaced apart from the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer. In a lateral IGBT having a layer, an emitter electrode ohmically connected to the second and third semiconductor layers, and a collector electrode ohmically connected to the fourth semiconductor layer, the emitter electrode, the collector electrode, and the gate electrode are in the same plane , The distance between collector and emitter is L _CE When the minority carrier diffusion coefficient is D, the minority carrier lifetime τ of the first semiconductor layer is
τ> L _CE ² /5.29×D
In addition, the surface concentration of the fourth semiconductor layer is 5 × 10 ¹⁷ / cm ³ or less.

In one desirable embodiment of the present invention, the breakdown voltage is 500 V or more, the minority carrier lifetime of the first semiconductor layer is 0.38 μs or more, and the surface concentration of the fourth semiconductor layer is 5 × 10 ^17. This is a lateral IGBT of / cm ³ or less.

  In a preferable application example of the present invention, the lateral IGBT has a lateral diode in which an anode electrode and a cathode electrode are in the same plane, and the lateral IGBT and the lateral diode are used as upper and lower arm switching elements and flywheel diodes. One or more phases are integrated on one chip to constitute a motor control device.

  According to a preferred embodiment of the present invention, minority carriers injected from the collector can reach the channel layer along the current path from all the emitter layers without deteriorating the high-speed turn-off required for the inverter IC. Thus, the current flows uniformly inside the IGBT, and the on-voltage can be reduced.

  Other objects and features of the present invention will be made clear in the embodiments described below.

  FIG. 1 is a functional block diagram of a one-chip inverter IC which is one type of intelligent power IC suitable for application of the present invention.

  The one-chip inverter 101 is an IC in which an inverter main circuit including a switching element 102 and a flywheel diode 103 and its control circuit are integrated on one chip. The control circuit includes upper and lower arm drive circuits 104 and 105, a level shift circuit 106 that transmits a drive signal from the bottom to the upper arm, a high-voltage side power supply 107, a protection circuit 108 for overcurrent and overheat, and a command signal from the microcomputer 109. There is a logic circuit 110 that generates a drive signal. Thus, by making it into one chip, it became possible to incorporate in the motor 111 by downsizing and reducing the number of parts.

  By the way, it is desirable to use an IGBT in order to reduce the conduction loss by reducing the voltage (ON voltage) generated when a current is passed through the switching element 102 at DC 140 V or higher obtained by rectifying AC 100 V of the AC power supply 112 by the rectifier circuit 113. . As described above, when a plurality of IGBTs are integrated on one chip, it is necessary to adopt an SOI structure or a dielectric isolation structure in which each element is surrounded by an oxide film.

  An IGBT integrated in an IC has a lateral structure having a collector, an emitter, and a gate on the same plane.

  FIG. 2 is a cross-sectional view of a lateral IGBT according to the first embodiment of the present invention. An oxide film (SiO 2) 2 is provided on a substrate 1 serving as a support, and an n − layer 3 is further provided thereon. A plurality of p channel layers 4 a and 4 b are provided in the n − layer 3. A plurality of n + emitter layers 5a, 5b, 5c, 5d are provided in the p channel layers 4a, 4b. Further, p + layers 6a and 6b are provided in the p channel layers 4a and 4b. The p + layers 6a and 6b are provided for the purpose of reducing the resistance of the p channel layer below the n + layer and preventing latch-up. An emitter electrode 13 is ohmically connected to the n + layers 4a, 4b, 4c, 4d and the p + layers 6a, 6b. N layers 11a and 11b are provided apart from the p channel layers 4a and 4b. In the n layers 11a and 11b, p collector layers 12a and 12b are provided. The n layers 11a and 11b are provided in order to prevent punch-through and ensure a breakdown voltage. The collector electrode 14a is ohmically connected to the p collector layer 12a, and the collector electrode 14b is ohmically connected to the p collector layer 12b. A gate oxide film 7a is provided on the surface of the p channel layer 4a, n + layer 5a, and n− layer 3, and a gate electrode 8a is provided on the gate oxide film 7a to form the left gate portion in the figure. . A gate oxide film 7c is provided on the surface of the p channel layer 4b, the n + layer 5d, and the n− layer 3, and a gate electrode 8c is provided on the gate oxide film 7c to form the right gate portion in the figure. . A gate oxide film 7b is formed on the p channel layer 4a, n + layer 5b, n− layer 3 surface, p channel layer 4b and n + layer 5c, and a gate electrode 8b is formed thereon to form a gate in the center of the figure. is doing. An oxide film 10a thicker than the gate oxide film is provided between the p channel layer 4a and the p collector layer 12a. Similarly, an oxide film 10b is provided between the p channel layer 4b and the p collector layer 12b. The gate electrodes 8a, 8b, 8c and the emitter electrode 13 are insulated by insulating films 9a, 9b, 9c.

When a positive voltage is applied to the collector with respect to the emitter and a voltage higher than the threshold voltage is applied to the gate, inversion layers are formed in the p channel layers 4a and 4b under the gate oxide films 7a, 7b and 7c, and the emitter n + layer 5a. , 5b, 5c, 5d flow into the n− layer 3. Holes are injected from the p collector layers 12a and 12b by these electrons. In this way, holes are injected, the resistance of the high resistance n− layer 3 decreases (conductivity modulation), and the on-voltage of the IGBT decreases. In the lateral IGBT having a plurality of gates as shown in FIG. 2, the distance between the emitter layer and the collector layer differs depending on the location of the emitter layer as shown in L _CE (A) and L _CE (B) in FIG. In the case of FIG. 2, when the conventional lifetime control is used, the hole can reach the route of the solid line A, but cannot reach the route of the dotted line B, and disappears due to recombination with electrons in the middle. Therefore, the current density is low at the central gate (below the oxide film 7b), and the on-voltage cannot be reduced.

By the way, the holes injected from the p collector layer are p (x) = p (x = 0) × exp (−x / Lp) with respect to the distance x from the collector layer (1).
Here, the diffusion length Lp of the hole in the n − layer 3 can be expressed by the following equation (2).

Lp = √ (Dp × τp) (2)
Here, Dp is the hole diffusion coefficient, and τp is the lifetime of the hole in the n− layer 3.

  The hole diffusion coefficient Dp can be expressed by the following equation (3) using Einstein's relational expression.

Dp = k × T / q × μp (3)
Here, k is the Boltzmann coefficient, T is the absolute temperature, q is the elementary charge, and μp is the hole mobility.

  The lifetime in which the conductivity modulation sufficiently occurs with respect to the collector-emitter distance Lce and the on-voltage can be reduced is derived from the equations (1) to (3).

  If the hole does not reach 1/10 or more of the initial p (x = 0), conductivity modulation does not occur sufficiently. Therefore, it is necessary to satisfy the relationship of Lce <2.3 × Lp from the equation (1). Furthermore, the conditional expression (4) of the lifetime τp of the hole can be derived from the expression (2).

τp> Lce ² /(2.3 ² × Dp) (4)
By the way, in the n type, as described above, the minority carriers are holes, but in the p type, the minority carriers are electrons. Therefore, by generalizing and expressing the minority carrier lifetime by τ and the minority carrier diffusion coefficient by D, the equation (4) can be generalized as the following equation (5).

τ> Lce ² /(5.29×D) (5)
As a specific example, a case of a 500V withstand voltage product will be considered. From the breakdown voltage, Lce = 50 μm or more is necessary. Further, as the T = 300k, since μp ⁼ 480cm 2 / Vsec, from equation (3), a Dp = 0.12 cm. Therefore, it is sufficient that τp> 0.38 μs or more. That is, a lateral IGBT having a breakdown voltage of 500 V or more, a minority carrier lifetime of the first semiconductor layer of 0.38 μs or more, and a surface concentration of the fourth semiconductor layer of 5 × 10 ¹⁷ / cm ³ or less. means.

  By the way, if lifetime control is not performed, current continues to flow in the IGBT due to carriers remaining in the n− layer. This current is called tail current. Since this tail current continues to flow even when the collector voltage reaches the power supply voltage, the loss due to the product of the tail current and the collector voltage occupies a large proportion of the turn-off loss in the IGBT. For this reason, in order to reduce inverter loss, it is necessary to reduce the tail by a method other than lifetime control. In order to reduce the tail current, the carriers remaining in the n − layer may be reduced. As a reduction method, it has been found that the concentration of the p collector layer may be controlled.

FIG. 3 is a graph showing the relationship between the p collector surface concentration of the lateral IGBT and the turn-off time. For an inverter, the turn-off time needs to be 1.0 μs or less, and in this case, the p collector surface concentration needs to be 5 × 10 ¹⁷ / cm ³ .

  The means for reducing the turn-off loss by lifetime control such as an electron beam has a problem that the turn-off loss increases when the lifetime becomes high because the lifetime becomes long. In the method of reducing the turn-off loss by controlling the concentration of the p collector layer as in this embodiment, since the amount of holes injected from the p collector is determined by the concentration difference, the temperature dependence is small and the increase in turn-off at high temperatures is small. There is a feature.

  The above embodiment can be summarized with the reference numerals in FIG. 2 as follows.

A first semiconductor layer (3) of the first conductivity type (n−);
A plurality of second semiconductor layers (4a, 4b) of the second conductivity type (p) provided in the first semiconductor layer (3) and having an impurity concentration higher than that of the first semiconductor layer (3);
A plurality of first semiconductor type (n) third semiconductor layers (5a, 5b,...) Provided in the second semiconductor layer (4a, 4b) and having a higher impurity concentration than the second semiconductor layers (4a, 4b). 5c, 5d),
A plurality of MOS (Metal Oxide Semiconductor) structures provided on the surfaces of the first, second, and third semiconductor layers;
A plurality of second conductivity types provided in the first semiconductor layer (3) and provided away from the second semiconductor layers (4a, 4b) and having a higher impurity concentration than the first semiconductor layer (3). p) fourth semiconductor layer (12a, 12b);
An emitter electrode (13) that is in ohmic contact with the second and third semiconductor layers (4a, 4b, 5a to 5d);
Having collector electrodes (14a, 14b) in ohmic contact with the fourth semiconductor layers (12a, 12b);
In a lateral IGBT in which an emitter electrode (13), a collector electrode (14a, 14b), and a gate electrode (8a to 8c) are in the same plane,
When the collector-emitter distance is L _CE and the minority carrier diffusion coefficient is D, the minority carrier lifetime τ of the first semiconductor layer (3) is:
τ> L _CE ² /(5.29×D)
And the lateral concentration of the fourth semiconductor layer (12a, 12b) is 5 × 10 ¹⁷ / cm ³ or less.

  FIG. 4 is a cross-sectional view of a lateral IGBT according to the second embodiment of the present invention. In addition to the first embodiment, n layers 20a and 20b are provided for the p channel layers 4a and 4b. As a result, the n-layer resistance between the p-channel layers 4a and 4b can be prevented from increasing due to the pinch-off and the on-voltage can be prevented from increasing, so that the on-voltage can be further reduced than in the first embodiment.

FIG. 5 is a cross-sectional view of a lateral IGBT according to the third embodiment of the present invention. In addition to the first embodiment, p + layers 15a and 15b are provided. The p + layers 15a and 15b are provided intermittently with respect to the long side direction (depth direction in FIG. 5) of the lateral IGBT. The collector electrodes 14a and 14b are in contact with both the p collector layers 12a and 12b and the p + layers 15a and 15b. Since the p collector layers 12a and 12b have a low surface concentration of 5E ¹⁷ / cm ³ or less, the contact resistance increases. For this reason, the p + layers 15a and 15b are provided to reduce the contact resistance. However, if all the collector electrodes are in contact with the p + layers 15a and 15b, the number of holes injected from the collector increases and the turn-off loss increases. Therefore, the p + layers 15a and 15b are intermittently provided in the long side direction (depth direction in FIG. 5), and the collector electrodes 14a and 14b are provided on both the p + layers 15a and 15b and the p collector layers 12a and 12b. I try to make contact.

  By the way, in the lifetime control by the electron beam, since the element other than the IGBT, for example, a flywheel diode is irradiated in the monolithic structure, the speed of the diode is also increased. Therefore, when an inverter IC is manufactured using the lateral IGBT of the present invention, a diode speed-up means is necessary.

  FIG. 6 is a sectional view and a partial depth structure diagram of a first embodiment of a diode integrated with a lateral IGBT of the present invention. An oxide film (SiO 2) 2 is provided on a substrate 1 serving as a support, and an n − layer 3 is provided thereon. A p anode layer 30 is provided in the n − layer 3. Apart from the p anode layer 30, n + cathode layers 35 a and 35 b are provided. A gate oxide film 31a is provided on the surface of the p anode layer 30n-layer 3, and an electrode 32a is provided thereon. An anode electrode 37 is ohmically connected to the p anode layer 30. Cathode electrodes 36a and 36b are connected to the cathode n + layers 35a and 35b. Thick oxide films 34a and 34b are provided between the anode p layer 30 and the cathode n + layers 35a and 35b. Insulating films 33a and 33b are provided on the electrodes 32a and 32b. The electrodes 32a and 32b are at the same potential as that of the anode electrode 37 and serve as a field plate.

  The diode switching loss is due to the recovery current that flows during recovery. For this reason, it is necessary to reduce the recovery loss in order to reduce the loss of the diode. It has been found that there is a relationship between the anode p layer concentration and the recovery current when the lifetime is not controlled.

FIG. 7 is a graph showing the relationship between the p-anode layer surface concentration of the lateral IGBT and the peak value of the recovery current normalized by the forward current. By reducing the surface concentration of the p anode layer, the recovery current can be reduced without controlling the lifetime. In the inverter IC, since the recovery current needs to be ½ or less of the forward current, the p anode layer surface concentration needs to be 5E ¹⁷ / cm ³ or less.

  FIG. 8 is a sectional structural view of a second embodiment of the diode integrated with the lateral IGBT of the present invention. The p anode layer is divided into a plurality of p layers 40a, 40b, and 40c. Further, the anode electrode is in contact with the n-layer 3 as well as the p layers 40a, 40b and 40c. The contact portion between the anode electrode and the n− layer 3 is in Schottky contact. By the way, the peak value of the recovery current is determined by the carriers accumulated in the vicinity of the p anode. By dividing the p layer into a composite structure with a Schottky junction, carriers accumulated in the vicinity of the p anode can be reduced, and the recovery current can be reduced as compared with the diode of the first embodiment.

  FIG. 9 is a sectional view and a partial depth structure diagram of a third embodiment of a diode integrated with a lateral IGBT of the present invention. In order to show the depth direction of the diffusion layer of the anode, the anode electrode 37 is omitted. In addition to the second embodiment, p + layers 41a, 41b and 41c are provided in the p layers 40a, 40b and 40c. The p + layers 41a, 41b, and 41c are provided intermittently in the long side direction (depth direction in FIG. 9) of the diode. Thereby, the contact resistance between the p layers 40a, 40b, and 40c and the anode electrode 37 is reduced. Further, when the p + layers 41a, 41b, and 41c are in contact with the anode electrode 37 over the entire surface, the number of holes injected increases and the recovery current increases. Therefore, the p + layers 41a, 41b, and 41c are arranged in the long side direction of the diode (the depth direction in FIG. 9). ) Is provided intermittently.

According to the above preferred embodiment of the present invention, in the lateral IGBT, when the distance between the collector and the emitter is L _CE and the diffusion coefficient of minority carriers is D, the conditional expression of lifetime τ is
τ> L _CE ² /(5.29×D)
The surface concentration of the collector layer was set to 5 × 10 ¹⁷ / cm ³ or less. As a result, minority carriers injected from the collector can reach the channel layer along the current path from all the emitter layers without impairing the high-speed turn-off required for the inverter IC. It can flow uniformly and reduce the on-voltage.

The functional block diagram of the one-chip inverter IC suitable for applying the lateral type IGBT by this invention. 1 is a cross-sectional structure diagram of a lateral IGBT according to a first embodiment of the present invention. The graph which shows the relationship between the p collector surface density | concentration of a lateral IGBT, and turn-off time. The cross-section figure of horizontal IGBT by 2nd Example of this invention. The cross section and partial depth structure figure of the horizontal type IGBT by the 3rd example of the present invention. 1 is a cross-sectional structural view of a first embodiment of a diode integrated with a lateral IGBT of the present invention. FIG. The graph which shows the relationship of the peak value of the recovery current normalized by the p anode layer surface density | concentration of the horizontal IGBT, and the forward current. FIG. 3 is a sectional structural view of a second embodiment of a diode integrated with a lateral IGBT of the present invention. The cross section and partial depth structure figure of the 3rd Example of the diode integrated with the horizontal type IGBT of this invention.

Explanation of symbols

  1: support substrate, 2: oxide film, 3: n− layer, 4: p channel layer, 5: n + layer, 6: p + layer, 7: gate oxide film, 8: gate electrode, 9: insulating film, 10 : Thick oxide film, 11: n layer, 12: p collector layer, 13: emitter electrode, 14: collector electrode, 20: n layer, 30: p anode layer, 31: gate oxide film, 32: electrode, 33: insulation Film: 34: thick oxide film, 35: n + cathode layer, 36: cathode electrode, 37: anode electrode, 40: p anode layer, 41... P + layer.

Claims (9)

A first semiconductor layer of a first conductivity type;
A plurality of second conductivity type second semiconductor layers provided in the first semiconductor layer and having an impurity concentration higher than that of the first semiconductor layer;
A plurality of third semiconductor layers of a first conductivity type provided in the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer;
A plurality of MOS structures provided on the surface of the first, second, and third semiconductor layers;
A plurality of second conductivity type fourth semiconductor layers provided in the first semiconductor layer and spaced apart from the second semiconductor layer and having a higher impurity concentration than the first semiconductor layer;
An emitter electrode in ohmic contact with the second and third semiconductor layers;
Having a collector electrode in ohmic contact with the fourth semiconductor layer;
In a lateral IGBT in which an emitter electrode, a collector electrode, and a gate electrode are in the same plane,
When the collector-emitter distance is L _CE and the minority carrier diffusion coefficient is D, the minority carrier lifetime τ of the first semiconductor layer is
τ> L _CE ² /(5.29×D)
And the lateral concentration of the fourth semiconductor layer is 5 × 10 ¹⁷ / cm ³ or less.   2. The lateral IGBT according to claim 1, wherein the second semiconductor layer is surrounded by a fifth semiconductor layer of the first conductivity type having a higher concentration than the first semiconductor layer. A first semiconductor layer of a first conductivity type;
A plurality of second conductivity type second semiconductor layers provided in the first semiconductor layer and having an impurity concentration higher than that of the first semiconductor layer;
A plurality of third semiconductor layers of a first conductivity type provided in the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer;
A plurality of MOS structures provided on the surface of the first, second, and third semiconductor layers;
A plurality of second conductivity type fourth semiconductor layers provided in the first semiconductor layer and spaced apart from the second semiconductor layer and having a higher impurity concentration than the first semiconductor layer;
An emitter electrode in ohmic contact with the second and third semiconductor layers;
Having a collector electrode in ohmic contact with the fourth semiconductor layer;
In a lateral IGBT in which an emitter electrode, a collector electrode, and a gate electrode are in the same plane,
The breakdown voltage is 500 V or more, the minority carrier lifetime of the first semiconductor layer is 0.38 μs or more, and the surface concentration of the fourth semiconductor layer is 5 × 10 ¹⁷ / cm ³ or less. Horizontal IGBT.   2. The semiconductor device according to claim 1, further comprising a plurality of second conductivity type fifth semiconductor layers provided in the fourth semiconductor layer and having an impurity concentration higher than that of the fourth semiconductor layer, wherein the collector electrode includes the fourth semiconductor layer. And a fifth semiconductor layer in ohmic connection.   5. The lateral IGBT according to claim 4, wherein a fifth semiconductor layer shorter than the length of the fourth semiconductor layer is provided intermittently along the long side direction.   6. The lateral IGBT according to claim 1 and a lateral diode in which an anode electrode and a cathode electrode are on the same plane. The lateral IGBT and the lateral diode are used as an upper and lower arm switching element and a flywheel diode. A motor control device characterized by integrating phases and more into one chip. 7. The motor control device according to claim 6, wherein the surface concentration of the anode layer of the diode is 5 × 10 ¹⁷ / cm ³ or less.   8. The motor control device according to claim 7, wherein the diode has an anode electrode in contact with the p anode layer and the n− layer.   9. The diode according to claim 8, wherein the p anode layer is composed of a p + layer having a higher concentration than the p layer, and the p + layer shorter than the length of the p layer is intermittently provided along the long side direction. A motor control device.

Images