JPH1140818A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a semiconductor device in both the high-speed switching properties and high-output properties. SOLUTION: This device is equipped with an insulating layer 2 formed on a substrate 1, a high-resistance n<-> -type active layer 3 formed on the insulating layer 2, an n-type buffer layer 4 formed on the n<-> -type active layer 3, a p-type drain layer 21 formed on the surface of the buffer layer 4, a p<+> -type contact layer 22 which is higher in impurity concentration than in the p-type drain layer 21 and formed on the p-type drain layer 21, a drain electrode 14 formed on the p-type drain layer 21 and the p<+> -type contact layer 22, a p-type base layer 6 formed on the surface of the n<-> -type active layer 3, an N<+> -type source layer 7 formed on the P-type base layer 6, a source electrode 15 formed on the n<+> -type source layer 7 and the p-type base layer 6, and a gate electrode 11 formed on the p-type base layer 6 sandwiched in between the n<+> -type source layer 7 and the n<-> -type active layer 3 through the intermediary of a gate oxide film 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a high withstand voltage, and more particularly to a semiconductor device using an SOI (Silicon On Insulator) substrate.

[0002]

2. Description of the Related Art In the field of power electronics, an IGBT (Insulate) having both the convenience of being able to drive a voltage by a gate and the high output characteristics of a bipolar transistor is known.
d Gate Bipolar Transistor) is widely used.
This IGBT has a power MOSF due to the aforementioned advantages.
It is possible to control a larger current than ET.

FIG. 14 is a plan view of an electrode-semiconductor interface position for showing the structure of this type of lateral IGBT.
FIG. 15 is a cross-sectional view taken along line 15-15 of FIG. 14 with electrodes attached. Similarly, in the present specification, a plan view is shown at an electrode-semiconductor interface position, and a cross-sectional view is shown with electrodes attached.

[0004] The lateral IGBT is on a silicon substrate 1, a SiO ₂ buried oxide film 2 and the high-resistance n- type active layer 3 are sequentially formed. A substantially striped n-type buffer layer 4 is selectively formed on the surface of the n − -type active layer 3 so as not to reach the buried oxide film 2, and a p-type emitter layer is formed on the surface of the n-type buffer layer 4. + Type drain layer 5 is selectively formed in a substantially striped shape.

The n− type active layer 3 has a dose of 1 × 1.
It is about 0 ¹² cm ^-2 . The n-type buffer layer 4 is formed by, for example, phosphorus ion implantation, and has a dose of 5 × 10 ^13.
About 2 × 10 ¹⁴ cm ⁻² . The dose of the p + type drain layer 5 is 1 × 10 ¹⁵ cm ⁻² or more, but may be about 8 × 10 ¹⁴ cm ⁻² .

On the surface of the n − -type active layer 3 different from the n-type buffer layer 4, a substantially striped p-type base layer 6 is formed.
Are formed selectively so as not to reach the buried oxide film 2,
On the surface of the p-type base layer 6, a low-resistance n + -type source layer 7 and a p + -type contact layer 8 are formed in a substantially striped shape.

The surface region from a part of the n-type buffer layer 4 to the vicinity of the p-type base layer 6 in the n − -type active layer 3 has LO
A COS oxide film 9 is formed, and the p-type base layer 6 extends from the end of the n − -type active layer 3 adjacent to the LOCOS oxide film 9.
A gate oxide film 10 is formed on the region up to a part of n + type source layer 7.

A gate electrode 11 is formed on the gate oxide film 10, and an S-side field plate 12 slightly extending from the gate electrode 11 toward the drain is formed on the LOCOS oxide film 9. Similarly, a D-side field plate 13 is formed on the LOCOS oxide film 9 near the n-type buffer layer 4.

A drain electrode 14 is formed on the p + -type drain layer 5 so as to be in contact with the D-side field plate 13. A source electrode 15 is formed on the n + -type source layer 7 and the p + -type contact layer 8.

When a positive voltage is applied to the gate electrode 11, electrons appear on the surface of the p-type base layer 6 immediately below the gate in proportion to the positive voltage, and the surface of the p-type base layer 6 is inverted to an electron region. I do. This inversion region becomes a channel, and short-circuits the n + -type source layer 7 and the n − -type active layer 3.

Here, when a positive voltage is applied to the drain electrode 14, electrons are supplied from the source electrode 15 and injected from the n + -type source layer 7 into the n − -type active layer 3 through the channel. As a result, holes are injected from the p + -type drain layer 5 into the n − -type active layer 3 via the n-type buffer layer 4. Due to the injection of holes, conduction modulation occurs in the n − -type active layer 3 in which electrons and holes are present at a high density and coexist at substantially the same density so as to cancel each other's charges. Becomes

Therefore, the electrons of the n− type active layer 3 flow to the drain electrode 14 via the p + type drain layer 5, and the holes of the n− type active layer 3 pass through the p type base layer 6 to the source electrode 15.
Flows to

At the time of turn-off, a positive gate voltage is removed from the gate electrode 11. As a result, the channel on the surface of the p-type base layer 6 immediately below the gate disappears, the n + -type source layer 7 and the n − -type active layer 3 are cut off, and electron injection is stopped. On the other hand, some of the holes in the n − -type active layer 3 are discharged to the source electrode 15 via the p-type base layer 6, and the remaining holes recombine with electrons and disappear. As a result, the horizontal IGBT is turned off.

[0014]

However, in the IGBT as described above, the injection of holes, which are minority carriers, into the n − -type active layer 3 causes conduction modulation and lowers the on-resistance. Even when the device is turned off to stop the injection of electrons, a current flows through the element while the accumulated holes are discharged, so that there is a problem that the switching speed is lower than that of the power MOSFET. Therefore, to increase the switching characteristics of the lateral IGBT, it is necessary to control the hole injection efficiency from the drain.

As methods for controlling the injection efficiency, for example, there are the following methods (a) to (c). (A) In this method, a part of the drain electrode 14 is brought into contact with the n − -type active layer 3. However, in this method, since holes are not sufficiently injected in the ON state, there is a problem that ON characteristics are deteriorated. (B) This is a method of increasing the dose of the n-type buffer layer 4, which will be described with reference to a curve N in FIG. A curve N indicates the ON voltage V when the dose of the n-type buffer layer 4 is changed.
7 shows a trade-off between f and the turn-off time Tf.
Although this method is effective for speeding up to about 500 ns as shown by the curve N, if a horizontal IGBT having a turn-off time Tf shorter than that is to be created,
Since the on-state voltage becomes extremely high when the dose of the n-type buffer layer 4 exceeds 1 × 10 ¹⁵ cm ⁻² , it is impractical. (C) This method is based on the disadvantage of the method (b), and reduces the dose of the p + -type drain layer 5 while keeping the dose of the n-type buffer layer 4 as it is. In this method, as shown by the curve P in FIG. 16 and FIG. 17, the turn-off time Tf can be shortened to about 300 ns, but if it is to be shorter, the surface concentration of the p + -type drain layer 5 needs to be reduced. Occurs. Surface concentration of 1 × 10 ¹⁹
When it is less than cm ^-3, it is difficult to make an ohmic contact, and there is a problem that a Schottky barrier is generated and the contact resistance is increased, so that the on-voltage Vf is increased.

As described above, the lateral IGBT has a problem that the turn-off time Tf is long. However, if an attempt is made to shorten the turn-off time Tf, there arises a problem that the on-voltage Vf increases. Further, the output characteristics are deteriorated due to the increase of the ON voltage Vf,
There is a problem that the operable current value is reduced. The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device having both high-speed switching characteristics and high-output characteristics.

[0017]

A semiconductor device according to the present invention comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a high-resistance first conductivity type active layer formed on the insulating layer. A first conductive type buffer layer formed on the surface of the first conductive type active layer; a second conductive type drain layer formed on the surface of the first conductive type buffer layer; A second conductivity type contact layer formed on the surface of the drain layer and having a higher impurity concentration than the second conductivity type drain layer;
A drain electrode formed on the conductivity type drain layer; a second conductivity type base layer formed on the surface of the first conductivity type active layer; and a first electrode formed on the surface of the second conductivity type base layer.
A conductive type source layer, a source electrode formed on the first conductive type source layer and on the second conductive type base layer, and sandwiched between the first conductive type source layer and the first conductive type active layer; A gate electrode provided on the second conductive type base layer via a gate insulating film.

Here, the second conductivity type contact layer is formed of the second conductive type contact layer.
The conductive type drain layer may be formed in an island shape along a direction substantially perpendicular to the current path. The second conductivity type contact layer may be formed in the second conductivity type drain layer in a stripe shape having a longitudinal direction substantially parallel to the current path.

The ratio obtained by dividing the surface area of the second conductivity type contact layer by the surface area of the second conductivity type drain layer may be in the range of 10 to 78%. The impurity concentration on the surface of the second conductivity type contact layer is set to 1 × 10 ¹⁹ cm.
^-3 or more, and the impurity concentration on the surface of the second conductivity type drain layer 21 may be defined to be in the range of 1 × 10 ¹⁸ cm ⁻³ to 3 × 10 ¹⁸ cm ⁻³ .

Therefore, according to the present invention, by taking the above measures, the second conductivity type drain layer having a low impurity concentration for reducing the hole injection efficiency and the contact resistance for preventing an increase in the contact resistance are provided. By providing the second conductive type contact layer having a high impurity concentration, the second conductive type contact layer can prevent an increase in on-voltage while improving the switching speed by the second conductive type drain layer. Accordingly, high-speed switching characteristics and high-output characteristics can be realized at the same time.

When the second conductivity type contact layer is formed in an island shape, the hole injection efficiency can be further reduced, and the hole discharge speed can be further increased.

Further, when the second conductivity type contact layer is formed in a stripe shape, high-speed switching characteristics and high output characteristics can be simultaneously realized with even better values.

Further, by setting the ratio obtained by dividing the surface area of the contact layer of the second conductivity type by the surface area of the drain layer of the second conductivity type within the range of 10 to 78%, switching characteristics and high output characteristics can be obtained. The balance can be optimized.

Further, the impurity concentration on the surface of the contact layer of the second conductivity type is specified to be 1 × 10 ¹⁹ cm ⁻³ or more, and the impurity concentration on the surface of the drain layer 21 of the second conductivity type is set to 1 × 10 ¹⁸ cm ^−3.
And 3 × 10 ¹⁸ cm ⁻³ , a standard in element design can be obtained.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a plan view showing a configuration of a horizontal IGBT according to a first embodiment of the present invention, and FIG.
14 is a sectional view taken along line 2-2 of FIG. 14, wherein the same reference numerals are given to the same parts as in FIG. 14 and FIG.
Here, different parts will be mainly described.

That is, in this embodiment, the hole injection efficiency is reduced and the contact resistance is prevented from increasing at the same time. Specifically, as shown in FIGS. 1 and 2, the p + -type drain layer is formed. Instead, the low impurity concentration p-type drain layer 21 is selectively formed on the surface of the n-type buffer layer 4, and is selectively formed on the surface of the p-type drain layer 21 and is higher than the p-type drain layer 21. And a p @ + -type contact layer 22 having an impurity concentration. FIG. 3 shows the impurity concentration distribution along the depth direction on the drain side.

Here, the p-type drain layer 21 is formed to a depth of 0.25 μm by, for example, boron ion implantation at a low dose (1 × 10 ¹⁴ cm ⁻² ), and the impurity concentration on the surface is substantially 2 μm. It is about × 10 ¹⁸ cm ^-3 .

The reason for setting the impurity concentration on the surface of the p-type drain layer 21 to 1 × 10 ^{18 to} 3 × 10 ¹⁸ cm ⁻³ is that n
When the surface impurity concentration of the p-type buffer layer 4 is about 1 × 10 ¹⁸ cm ⁻³ , the impurity concentration of the p-type drain layer is 1 × 10 ¹⁸ cm ^{−3.
If it is} smaller than ¹⁸ cm ^-3, the impurity concentration of the n-type buffer layer 4 will be lower than that of the n-type buffer layer 4, so that there is no point in providing the p-type drain layer 21. Also, the p-type drain layer 2
When the impurity concentration on the surface of 1 exceeds 3 × 10 ¹⁸ cm ^-3 ,
This is because the impurity concentration becomes substantially equal to that of the p-type contact layer 22, so that there is no need to provide the p-type drain layer 21 in the same manner.

The p + -type contact layer 22 is formed to a depth of 0.1 μm by, for example, boron ion implantation at a high dose (1 × 10 ¹⁵ cm ⁻² or more), and the impurity concentration on the surface is 1 × 10 ¹⁹ cm. ^-3 or more. Specifically, p +
The contact layer 22 is formed in a stripe shape along the side of the p-type drain layer 21 and the p + -type contact layer 22 that is away from the source electrode 15 in the contact region 23 to the drain electrode 14.

The reason why the impurity concentration on the surface of the p-type contact layer 22 is set to 1 × 10 ¹⁹ cm ⁻³ or more is that if the impurity concentration of the p-type contact layer 22 becomes less than 1 × 10 ¹⁹ cm ⁻³ , This is because the resistance increases.

The n-type buffer layer 4 is formed to a depth of 4 μm by, for example, ion implantation of phosphorus with a low dose (1.5 × 10 ¹⁴ cm ⁻² ), and the impurity concentration on the surface is substantially 1 ×. It is about 10 ¹⁸ cm ^-3 .

Next, the operation of such a horizontal IGBT will be described. In this lateral IGBT, the impurity concentration of the p-type drain layer 21 is made lower than that of the conventional p + -type drain layer 5 by controlling the amount of boron ions to be implanted.
The hole injection efficiency during operation is reduced. That is, the switching speed is improved by lowering the hole injection amount during operation to reduce the hole accumulation amount in the n − -type active layer 3 and shortening the hole discharge time when the switch is turned off. be able to.

On the other hand, in order to prevent an increase in contact resistance due to a decrease in the impurity concentration of the p-type drain layer 21, the p + -type contact layer 2 having a high impurity concentration and a low resistance is used.
2 are provided. Therefore, while the switching speed is improved by the p-type drain layer 21, the p + -type contact layer 2
With 2, the rise of the ON voltage can be prevented. That is, high-speed switching characteristics and high output characteristics can be realized simultaneously.

For example, FIG. 4 is a diagram showing a trade-off curve of a horizontal IGBT. This curve shows the surface area ratio of the p + -type contact layer 21 / p-type drain layer 22 on the horizontal axis,
The vertical axis represents the turn-off time Tf and the ON voltage Vf. As shown, the ON voltage Vf is reduced in proportion to the surface area of the p + -type contact layer 22, and the p-type drain layer 2
In turn, the turn-off time Tf is shortened in proportion to the surface area.

Here, referring to FIG. 4, by optimizing the surface area ratio of the p + -type contact layer 21 / p-type drain layer 22, ie, by setting it between 10 and 78%, switching characteristics and high output characteristics can be obtained. Is optimized, and a horizontal IGBT with an excellent trade-off can be realized.

As described above, according to the first embodiment,
By providing a low impurity concentration p-type drain layer 21 for lowering the hole injection efficiency and a high impurity concentration p @ + -type contact layer 22 for preventing an increase in contact resistance, the p-type drain layer 21 is formed. While the switching speed is improved by the layer 21, the rise of the on-state voltage can be prevented by the p @ + -type contact layer 22, so that the high-speed switching characteristic and the high output characteristic can be simultaneously realized. (Second Embodiment) FIG. 5 is a plan view showing a configuration of a horizontal IGBT according to a second embodiment of the present invention, and FIG.
FIG. 6 is a cross-sectional view taken along line 6-6 of FIG. 6. The same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and substantially the same parts are denoted by a subscript a, and detailed description thereof is omitted. The different parts will be mainly described. 5 is a sectional view taken along line 2-2 in FIG.
Is the same as the cross-sectional configuration shown in FIG.

That is, in the present embodiment, the pattern shapes of the p-type drain layer 21 and the p + -type contact layer 22 are optimized. Specifically, as shown in FIGS. By selectively forming ap + -type contact layer 22a along the current path in the p-type drain layer 21 of
The p + -type contact layer 22 has a comb-like shape as a whole. The p + -type contact layers 22 and 22a have the same impurity concentration, and the width and length of the p + -type contact layer 22a can be set arbitrarily.

With the above-described configuration, the hole injection efficiency can be reduced as compared with the first embodiment. Therefore, in addition to the effects of the first embodiment, a better value and a high-speed switching characteristic can be obtained. High output characteristics can be realized at the same time. (Third Embodiment) FIG. 7 is a plan view showing the configuration of a horizontal IGBT according to a third embodiment of the present invention, and FIG.
8 is a cross-sectional view taken along line 8-8 of FIG. 8, and the same parts as those in FIGS. 5 and 6 are denoted by the same reference numerals, detailed description thereof will be omitted, and different parts will be mainly described here. In addition, 6- of FIG.
The cross section taken along line 6 is the same as the cross section shown in FIG.

That is, in the present embodiment, the pattern shapes of the p-type drain layer 21 and the p + -type contact layer 22 are optimized. Specifically, as shown in FIGS. By extending the p-type drain layer 21 between the respective p + -type contact layers 22a to the inside of the stripe-shaped p + -type contact layer 22 and omitting the p + -type contact layer 22 intermittently, the current path and the Has a structure provided with p @ + -type contact layers 22, 22a and a p-type drain layer 21 alternately along a direction perpendicular to the direction.

With the above structure, the hole injection efficiency can be further reduced and the hole discharge speed can be further increased as compared with the second embodiment. The increase in the hole discharge speed here is due to the decrease in the hole accumulation amount in the direction deviating from the current path, in addition to the decrease in the hole injection efficiency.

That is, the lateral IGBT according to the present embodiment
In this case, by omitting a part of the striped p + -type contact layer 22, the amount of accumulated holes in the region 24 of the n − -type active layer 3 below the drain electrode 14 is reduced, and the holes are easily discharged. Therefore, it is presumed that the hole discharge speed can be further increased.

As described above, according to the third embodiment,
In addition to the effects of the second embodiment, high-speed switching characteristics and high-output characteristics can be simultaneously realized with better values. (Fourth Embodiment) FIG. 9 is a plan view showing a configuration of a horizontal IGBT according to a fourth embodiment of the present invention, and FIG. 10 is a sectional view taken along line 10-10 of FIG. The same parts as in FIG. 7 are denoted by the same reference numerals, and substantially the same parts are denoted by the suffix b, detailed description of which is omitted, and different parts will be mainly described here. 9 is a sectional view taken along line 8-8 in FIG.
Is the same as the cross-sectional configuration shown in FIG.

That is, in the present embodiment, the pattern shapes of the p-type drain layer 21 and the p + -type contact layer 22 are optimized. Specifically, as shown in FIGS. Of the p + type contact layer 22 of FIG.
An island-shaped p + -type contact layer 22b is formed selectively in the type drain layer 21 along a direction orthogonal to the current path. Note that the p + -type contact layers 22 and 2
2b has the same impurity concentration.

Here, for example, the p + type contact layer 2
2b, as shown in the plan view of FIG. 11, a plurality of squares each having a square of 2 μm is 10 μm along a direction orthogonal to the current path.
Are arranged in a lattice pattern at intervals of 4 μm along the current path. In this case, the surface area ratio of the p + -type contact layer 22b to the p-type drain layer 22 is obtained as 10% as shown below.

[0045]

(Equation 1)

With the above-described structure, the hole injection efficiency can be further reduced and the hole discharge speed can be further increased as compared with the first to third embodiments.

That is, the lateral IGBT according to the present embodiment
Since the p + -type contact layer 22 has an island shape, the amount of accumulated holes in the region 24 below the drain electrode 14 in the n − -type active layer 3 is further reduced as described above. It is presumed that the holes can be discharged more easily, so that the hole discharge speed can be further increased. It is also presumed that the closer the island-shaped p + -type contact layer 22 is formed to the source side, the higher the hole discharge speed can be.

As described above, according to the present embodiment, the third
In addition to the effects of the embodiment, since the hole discharge speed can be further increased, high-speed switching characteristics and high-output characteristics can be simultaneously realized with better values.

The case where the ratio of the surface area of the p + -type contact layer 22b to the surface area of the p-type drain layer 22 is 10% has been described as an example.
It goes without saying that the deformation may be made to fall within the range of 78%.

FIGS. 1 to 10 show that a structure symmetrically arranged about the left side of the figure is effective in obtaining a high breakdown voltage. (Fifth Embodiment) FIG. 12 is a sectional view showing the structure of a semiconductor device according to a fifth embodiment of the present invention. The same parts as those in FIG. ,
Here, different parts will be mainly described.

That is, this embodiment shows a modification in which another element is formed together with the IGBT. For example, as shown in FIGS. 12 and 13, a free wheeling diode (FRD) is provided together with the IGBT. Is formed. In other words, this embodiment shows an example of application to an inverter device.

Specifically, an element isolation layer 30 using a trench is formed from the surface of the n − type active layer 3 to a depth reaching the buried oxide film 2. With this trench, n-
The active layer 3 is insulated and separated into an IGBT region and an FRD region. In the IGBT region, the I
Since the GBT is formed, the description is omitted.

The FRD region is a region where a freewheeling diode is formed. A p-type emitter layer 31 is selectively formed on the surface of the n − -type active layer 3 so as not to reach the buried oxide film 2. On the surface of the emitter layer 31, a p + type anode layer 32 is selectively formed.

Further, the n-type layer, which is different from the p-type
An n-type buffer layer 33 is selectively formed on the surface of the n-type active layer 3 so as not to reach the buried oxide film 2, and an n + -type cathode layer 34 and a p + -type contact are formed on the surface of the n-type buffer layer 33. The layer 35 is selectively formed.

A LOCOS oxide film 36 is formed in a surface region from a part of the p-type emitter layer 31 to the vicinity of the n-type buffer layer 33 in the n − -type active layer 3. LOCOS
On the oxide film 36, an A-side field plate 37 is formed near the p-type emitter layer 31, and the n-type buffer layer 3 is formed.
A K-side field plate 38 is formed near 3.

On the p + type anode layer 32, the anode electrode 39 is in contact with the A-side field plate 37.
Are formed. The n + type cathode layer 34 and p
A cathode electrode 40 is formed on the + -type contact layer 35 so as to be in contact with the K-side field plate 38.

The cathode electrode 40 is electrically connected to the drain electrode 14 as shown in FIG. Similarly, anode electrode 39 is electrically connected to source electrode 15.

With the above configuration, the inverter device having the effects of the fourth embodiment can be formed on one chip. In this embodiment, the IGBT and the FRD
And IGBTs can be formed on one chip, respectively. Therefore, the present invention is not limited to the IGBT of the fourth embodiment but may be applied to the IGBTs of the first to third embodiments. (Other Embodiments) In the above embodiments, the p-type drain layer 21 and the p + -type contact layer 22 having various patterns have been described. However, the present invention is not limited to this. The same effect can be obtained by implementing the present invention in the same manner regardless of the pattern shape as long as the configuration uses the + type contact layer 22.

Similarly, a low impurity concentration second conductivity type drain layer for lowering the hole injection efficiency and a high impurity concentration second conductivity type contact layer for preventing an increase in contact resistance are provided. As long as it is used, even if the specific impurity concentration, pattern shape, formation depth, and the like are variously modified, the present invention can be implemented in the same manner and the same effect can be obtained. In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.

[0060]

As described above, according to the present invention, it is possible to provide a semiconductor device having both high-speed switching characteristics and high output characteristics.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a horizontal IGBT according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the same embodiment taken along line 2-2 of FIG. 1;

FIG. 3 is a view showing an impurity concentration distribution in a depth direction on a p-type drain layer side of the embodiment.

FIG. 4 is a view showing a trade-off curve of the horizontal IGBT according to the embodiment;

FIG. 5 is a plan view showing a configuration of a horizontal IGBT according to a second embodiment of the present invention.

FIG. 6 is a sectional view of the same embodiment taken along line 6-6 of FIG. 5;

FIG. 7 is a plan view showing a configuration of a horizontal IGBT according to a third embodiment of the present invention.

FIG. 8 is a sectional view of the same embodiment taken along line 8-8 in FIG. 7;

FIG. 9 is a plan view showing a configuration of a horizontal IGBT according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view of the same embodiment taken along line 10-10 of FIG. 9;

FIG. 11 is a plan view showing the arrangement of the p + -type contact layer in the embodiment.

FIG. 12 is a sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention;

FIG. 13 is a circuit diagram showing a connection relation of the semiconductor device in the same embodiment;

FIG. 14 is a plan view showing a configuration of a conventional horizontal IGBT.

FIG. 15 is a cross-sectional view taken along line 15-15 of FIG.

FIG. 16 is a diagram showing a trade-off curve of a conventional horizontal IGBT.

FIG. 17 is a diagram showing a trade-off curve of a conventional horizontal IGBT.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate 2 buried oxide film 3 n-type active layer 4 n-type buffer layer 6 p-type base layer 7 n-type source layer 8 p-type contact layer 9 LOCOS oxide film 10 gate Oxide film 11 ... Gate electrode 12 ... S-side field plate 13 ... D-side field plate 14 ... Drain electrode 15 ... Source electrode 21 ... P-type drain layer 22, 22a, 22b ... P + -type contact layer 23 ... Contact region 24 ... Downside Area 30 Element isolation layer 31 P-type emitter layer 32 P-type anode layer 33 N-type buffer layer 34 N-type cathode layer 35 P-type contact layer 36 LOCOS oxide film 37 A-side field plate 38: K-side field plate 39: anode electrode 40: cathode electrode

Claims (5)

[Claims] A semiconductor substrate; an insulating layer formed on the semiconductor substrate; a high-resistance first conductive type active layer formed on the insulating layer; and a surface of the first conductive type active layer. A first conductivity type buffer layer formed; a second conductivity type drain layer formed on a surface of the first conductivity type buffer layer; and a second conductivity type drain layer formed on a surface of the second conductivity type drain layer.
A second conductivity type contact layer having a higher impurity concentration than the conductivity type drain layer; a drain electrode formed on the second conductivity type contact layer and on the second conductivity type drain layer; A second conductivity type base layer formed on the surface of the layer, a first conductivity type source layer formed on the surface of the second conductivity type base layer, and on the first conductivity type source layer and the second conductivity type A source electrode formed on a base layer; and a gate provided on the second conductivity type base layer interposed between the first conductivity type source layer and the first conductivity type active layer via a gate insulating film. A semiconductor device comprising: an electrode; 2. The semiconductor device according to claim 1, wherein the second conductivity type contact layer is formed in the second conductivity type drain layer in an island shape along a direction substantially perpendicular to a current path. A semiconductor device characterized by the above-mentioned. 3. The semiconductor device according to claim 1, wherein the second conductivity type contact layer is formed in the second conductivity type drain layer in a stripe shape having a longitudinal direction substantially parallel to a current path. Characteristic semiconductor device. 4. The semiconductor device according to claim 1, wherein a ratio obtained by dividing the surface area of the second conductivity type contact layer by the surface area of the second conductivity type drain layer is 10 to 7
A semiconductor device characterized by being within a range of 8%. 5. The semiconductor device according to claim 1, wherein an impurity concentration on a surface of said second conductivity type contact layer is 1%.
× 10 ¹⁹ cm ⁻³ or more, and the impurity concentration on the surface of the second conductivity type drain layer is 1 ×
A semiconductor device characterized by being in the range of 10 ^{18 to} 3 × 10 ¹⁸ cm ⁻³ .