JP4852188B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of performing switching control of a high voltage and a large current.
[0002]
[Prior art]
An inverter device is used to generate a desired current and voltage for driving a motor such as an electric vehicle from a given power source. This inverter includes a configuration in which a switching element and a reflux diode connected in reverse parallel thereto are paired.
[0003]
For power switching elements such as insulated gate bipolar transistors (IGBTs) and MOS field effect transistors (MOSFETs) used in such inverters, it is very important to reduce power loss. Therefore, a low on-voltage (that is, low on-resistance) is required. For this reason, it has been attempted to reduce the on-voltage by adopting a vertical gate structure capable of increasing the cell density as compared with the conventional horizontal gate structure.
[0004]
In addition, the switching element is required to have a high-speed switching operation in order to realize a high-speed operation of the inverter and to have a small switching loss accompanying the switching operation. In addition, the current that can flow per unit area of the switching element, that is, the controllable current density is improved, and the switching element cost can be reduced as the switching element is downsized and the number of chips obtained from one wafer is increased. Efforts have been made to
[0005]
An IGBT is suitable as a switching element that meets such requirements. This is because the IGBT is a semiconductor element in which a power MOSFET and a bipolar transistor are combined on a single chip, and has both high-speed switching performance by a MOS gate and high breakdown voltage and high conduction characteristics by bipolar transistor operation. In particular, a trench IGBT that forms a vertical gate structure with a trench structure has been attracting attention as an element that can satisfactorily satisfy both the on-voltage and the high-speed switching performance.
[0006]
FIG. 7 is a schematic cross-sectional view of a trench IGBT for explaining the principle of the trench IGBT. A p base layer 4, an n ⁻ epitaxial layer 6, an n ⁺ buffer layer 8, and a p ⁺ collector layer 10 are formed on the semiconductor portion 2 of the element mainly from the front surface to the back surface. Further, an n ⁺ emitter region 12 is formed on the surface side of the p base layer 4. The n ⁺ emitter region 12 is formed so as to leave a portion where the p base layer 4 is exposed on the surface. The trench 14 is formed from the surface of the semiconductor portion 2 to a depth reaching the n ⁻ epitaxial layer 6 by scraping the n ⁺ emitter region 12 and the p base layer 4. A gate electrode 18 is buried in the trench 14 via a gate oxide film 16. An emitter electrode 20 is provided on the surface of the semiconductor portion 2 so as to be in contact with the p base layer 4 and the n ⁺ emitter region 12. An interlayer insulating film 22 is disposed on the trench 14, and an emitter electrode 20 is formed thereon, thereby ensuring insulation between the gate electrode 18 and the emitter electrode 20. A collector electrode 23 is connected to the p ⁺ collector layer 10.
[0007]
In this configuration, the n ⁺ emitter region 12, the p base layer 4, the n ⁻ epitaxial layer 6 and the gate electrode 18 constitute a MOSFET. With the collector potential higher than the emitter potential, the gate potential is set to a positive potential with respect to the emitter potential. When the gate voltage exceeds the threshold voltage, a channel is formed in a region in contact with the gate electrode 18 of the p base layer 4, and a large number of electrons flow from the n ⁺ emitter region 12 to the n ⁻ epitaxial layer 6 to be turned on.
[0008]
The p base layer 4, the n ⁻ epitaxial layer 6, the n ⁺ buffer layer 8, and the p ⁺ collector layer 10 constitute a pnp bipolar transistor. When turned on, holes flow from the p ⁺ collector layer 10 to the n ⁻ epitaxial layer 6 in the pnp bipolar transistor portion. Thus n ^- number of holes and electrons are accumulated in the epitaxial layer 6, n ^- resistance of the epitaxial layer 6 is greatly reduced. The on-voltage of the element is greatly reduced by this conductivity modulation effect.
[0009]
In the IGBT, in the ON state, most of the holes flowing into the n ⁻ epitaxial layer 6 are recombined with electrons there, but the surplus flows to the emitter electrode 20. At the time of switching operation, it is necessary to remove holes accumulated in the n ⁻ epitaxial layer 6 by passing them as a hole current through the p base layer 4 to the emitter electrode 20. Here, the IGBT element structure is accompanied by a parasitic thyristor including a p ⁺ collector layer 10, an n ⁻ epitaxial layer 6, a p base layer 4, and an n ⁺ emitter region 12. Therefore, when the hole current flowing through the p base layer 4 in the ON state and the switching operation increases, the parasitic thyristor becomes conductive, and a latch-up phenomenon occurs in which the operation of the element cannot be controlled by the gate electrode 18. The parasitic thyristor latches up, and the element can be destroyed.
[0010]
In the prior art that suppresses the operation of the parasitic thyristor for the purpose of improving the breakdown tolerance, attention has been focused on the structure of the cell, which is the basic structural unit of the element. For example, the prior art disclosed in Japanese Patent Laid-Open No. 1-198076 devises the surface structure of the cell region of the element.
[0011]
[Problems to be solved by the invention]
However, there has been a problem that even if such an improvement of the cell structure is performed, only a breakdown resistance lower than expected from the structure of the cell can be obtained.
[0012]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a highly reliable semiconductor device in which element destruction due to a latch-up phenomenon is suppressed.
[0013]
[Means for Solving the Problems]
As a result of our investigation, the above problem that the breakdown structure does not increase as much as the improvement of the cell structure is expected is that the hole current is concentrated in the peripheral cells among the cells arranged on the chip. It turned out that it was caused by.
[0014]
The concentration of the hole current around the cell will be described next. FIG. 8 is a schematic top view of a cell peripheral portion of a conventional trench IGBT. An n ⁺ emitter region 12 is provided along a plurality of trenches 14 provided in the p base layer 4. The n ⁺ emitter region 12 is provided in the right portion in FIG. 8, and this portion constitutes a cell area (active region), and the left portion constitutes a non-cell area (inactive region). Incidentally, the non-cell area is used for maintaining the element breakdown voltage and for performing gate wiring. FIG. 9 is a schematic diagram of a device cross section along the line AA ′ shown in FIG. An arrow 30 schematically shows a hole current from the n ⁻ epitaxial layer 6 to the p base layer 4. The hole current in the inner area of the cell area is generated mainly by the holes accumulated in the n ⁻ epitaxial layer 6 portion immediately below each cell in the portion, but the hole current in the peripheral portion of the cell area is It includes not only holes directly under the cell but also a component due to a large amount of holes accumulated in the n ⁻ epitaxial layer 6 portion of the non-cell area adjacent to the cell. That is, the hole current from the non-cell area is concentrated in the peripheral cells. For this reason, it was found that the hole current in the peripheral cells was several times that of the central cell in the cell area.
[0015]
Although the conventional technology can improve the breakdown tolerance at the center of the cell area, it cannot effectively prevent the hole current concentration in the peripheral cells, so the breakdown tolerance of the entire device is The value stayed lower than expected.
[0016]
The present invention solves the problem of avoiding destruction of a semiconductor device by suppressing current concentration in peripheral cells caused by the mechanism as described above, and achieves the above object.
[0017]
The semiconductor device according to the present invention includes a first conductivity type base layer formed on a surface of a semiconductor substrate, a second conductivity type emitter region selectively formed on the surface of the first conductivity type base layer, and the first A second conductivity type base layer bonded to the conductivity type base layer; a first conductivity type collector layer bonded to the second conductivity type base layer and connected to a collector electrode; the first conductivity type base layer; An emitter electrode connected to the conductive type emitter region, and a current flowing between the second conductive type emitter region and the second conductive type base layer facing the first conductive type base layer via an insulating film In a semiconductor device having a gate electrode to be controlled and performing current control between the emitter electrode and the collector electrode, a cell area in which the second conductivity type emitter region of the first conductivity type base layer is disposed Part and said 1 first trench between the non-cell area portion which is not disposed in the second conductive type emitter region of the conductivity type base layer is formed, the cell area portion and said non-cell area portion is electrically separated, provided along the longitudinal center line of the second conductive type emitter region, is shall comprise a second trench having an end portion which is formed so as to protrude to the non-cell area portion from said first trench .
[0018]
According to the present invention, even if a charge flows from the second conductivity type base layer into the first conductivity type base layer in the non-cell area portion, a current due to the charge flows to the first conductivity type base layer in the cell area portion. Is inhibited by the trench. Therefore, current is less likely to concentrate from the non-cell area to the periphery of the cell area, and the latch-up phenomenon of the parasitic thyristor at that portion is suppressed.
[0019]
A preferred aspect of the present invention is a semiconductor device in which an electrode material is embedded in the first trench through an insulating film, and the electrode material is used as a wiring to the gate electrode.
[0020]
In another semiconductor device according to the present invention, a contact for connecting the first conductivity type base layer in the non-cell area portion to the emitter electrode is disposed along the first trench.
[0021]
According to the present invention, the first conductivity type base layer in the non-cell area portion is provided with a contact at the end on the cell area side, and is connected to the emitter electrode here. As a result, the charge that flows into the cell area from the bottom of the non-cell area is sucked out from the contact located before reaching the cell area, and the current from the non-cell area to the cell area is effectively suppressed. Is done.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0023]
FIG. 1 is a schematic top view of an insulating semiconductor device according to the present invention. This device is divided into a device breakdown voltage maintaining region 42 on the outer side and a region including an inner cell area by a gate wiring 40 arranged around the chip. A region inside the gate wiring 40 is divided by a gate wiring 44 arranged therebetween, and here, three cell areas 46 are formed. The gate lines 40 and 44 are connected to the gate pad 48. In FIG. 1, a structure such as a contact hole for making contact with each electrode is omitted for the sake of simplicity.
[0024]
FIG. 2 is an enlarged top view of a region 52 in FIG. 1 in order to explain the structure of the apparatus in detail. The basic structure of the trench IGBT formed in the cell area 46 is the same as the known structure described in the prior art, and the description of the structure and operation is omitted. In the following description and drawings, FIG. Similar components are denoted by the same reference numerals.
[0025]
On a silicon p ⁺ substrate (impurity concentration: 1 × 10 ¹⁸ cm ⁻³ or more) constituting the p ⁺ collector layer 10, an n ⁺ buffer layer 8 (thickness: 10 to 20 μm) and an n ⁻ epitaxial layer 6 ( (Thickness: 50 to 100 μm) is formed by an epitaxial growth method. The n ⁺ buffer layer 8 is a low resistance layer having an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ . On the other hand, the impurity concentration of the n ⁻ epitaxial layer 6 is about 1 × 10 ¹⁴ cm ⁻³ .
[0026]
The p base layer 4 (thickness: 2 to 5 μm, impurity peak concentration: about 1 × 10 ¹⁷ cm ⁻³ ) is formed on the surface of the n ⁻ epitaxial layer 6 by thermal diffusion of impurities. A photoresist film is formed on the surface of the p base layer 4, and this photoresist film is patterned to form a mask for forming an n ⁺ region. The n ⁺ region (diffusion depth: about 0.5 to 1 μm, impurity peak concentration: about 1 × 10 ²⁰ cm ⁻³ ) is formed by implanting impurities from above the mask.
[0027]
The pattern of the n ⁺ region includes an elongated stripe-shaped n ⁺ emitter region 12 having a width of several μm and a length of about 1 mm. In order to enable large current control, a number of IGBTs are arranged in parallel in the cell area 46. Correspondingly, a plurality of n ⁺ emitter regions 12 are also arranged in parallel. The n ⁺ region includes a contact region 60 that bridges between the n ⁺ emitter regions 12 adjacent to each other. This contact region 60 is provided exclusively to ensure electrical contact between n ⁺ emitter region 12 and emitter electrode 20 (emitter electrode 50 in FIG. 1).
[0028]
A trench 14 is formed along the longitudinal center line of the n ⁺ emitter region 12. The trench 14 has a depth of about 1 to 3 μm deeper than the p base layer 4, has a width of 1 μm, and a length of about 1 mm, similar to the n ⁺ emitter region 12. By forming along a trench 14 at the center line of the n ⁺ emitter region 12, each of n ⁺ emitter region 12 is divided into two regions adjacent to the trenches 14. A gate electrode 18 is embedded inside the trench 14 via a gate oxide film 16. The film thickness of the gate oxide film 16 is 80 to 100 nm. The gate electrode 18 is configured to have an interval of about 4 μm, for example.
[0029]
The trench 68 that electrically separates the cell area and the non-cell area is formed by forming the gate oxide film 64 in the trench 62 and then burying the wiring electrode 66. The trench 68 can be basically formed by a process common to the gate electrode 18. The trench 62 is provided outside the cell area 46, that is, in the p base layer 4 portion in a region where the n ⁺ emitter region 12 is not formed.
[0030]
One feature of the structure of the semiconductor device is that the p base layer 4 is separated into a cell area 46 and another region (ie, a non-cell area) by a trench 62 deeper than the p base layer 4. It is in. Here, the other regions refer to the element breakdown voltage maintaining region 42, the gate pad 48, the gate wirings 40, 44, and the like.
[0031]
Thereafter, a striped interlayer insulating film 22 is provided on the trenches 14 and 62 so as to cover the trenches 14 and 62. The interlayer insulating film 22 is for ensuring insulation between the emitter electrode 20 provided on the film and the gate electrodes 18 and 66 formed below the film.
[0032]
Next to the interlayer insulating film 22, an emitter electrode 20 is formed. FIG. 3 is a schematic view of the element cross section along the straight line BB ′ shown in FIG. By providing the interlayer insulating film 22 as described above, the emitter electrode 20 can be laminated not only in the portion where the semiconductor layer is exposed, such as the p base layer 4, but also in the region where the gate electrodes 18 and 66 are disposed. it can. That is, the emitter electrode 20 is basically formed on the entire surface of the cell area 46, thereby eliminating the need for fine patterning on the emitter electrode 20. In this semiconductor device, the emitter electrode 20 extends beyond the trench 62 to the non-cell area. The emitter electrode 20 is in electrical contact with the p base layer 4 and the n ⁺ emitter region 12 exposed in the gap between the interlayer insulating films 22 in the cell area, and keeps them at a common potential. Further, in the non-cell area, a contact 72 that electrically contacts the emitter electrode 20 and the p base layer 4 is provided along the vicinity of the trench 62. Note that the n ⁺ emitter region 12 in the cell area is at least partially covered by the interlayer insulating film 22, and the area of the n ⁺ emitter region 12 exposed in the gap between the interlayer insulating films 22 is reduced. The contact region 60 described above is provided to compensate for this.
[0033]
Next, the operation of this semiconductor device will be described. With the collector potential higher than the emitter potential, the gate potential is set to a positive potential with respect to the emitter potential. When the gate voltage exceeds the threshold voltage and becomes a sufficient value, a channel is formed in a region in contact with the gate electrode 18 of the p base layer 4, and a large number of electrons flow from the n ⁺ emitter region 12 to the n ⁻ epitaxial layer 6 and turn on. It becomes. When turned on, holes are transferred from the p ⁺ collector layer 10 to the n ⁻ epitaxial layer 6 in the pnp bipolar transistor portion composed of the p base layer 4, the n ⁻ epitaxial layer 6, the n ⁺ buffer layer 8, and the p ⁺ collector layer 10. Flows in. Thus n ^- number of holes and electrons are accumulated in the epitaxial layer 6, n ^- resistance of the epitaxial layer 6 is greatly reduced. Due to this conductivity modulation effect, the on-voltage is greatly reduced as in the conventional semiconductor device. On the other hand, when the gate voltage becomes lower than the threshold voltage, the inflow of electrons from the n ⁺ emitter region 12 to the n ⁻ epitaxial layer 6 is stopped, and the transistor is turned off.
[0034]
In the ON state and switching, as described in the prior art, it is necessary to remove holes accumulated in the n ⁻ epitaxial layer 6 by passing them as a hole current through the p base layer 4 to the emitter electrode 20. is there. In the present semiconductor device, as described above, the p base layer 4 is separated into the cell area 46 and the non-cell area by the trench 62. As a result, holes accumulated in the n ⁻ epitaxial layer 6 immediately below the non-cell area are prevented from flowing into the cell area through the p base layer 4, and the hole current from the non-cell area to the peripheral cells is blocked. Concentration is suppressed. FIG. 3 schematically shows the state of the hole current around the cell area. In the figure, an arrow 70 indicates a hole current from the n ⁻ epitaxial layer 6 immediately below the non-cell area in the semiconductor device to the p base layer 4. By preventing the hole current 70 from flowing into the n ⁺ emitter region 12 of the peripheral cell in this way, the parasitic thyristor latch-up in the peripheral cell is less likely to occur.
[0035]
In the present semiconductor device, the emitter electrode 20 is in electrical contact with the p base layer 4 in the non-cell area in the vicinity of the trench 62 via the contact 72 as described above. As a result, holes accumulated in the n ⁻ epitaxial layer 6 immediately below the non-cell area are sucked out from the contact 72 to the emitter electrode 20 before reaching the cell area. Therefore, the inflow of holes from the non-cell area to the peripheral portion of the cell area is further effectively suppressed, and the latch-up of the parasitic thyristor is favorably avoided. In order to effectively suck and discharge holes from the contact 72, it is preferable to arrange the contact 72 along the non-cell area side of the trench 62 continuously or at a predetermined interval or less.
[0036]
The present semiconductor device having the above-described characteristics no longer causes element breakdown even when a current more than twice as large as that of a conventional semiconductor device having no such characteristics is passed.
[0037]
In the above-described embodiment, the trench 62 is formed in a straight line when viewed from above. However, the essential function of the trench 62 is to divide the p base layer 4 between the non-cell area and the cell area 46 and to prevent the hole current from flowing into the peripheral cells from the non-cell area. The pattern is not necessarily limited to a straight line. FIG. 4 is a schematic top view of the periphery of a cell of a semiconductor device showing an example thereof. In this example, the p base layer 4 of the non-cell area and the cell area is divided by the trench electrode 80 formed in a different pattern. Also with this configuration, the same effect as in the above embodiment was obtained.
[0038]
Further, the number of trenches is not limited to one. FIG. 5 is a schematic top view of the periphery of a cell of a semiconductor device showing an example thereof. In this example, the non-cell area and the cell area are divided by two trench electrodes 90 and 92. Also with this configuration, a good breakdown resistance was realized as in the above embodiment.
[0039]
Furthermore, in order to divide the p base layer 4 between the non-cell area and the cell area and inhibit the inflow of hole current, it is not always necessary to embed an electrode material in the trench. FIG. 6 is a schematic cross-sectional view of the periphery of a cell of a semiconductor device showing an example thereof. In this example, the trench 100 has a structure simply filled with an insulator.
[0040]
Up to this point, an example in which the present invention is applied to a trench IGBT has been described. However, the present invention can also be applied to a planar IGBT, and the cell area and the non-cell area are separated to improve the breakdown resistance. Can be planned.
[0041]
Further, the same effect can be obtained when applied not only to the n-type channel device as described above but also to a p-type channel device.
[0042]
【The invention's effect】
According to the semiconductor device of the present invention, the hole provided between the non-cell area and the cell area prevents the hole current from flowing from the non-cell area to the cell area. It is avoided that the hole current is concentrated and the latch-up phenomenon occurs. That is, an insulated gate semiconductor device having a high breakdown resistance can be obtained, and element destruction due to a surge voltage or the like generated at the time of switching of an inductance load or the like can be prevented, and an effect of enabling use with a larger current can be obtained.
[Brief description of the drawings]
FIG. 1 is a schematic top view of an insulating semiconductor device according to an embodiment of the present invention.
FIG. 2 is a schematic top view of the periphery of a cell area of the apparatus.
FIG. 3 is a schematic cross-sectional view around the cell area of the apparatus.
FIG. 4 is a schematic top view of the periphery of a cell area according to another embodiment of the present invention.
FIG. 5 is a schematic top view of the periphery of a cell area according to another embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view of the periphery of a cell area according to another embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view of a trench IGBT for explaining the principle of the trench IGBT.
FIG. 8 is a schematic top view of a cell peripheral portion of a conventional trench IGBT.
FIG. 9 is a schematic cross-sectional view of a cell periphery of a conventional trench IGBT.
[Explanation of symbols]
4 p base layer, 6 n ⁻ epitaxial layer, 8 n ⁺ buffer layer, 10 p ⁺ collector layer, 12 n ⁺ emitter region, 14, 62, 100 trench, 16, 64 gate oxide film, 18 gate electrode, 20, 50 Emitter electrode, 22 interlayer insulation film, 40, 44 gate wiring, 42 element breakdown voltage maintenance region, 46 cell area, 66 wiring electrode, 72 contact, 80, 90, 92 trench electrode.

Claims (3)

A first conductive type base layer formed on the surface of the semiconductor substrate; a second conductive type emitter region selectively formed on the surface of the first conductive type base layer; and a first type bonded to the first conductive type base layer. A second conductivity type base layer, a first conductivity type collector layer joined to the second conductivity type base layer and connected to a collector electrode, and connected to the first conductivity type base layer and the second conductivity type emitter region; An emitter electrode, and a gate electrode that controls the current flowing between the second conductivity type emitter region and the second conductivity type base layer opposite to the first conductivity type base layer via an insulating film In a semiconductor device that performs current control between the emitter electrode and the collector electrode,
A cell area portion in which the second conductivity type emitter region is disposed in the first conductivity type base layer and a non-cell area portion in which the second conductivity type emitter region is not disposed in the first conductivity type base layer. A first trench is formed between the cell area portion and the non-cell area portion ,
Wherein provided along the longitudinal center line of the second conductive type emitter region, characterized Rukoto comprises a second trench having an end portion which is formed so as to protrude to the non-cell area portion from said first trench A semiconductor device. The semiconductor device according to claim 1,
An electrode material is embedded in the first trench through an insulating film, and the electrode material is used as a wiring to the gate electrode. The semiconductor device according to claim 1,
A contact for connecting the first conductivity type base layer of the non-cell area portion to the emitter electrode is disposed along the first trench.

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