JP2011082585A - Insulated gate semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an element structure of an insulated gate semiconductor device by which the device is prevented from being broken due to remaining carriers when being switched on while making possible the reduction of on-voltage, and also capable of improving a breaking capacity by accelerating the discharge of remaining carriers around a chip area, especially when turned off. <P>SOLUTION: The insulated gate semiconductor device has an isolation structure formed around the periphery of a semiconductor substrate in order to demarcate the element region inside; a peripheral diffusion region formed at the outer side of the isolation structure of the semiconductor substrate; base regions which are formed inside the element region, divided by insulated trench gates, and have emitter regions on the surfaces; collector regions; a plurality of cell structures having emitter electrodes connected to the emitter regions and the base regions; dummy base regions being base regions which are adjacent to the cell structures without having on their surfaces the emitter regions connected to the emitter electrode; and a connection section for electrically connecting the peripheral diffusion regions to the emitter electrodes. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to an insulated gate semiconductor device, and more particularly to an insulated gate bipolar transistor (IGBT) having a trench gate and an element structure thereof.

  Conventionally, IGBTs have been widely used as insulated gate transistors, but as an improved version of them, an injection enhanced gate transistor (IEGT) that can store electrons under the gate has been developed. Since power can be realized, it has been widely used recently.

  In the conventional insulated gate semiconductor device, the ring-shaped diffusion region in the outer peripheral portion and the diffusion layer region under the gate wiring portion are formed in connection with the base diffusion layer in the cell region.

  However, a semiconductor device such as IEGT having a particularly high breakdown voltage uses a trench gate as a gate electrode and an emitter electrode in a base region between the trench gates in order to increase accumulated carriers in the cell region and reduce negative capacitance. In other words, a dummy base region in a so-called floating state that is not in contact with is provided.

  This negative capacitance is problematic in that if the potential of the p-type dummy base layer in the dummy cell region is not completely floating, an overshoot of the gate-emitter voltage Vge is caused. More specifically, even if the potential of the p-type dummy base layer is designed to be floating, the potential at the OFF time via a parasitic resistance due to a parasitic structure (for example, partial connection with a cell end or a junction termination). Is fixed in the vicinity of zero potential, the gate-emitter voltage Vge reaches the threshold voltage Vth at the time of turn-on, and then the potential of the p-type dummy base layer rapidly rises with the injection of holes. There is a phenomenon that Vge overshoots.

  In addition, by providing a dummy base region that is not connected to the emitter layer, it is possible to promote the injection of carriers and reduce the on-voltage. However, when the semiconductor device is switched, carriers remain in the dummy base region and the breakdown tolerance is reduced. There is a problem of causing a decrease.

Furthermore, when the current is interrupted, it is necessary to discharge the carriers present in the element. For this reason, the carriers in the cell region are emitted from the emitter electrode, and the carriers present in the periphery of the element are derived from the ring-shaped diffusion region in the outer peripheral portion. It is discharged through the base diffusion layer in the cell region. However, if the ring-shaped diffusion region in the outer peripheral portion or the diffusion layer region under the gate wiring portion and the base diffusion layer in the cell region are completely separated, there is no path for discharging carriers in the outer peripheral region when the current is interrupted. There is a risk of lowering.
JP-A-2001-168333

  An object of the present invention is to provide an element structure capable of preventing breakdown due to residual carriers at the time of switching in an insulated gate semiconductor device while enabling a reduction in on-voltage.

  It is another object of the present invention to provide an element structure capable of enhancing the shutoff resistance by promoting the discharge of residual carriers in the peripheral region of the chip particularly in an insulated gate semiconductor device during turn-off.

One aspect of the present invention is an isolation structure that is formed in a circular shape around a semiconductor substrate and defines an internal element region;
A peripheral diffusion region formed outside the isolation structure in the semiconductor substrate;
A plurality of base regions formed in the element region and divided by insulated trench gates, having a base region having an emitter region on the surface, a collector region, and an emitter electrode connected to the emitter region and the base region Cell structure of
A dummy base region that is adjacent to the cell structure and has no emitter region connected to the emitter electrode on a surface portion;
A connection portion for electrically connecting the peripheral diffusion region to the emitter electrode,
The base region and the dummy base region are provided alternately with the trench gate interposed therebetween, providing an insulated gate semiconductor device.

It is a top view which shows the insulated gate semiconductor device to which this invention is applied. FIG. 2 is an enlarged cross-sectional view taken along line A-A ′ in FIG. 1. It is a typical top view which shows the 1st Example of the 1st Embodiment of this invention. It is a fragmentary sectional view of the element which shows the example of wiring structure. It is a perspective view which shows the structure of FIG. It is element sectional drawing which shows the other example of a wiring structure. It is a top view which shows the 2nd Example of the 1st Embodiment of this invention. It is a top view which shows the 3rd Example of the 1st Embodiment of this invention. It is a top view which shows the 4th Example of the 1st Embodiment of this invention. It is a top view of the IGBT structure common to the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of IGBT concerning the 1st Example in the 2nd Embodiment of this invention. FIG. 12 is a partially cutaway perspective view illustrating a state in a depth direction along the line C-C ′ in FIG. 11. It is a figure which shows simply the relationship between the diffusion layer for carrier discharge | emission, and wiring. It is a figure which shows a simple structure similarly. It is element sectional drawing which shows a 2nd Example. It is sectional drawing which shows the D-D 'cross section in FIG. It is sectional drawing which shows the structure of the 3rd Example of the 2nd Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a plan view showing an insulated gate semiconductor device to which the present invention is applied, and FIG. 2 is an enlarged sectional view taken along the line A-A '.

  As shown in these drawings, the outer peripheral ring portion and the element portion are separated by the isolation trench 8 circulating around the periphery of the N-type substrate 10, and the outermost portion of the P-type diffusion region is outside the isolation trench 8. A dummy base region 7 which is a P-type diffusion region having a floating structure is provided on the inner peripheral end portion 9 and on the inner side.

  In the cross-sectional view of FIG. 2, the configuration of the element portion is also shown. On the inner peripheral side of the dummy base 7, a P-type base region 6 defined by a trench gate electrode 3 covered with an insulating film 4 and a dummy are provided. Base regions 7 are alternately formed. An N-type emitter region 5 is formed adjacent to the gate electrode 3 at the upper end of the base region. The dummy base region means a dummy base region that is a base region having no emitter region connected to the emitter electrode on the surface portion. An interlayer insulating film 2 is formed on the dummy base region 7 and the gate electrode 3, and an emitter electrode 1 is formed on the whole.

First embodiment

  A first embodiment of an insulated gate semiconductor device according to the present invention will be described below. This form is suitable for discharging the carrier in the outer peripheral diffusion region.

  FIG. 3 is a schematic plan view showing a first example of the first embodiment of the present invention, and is a plan view of a semiconductor element as viewed from above. This semiconductor element is, for example, a high-power IGBT having a size of about 15 mm on a side.

  According to the figure, a ring-shaped electrode 11 is formed on the outer periphery, and an emitter electrode 12 and a gate electrode 13 are formed therein. In the example of FIG. 3, the emitter electrodes are formed in four columns, and the lower side of the second column from the right is the gate electrode. In addition, the thick line in the figure indicates the metal wiring 14 provided on the gate wiring in order to reduce the resistance. In this embodiment, the outer peripheral ring-shaped electrode 11 is connected to the upper side of each emitter electrode 12 in the figure, and a metal wiring 15 formed integrally in the same process is provided.

  4 to 6 show a state in which the emitter electrode and the outer ring electrode are connected.

  4 is a cross-sectional view showing a wiring structure in which the gate electrode is divided at the wiring portion 15, and FIG. 5 is a perspective view of the wiring structure. As shown in FIG. 4, the innermost peripheral end portion 9 of the ring-shaped diffusion region is located outside the isolation trench 8, and the gate electrode 19 is interposed above the part via the insulating film 2. Is formed. As shown in FIG. 5, the gate electrode 19 is divided at the wiring portion, and a metal wiring 15 is provided in this portion, and the outer periphery located outside the emitter electrode 1 and the isolation trench inside the isolation trench. The ring electrodes 11 are connected.

  The ring-shaped diffusion region 9 and the outer peripheral ring-shaped electrode 11 located outside the isolation trench 8 are connected through a through hole 18 provided in the insulating film 2.

  In such a configuration, carriers existing in the peripheral portion of the element can be discharged through the outer peripheral ring electrode 11, the metal wiring 15 and the emitter wiring, and the cutoff resistance can be improved.

  FIG. 6 is a cross-sectional view showing another example of the connection structure between the emitter electrode and the outer ring electrode. In this example, as apparent from comparison with FIG. 4, since the gate electrode 19 is covered with the insulating film 17, the gate electrode 19 does not need to be divided and is entirely covered with the emitter electrode 1. It is in a state.

  In this example, the etching process or the like is small.

  FIG. 7 shows a second example of the first embodiment of the present invention in which five emitter electrodes 12 are provided and each column is divided into upper and lower parts. In the rightmost column, the gate electrode 13 is provided between the upper and lower emitter electrodes.

  Also in this embodiment, the metal wiring 15 is provided between all the emitter electrodes 12 and the ring electrode 11 on the outer peripheral portion, and the carriers in the outer peripheral region are discharged when the current is cut off as in the first embodiment. However, since the number of conductive points is larger than that in the first embodiment, it is particularly suitable for a large-area semiconductor device that handles a large current.

  FIG. 8 is a plan view showing a third example of the first embodiment of the present invention, which is similar to FIG. 4 in that the emitter regions 12 formed in four rows are vertically divided. A gate electrode 13 is provided at a corner portion at the lower end of the right column, and a part 11a of the outer peripheral ring electrode 11 extends between the upper emitter electrode. A metal wiring 15a for connection is also provided between the extended portion 11a and the emitter electrode 12a.

  In this embodiment, the gate electrode 13 is positioned at the corner, and the arrangement of the gate electrode is optimal for an element designed as such.

  FIG. 9 is a plan view showing a fourth example of the first embodiment of the present invention, in which the emitter electrodes 12 are formed in seven rows, of which the lower side of the central fourth row is the gate electrode 13. . The emitter electrode 12 and the outer peripheral ring electrode 11 disposed around the emitter electrode 12 are on the side surface in the leftmost and rightmost emitter electrodes, on the upper side in the even-numbered emitter electrodes, and in the odd-numbered columns excluding the leftmost and rightmost ends. Metal wiring for connection is provided on the lower side.

  In this embodiment, the metal wiring for connection is provided alternately on the upper side and the lower side, so that the wiring region can be manufactured with a margin.

Second embodiment

  The first embodiment described above is suitable for discharging carriers in the outer peripheral diffusion region, but the second embodiment described below is suitable for discharging carriers from the region inside the element. Is.

  FIG. 10 is a plan view of an IGBT structure common to the second embodiment of the present invention described below, and has a circular trench-shaped isolation region 52 that separates the outer peripheral portion 51 and the inner peripheral portion of the substrate 50. The trench-like isolation region is provided not only in the outer periphery of the emitter cell but also in the emitter cell so as to separate the emitter regions 53 formed in a plurality of rows. A trench-shaped isolation region 54 is provided. As described with reference to FIG. 1, the innermost peripheral end portion 55 is provided immediately outside the separation region, and the dummy base region 56 is formed inside. The dummy base region 56 is also formed along each isolation region between the emitter regions. The outer periphery of the emitter cell has the same potential as that of the emitter electrode at the innermost end for maintaining the withstand voltage.

  FIG. 11 is a cross-sectional view taken along line B-B ′ in FIG. 11 showing the structure of the IGBT according to the first example of the second embodiment of the present invention.

  A large number of trenches are formed, but there are isolation trenches 52 and 54 and a trench gate electrode 59. An interlayer insulating film 58 is formed on the substrate surface above these trenches. When there is no interlayer insulating film above the region between the trenches and the emitter electrode 61 is formed, the trench is a trench gate electrode 59, and the region between the trench gates is a base region 57, On the surface, an emitter region 60 is formed as an N-type impurity diffusion region.

A region between the trench gates, on which an interlayer insulating film is formed, is a P-type dummy base region 56. A region below the interlayer insulating film 58 and between the trench gate electrode 59 and the isolation trench 54 is also a dummy base region 56. Further, a region between the isolation trenches 54 is, for example, a P-type carrier discharge diffusion layer 62.
FIG. 12 is a partially cutaway perspective view showing a state in the depth direction along the line CC ′ in FIG. 11. In this figure, most of the interlayer insulating film 58 and the emitter electrode formed on the four right trenches are omitted. This is because contact holes and wirings (both not shown) formed in the interlayer insulating film 58 in the contact region 63 indicated by broken lines in FIG. 12 are formed in the interlayer insulating film on the carrier discharging diffusion layer 62. And is connected to the emitter electrode through the same potential. This state is schematically shown in FIG.

  According to such a configuration, at the time of switching, residual carriers are discharged to the emitter through the P-type diffusion layer 62 inside the emitter cell, so there is no accumulation of carriers and the breakdown resistance is improved.

  In FIG. 13, the carrier discharge diffusion layer 62 is connected to the wiring 64 connected to the emitter electrode 61. However, as shown in FIG. 14, which similarly shows a simple structure, the gate electrode 65 separated from the emitter electrode 61. You may make it connect with. This is because it is not possible to form an active layer directly under the gate electrode, and the gate electrode generally has a wide width of about 100 μm, so it is suitable to provide a carrier discharge diffusion layer 62 for collecting carriers. Because.

  FIG. 15 is a device cross-sectional view showing a second embodiment for discharging carriers from the region inside the device, and shows the B-B ′ cross section of FIG. 11 as in the case of FIG. 11. FIG. 16 shows a D-D ′ cross section in FIG. 15. In these drawings, the same components as those in FIGS. 11 and 12 are denoted by the same reference numerals.

  In this embodiment, the isolation regions 52 and 54 provided in the embodiment shown in FIGS. 11 and 12 are not provided, but are separated by a diffusion layer 66, for example, an n-type impurity diffusion layer. .

  Since this embodiment is different only in the structure of the isolation region, the operation and effect are exactly the same as in the case of Embodiment 1, and during switching, residual carriers are discharged to the emitter through the p-type diffusion layer inside the emitter cell. There is no accumulation of carriers, and the breakdown resistance is improved.

  FIG. 17 is a cross-sectional view taken along the line B-B ′ in FIG. 11, showing the configuration of the third example of the second embodiment of the present invention.

  In the first and second embodiments described above, residual carriers are discharged to the emitter via the p-type diffusion layer and wiring. In this embodiment, an emitter electrode 67 that directly contacts the carrier discharge P-type diffusion layer 62. Is provided.

  Even in this embodiment, residual carriers can be efficiently discharged. However, unlike the first and second embodiments, the residual carriers are directly supplied from the carrier discharge p-type diffusion layer to the emitter electrode without using a wiring. Can be discharged, the discharge capacity is higher than those in Examples 1 and 2.

  The first embodiment and the second embodiment described above may be applied alone, but both may be applied together.

11 Outer ring electrodes 1, 12 Emitter electrode 15 Metal wiring 18 Through hole

Claims (3)

An isolation structure that is formed in a circular shape around the semiconductor substrate and demarcates the internal element region;
A peripheral diffusion region formed outside the isolation structure in the semiconductor substrate;
A plurality of base regions formed in the element region and divided by insulated trench gates, having a base region having an emitter region on the surface, a collector region, and an emitter electrode connected to the emitter region and the base region Cell structure of
A dummy base region that is adjacent to the cell structure and has no emitter region connected to the emitter electrode on a surface portion;
A connection portion for electrically connecting the peripheral diffusion region to the emitter electrode,
2. The insulated gate semiconductor device according to claim 1, wherein the base region and the dummy base region are alternately arranged with the trench gate interposed therebetween.   2. The insulated gate semiconductor device according to claim 1, wherein the emitter electrode is divided into a plurality of divided portions of two columns and the connection portion is provided at an end of each divided portion.   A gate electrode is provided in one of the corner portions of the columns at both ends, and the peripheral diffusion region extends between the gate electrode and the divided emitter electrode provided in the partition to which the corner portion belongs. 3. The insulated gate semiconductor device according to claim 2, wherein the connection portion is provided between a peripheral diffusion region and the divided emitter electrode.

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