JP4085073B2 - Vertical semiconductor device - Google Patents

Description

  The present invention relates to a vertical semiconductor device, and more particularly to a vertical insulated gate transistor (hereinafter simply referred to as IGBT).

  An IGBT as an insulated gate type high-breakdown-voltage semiconductor device is easily controlled by voltage control, and is widely used in the field of power electronics such as inverters and switching power supplies. In particular, the IGBT is a power device that combines high-speed switching characteristics of MOSFETs and high-output characteristics of bipolar transistors. A lateral IGBT advantageous for high integration is often used as an output device of a power IC. A power IC including a plurality of output devices is often manufactured using an SOI (Semiconductor On Insulator) substrate that is advantageous for dielectric separation.

  This type of conventional lateral IGBT will be described with reference to FIGS. 24 is a plan view of the IGBT, and FIG. 25 is a cross-sectional view taken along the line AA ′ of FIG.

The SOI substrate 1101 has a support substrate 1102, a buried oxide film 1103, and an n ⁻ type base layer 1104. An n-type buffer layer 1105 is selectively diffused in the surface of the n ⁻ -type base layer 1104, and the n-type buffer layer 1105 has a stripe shape in which both end portions protrude outward in an arc shape. Yes. A p-type drain layer 1106 is selectively diffused on the surface of the n-type buffer layer 1105, and the p-type drain layer 1106 has the same shape as the n-type buffer layer 1105.

A p-type base layer 1107 is selectively diffused and formed in the surface of the n ⁻ -type base layer 1104 so as to surround the n-type buffer layer 1105, and the p-type base layer 1107 has an inner peripheral surface that is n-type buffer layer 1105. Have the same shape. A striped n ⁺ -type source layer 1108 is selectively diffused and formed on the p-type base layer 1107 on both sides of the p-type drain layer 1106, and the n ⁺ -type source layer 1108 is a straight portion of the p-type drain layer 1106. Are formed in substantially the same length.

A gate electrode 1110 is formed on the p-type base layer 1107 sandwiched between the n ⁻ -type base layer 1104 and the n ⁺ -type source layer 1107 with a gate insulating film 1109 interposed therebetween. The gate electrode 1110 is formed in an annular structure so as to surround the n-type buffer layer 1105, and the inner peripheral surface has the same shape as the outer peripheral surface of the n-type buffer layer 1105. Further, a gate wiring 1113 for taking out the electrode to the outside is provided in a part of the gate electrode.

An insulating film 1111 is formed on the exposed surfaces of the gate electrode 1110 and the n ⁻ -type base layer 1104. A drain wiring 1112 and a source wiring 1114 are formed on the insulating film 1111. Contact holes 1115 are formed at predetermined positions in the insulating film 1111. Through these contact holes 1115, the drain wiring 1112 is in ohmic contact with the p-type drain layer 1106, and the source wiring 1114 is connected to the p-type base. The layer 1107 and the n ⁺ type source layer 1108 are in ohmic contact.

  In such a lateral IGBT, in order to obtain a high breakdown voltage characteristic, it is necessary to increase the arc-shaped curvature R at both ends of the n-type buffer layer 1105 to some extent. For this purpose, the n-type buffer layer The width Lb of 1105 needs to be increased. When the width Lb of the n-type buffer layer 1105 is increased, the width of the p-type drain layer 1106 is also increased, and the area of the p-type drain layer 1106 is necessarily increased.

  However, it has been found from experiments by the inventors that the on-voltage of the IGBT increases as the area of the p-type drain layer 1106 increases by increasing the width Lb of the n-type buffer layer 1105. FIG. 26 is a diagram showing the relationship between the area of the p-type drain layer and the on-voltage of the IGBT. As can be seen from FIG. 26, in the conventional IGBT, when the width Lb of the n-type buffer layer 105 is increased in order to obtain a high breakdown voltage characteristic, the area of the p-type drain layer 106 increases and the on-voltage increases. There was a problem.

  Next, a conventional vertical IGBT will be described. FIG. 27 shows a longitudinal sectional view of a conventional vertical IGBT.

This IGBT includes a drain electrode 1201, a p-type drain layer 1202, an n-type buffer layer 1203, an n ⁻ -type base layer 1204, a p-type base layer 1205, an n-type ⁺ source layer 1206, a gate insulating film 1207, a gate electrode 1208, a source An electrode 1209 is provided.

In this structure, when a positive voltage is applied to the source electrode 1209 with respect to the source electrode 1209 in a state where a positive voltage is applied to the drain electrode 1201, the p-type base layer 1205 below the gate electrode 1208 is applied. through a channel formed in the surface of, ^{n +} -type source layer 1206 the n ^- short -type base layer 1204, n ^- -type base layer 1204 and electrons are injected into. From the p-type drain layer 1202, holes corresponding to the injected electrons are injected into the n ⁻ -type base layer 1204.

As a result, the high resistance n ⁻ -type base layer 1204 is conductivity-modulated to become low resistance, and the on-voltage can be made lower than that of the MOSFET having the same forward blocking characteristic.

In order to turn off the IGBT, application of a positive voltage to the gate electrode 1208 may be stopped. Thereby, the injection of electrons into the n ⁻ -type base layer 1204 is stopped, and the injection of holes is stopped accordingly. However, n ^- -type base layer 1204 remaining electrons and holes in the due to expansion of the depletion layer due to the voltage increase drift current and the n ^- become a recombination current that depends on the lifetime of the mold base layer 1204, while Continue to flow.

  Therefore, in order to reduce the loss at the turn-off time of the IGBT while the on-voltage is kept low, as shown in FIG. 28, the carrier amount on the source electrode 1209 side is increased and the carrier amount on the drain electrode 1201 side is decreased in the on state. Things are necessary. This is because the depletion layer spreads from the source side and carriers on the drain side remain until the end.

  As a technique for reducing the carrier amount on the drain side, a method using a low-concentration p-type drain layer 1202 is proposed in the following document.

J. Fugger et al., "Optimizing the vertical IGBT structure-The NPT concept as the most economic and electrically ideal solution for a 1200V IGBT", Proceedings of the 8th ISPSD, pp. 169-172, 1996
In this method, the n-type buffer layer 1203 needs to be formed at the minimum concentration necessary to maintain the forward blocking voltage, and the p-type drain layer 1202 needs to be formed at a low concentration to suppress hole injection. is there.

  As a method for forming the p-type drain layer 1202, diffusion from high-temperature annealing to ion implantation of boron is used. However, due to surface dripping due to diffusion, the surface concentration of boron becomes low, an ohmic junction cannot be realized with respect to the drain electrode 1201, and hole injection hardly occurs. In addition, since the boron implantation dose is small, there is a problem that if the dose varies even slightly, the device characteristics change greatly and the process margin is small.

  Further, other problems in the vertical semiconductor device will be described. An IGBT is a low-loss semiconductor device, but in recent years, attempts have been made to reduce the thickness of the substrate in order to reduce the loss. For example, in an IGBT with a withstand voltage of 600 V class, the thickness of the substrate is reduced to 50 μm.

However, when the substrate is thinned and the n ⁻ -type base layer is thinned, there is a problem that the substrate is broken in the element manufacturing process.

  As described above, in the conventional vertical semiconductor device, it is necessary to form the p-type collector layer 1202 having a very low concentration in order to obtain a good trade-off relationship between the on-voltage and the turn-off loss. Diffusion from high-temperature annealing to ion implantation, which is a formation method, makes it difficult to control the surface concentration and causes variations in device characteristics.

  The first object of the present invention is to provide a vertical semiconductor device capable of realizing both a good on-voltage and a reduction in turn-off loss.

  Furthermore, conventionally, there has been a problem that the substrate is broken in the device manufacturing process when the loss is reduced by making the substrate thinner and the n-type base layer thinner.

  Accordingly, a second object of the present invention is to provide a vertical semiconductor device capable of realizing a reduction in loss without reducing the thickness of the substrate.

A vertical semiconductor device according to an aspect of the present invention includes a first conductive semiconductor substrate having a higher resistance than a first conductive buffer layer, and the first conductive formed on one surface of the first conductive semiconductor substrate. A first buffer layer, a plurality of first grooves formed in the other surface portion of the first conductive semiconductor substrate, and a shallower portion than the first groove in the other surface portion of the first conductive semiconductor substrate. The second conductivity type base layer formed, the first conductivity type source layer formed on both sides of each first groove in the surface portion of the second conductivity type base layer, the side wall of the first groove, and A first insulating film formed on a bottom surface; a gate electrode formed so as to be embedded in the first trench through the first insulating film; the first conductivity type source layer; A source electrode formed to connect to the conductive type base layer; A second groove formed on the first conductivity type buffer layer,
In the second insulating film formed on the side wall of the second groove, the second conductivity type first drain layer formed on the bottom surface portion of the second groove, and the surface portion of the first conductivity type buffer layer A second conductivity type second drain layer formed shallower than the second trench; and a second conductivity type second drain layer embedded in the second trench via the second insulating film. A buried drain electrode connected to one drain layer, and a drain electrode connected to the second conductivity type second drain layer and the buried drain electrode are provided.

  The vertical semiconductor device according to an aspect of the present invention includes a first conductive semiconductor substrate having a higher resistance than the first conductive buffer layer and the first conductive semiconductor substrate formed on one surface of the first conductive semiconductor substrate. A first conductivity type buffer layer; a second conductivity type base layer selectively formed on the other surface portion of the first conductivity type semiconductor substrate; and a selectively formed on a surface portion of the second conductivity type base layer. A first conductive type source layer; a gate insulating film formed on the second conductive type base layer between the first conductive type source layer and the first conductive type semiconductor substrate; and the gate insulating film. A gate electrode formed on the second conductivity type base layer, a source electrode formed to be connected to the first conductivity type source layer and the second conductivity type base layer, and the first conductivity type. A groove formed in the buffer layer and formed on the sidewall of the groove; An insulating film; a second conductivity type first drain layer formed on a bottom portion of the groove; and a second conductivity type second drain layer formed shallower than the groove on a surface portion of the first conductivity type buffer layer. A buried drain electrode that is buried in the trench through the insulating film, and is connected to the second conductivity type first drain layer; the second conductivity type second drain layer; and the buried drain electrode. And a drain electrode connected to each other.

  According to the vertical semiconductor device of the present invention, the surface concentration of the drain layer can be formed high by controlling the injection of holes by the area ratio in the drain layer, so that the vertical concentration is not affected by process variations. The turn-off characteristics of the type IGBT can be improved.

  Furthermore, according to the vertical semiconductor device of the present invention, the thickness from the drain layer formed on the bottom surface of the groove to the substrate on the source side is reduced to reduce the loss, and the thickness of the entire substrate is increased. Since the strength can be improved, the substrate can be prevented from cracking in the manufacturing process or the like.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the embodiments, an n-channel IGBT is shown in which the first conductivity type is n-type and the second conductivity type is p-type. In addition, components having substantially the same functions and configurations are denoted by the same reference numerals, and redundant description will be provided only when necessary.

(First reference example)
FIG. 1 is a plan view schematically showing a lateral IGBT according to a first reference example of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG.

The SOI substrate 1 includes a silicon support substrate 2, a buried oxide film 3, and a high resistance (low concentration) n ⁻ -type silicon active layer 4. In the IGBT of the present reference example, n ^- used as a mold base layer 14, n ^{- -} type silicon active layer 4 n The inner surface of the mold base layer 14, n-type buffer layer 15 is selectively formed by diffusion, and The n-type buffer layer 15 has a stripe shape with upper and lower ends projecting outward in an arc shape with a curvature R. A p-type drain layer 16 is selectively diffused on the surface of the n-type buffer layer 15.

  In this reference example, the p-type drain layer 16 is similar in shape to the n-type buffer layer 15 and has an annular structure.

A p-type base layer 17 is selectively diffused in the surface of the n ⁻ -type base layer 14 so as to be separated from the n-type buffer layer 15 and surround the n-type buffer layer 15. 17 has an inner peripheral surface similar to the n-type buffer layer 15.

Striped n ⁺ -type source layers 18 are selectively diffused and formed on the p-type base layer 17 on both sides of the p-type drain layer 16, and the n ⁺ -type source layer 18 is a straight line of the p-type drain layer 16. It is formed to have substantially the same length as the portion.

A gate electrode 20 is formed on the surface of the p-type base layer 17 sandwiched between the n ⁻ -type base layer 14 and the n ⁺ -type source layer 18 via a gate insulating film 19. The gate electrode 20 is formed in an annular structure so as to surround the n-type buffer layer 15, and the inner and outer peripheral surfaces have a shape similar to that of the n-type buffer layer 15. Furthermore, a gate wiring 23 for taking out the electrode to the outside is provided in a part of the gate electrode.

An insulating film 21 is formed on the exposed surfaces of the gate electrode 20 and the n ⁻ type base layer 14. On the insulating film 21, a drain wiring 22 and a source wiring 24 are formed.

Contact holes 25 are respectively formed at predetermined positions in the insulating film 21, the drain wiring 22 is in ohmic contact with the p-type drain layer 16 through the contact holes 25, and the source wiring 24 is connected to the p-type base. The layer 17 and the n ⁺ -type source layer 18 are in ohmic contact.

  According to the lateral IGBT of this reference example, the p-type drain layer 16 has an annular structure, and the area of the p-type drain layer 16 is small.

  Therefore, even if the width Lb of the n-type buffer layer 15 is increased and the breakdown voltage is increased by the reduction in the area of the p-type drain layer, the on-voltage does not increase.

(Second reference example)
FIG. 3 is a plan view of a lateral IGBT according to a second reference example of the present invention. Since this AA ′ cross section is the same as FIG.

  The difference between this reference example and the first reference example is that, in the first reference example, the p-type drain layer 16 has a ring structure, whereas in this reference example, the p-type drain layer 36 is One of upper and lower ends of the annular p-type drain layer 16 in the first reference example, for example, a horseshoe structure or an inverted U-shaped structure formed by cutting the lower end in the horizontal direction (left and right in the drawing). It is a point to have. Other configurations are the same as those in the first reference example.

  Also in the lateral IGBT of this reference example, the area of the p-type drain layer 36 is formed small, and the breakdown voltage can be increased without increasing the on-voltage as in the first reference example. Can do.

  Further, current concentrates on the arc-shaped end portion of the p-type drain layer 36, and there is a possibility that the element is broken at this portion, but in the first reference example, there are two places in the upper and lower sides. In this reference example, there is only one place, and there is little risk of element destruction.

  Here, the p-type drain layer 16 in the first reference example may be an aggregate of a plurality of strip-shaped drain layer portions 16a as shown in FIG.

  Similarly, the p-type drain layer 36 in the second reference example may be an aggregate of a plurality of strip-shaped drain layer portions 36a as shown in FIG.

(Third reference example)
FIG. 6 is a plan view of a lateral IGBT according to a third reference example of the present invention. Since this AA ′ cross section is the same as FIG.

  The difference between this reference example and the first reference example is that in the first reference example, the p-type drain layer 16 has a ring structure, whereas in this reference example, the p-type drain layer 46 is The upper and lower end portions of the p-type drain layer 16 having the annular structure of the first reference example are cut in the horizontal direction to form two stripe structures.

  Other configurations are the same as those in the first reference example.

  Also in this reference example IGBT, the area of the p-type drain layer 46 is small, and the breakdown voltage can be increased without increasing the on-voltage as in the case of the first reference example.

  In addition, since there are no arc-shaped portions at the upper and lower end portions of the p-type drain layer, there is no possibility of element destruction due to current concentration in the arc-shaped portions as in the first and second reference examples.

(Fourth reference example)
FIG. 7 is a plan view of a lateral IGBT according to a fourth reference example of the present invention. Since this AA ′ cross section is the same as FIG.

  The difference between this reference example and the first reference example is that in the first reference example, the p-type drain layer 16 has a ring structure, whereas in this reference example, the p-type drain layer 56 is The upper and lower ends of the p-type drain layer 16 having the annular structure of the first reference example are cut in the horizontal direction to form two stripes, and each striped p-type drain layer is cut in the horizontal direction. However, it is divided into a plurality of p-type drain layer portions 56a. In other words, the p-type drain layer 46 in the third reference example is divided into meshes. Other configurations are the same as those in the first reference example.

  In the lateral IGBT of this reference example, the area of the p-type drain layer 56 is smaller than that of the p-type drain layers 16, 36, and 46 in the first to third reference examples. Compared to the reference example, the breakdown voltage can be increased.

  Further, since there are no arc-shaped portions at the upper and lower end portions of the p-type drain layer 56, there is no fear of element destruction due to current concentration on the arc-shaped portions as in the first and second reference examples.

(Fifth reference example)
FIG. 8 is a plan view of a lateral IGBT according to a fifth reference example of the present invention. The AA ′ cross section is the same as FIG.

  The difference between this reference example and the first reference example is that in the first reference example, the p-type drain layer 16 has a ring structure, whereas in this reference example, the p-type drain layer 66 is The p-type drain layer is formed in a stripe shape, and the p-type drain layer is further divided into a plurality of p-type drain layer portions 66a in the horizontal direction. That is, strip-shaped p-type drain layer portions 66a are arranged in a ladder shape. Other configurations are the same as those in the first reference example.

  Also in the lateral IGBT of this reference example, the area of the p-type drain layer 66 is formed small, and the breakdown voltage can be increased without increasing the on-voltage as in the above reference example.

  In addition, since there are no arc-shaped portions at the upper and lower end portions of the p-type drain layer 66, there is no fear of element destruction due to current concentration in the arc-shaped portions as in the first and second reference examples.

  In addition, it is not limited to the said 1st reference example-5th reference example, It can implement in various changes.

  For example, in the above-described reference example, an n-channel lateral IGBT in which the first conductivity type is n-type and the second conductivity type is p-type is illustrated, but the present invention can also be applied to a p-channel lateral IGBT. In this case, the first conductivity type may be p-type and the second conductivity type may be n-type.

  Further, the present invention is not limited to the structure of the drain layer of the above reference example, and may be combined. For example, as described with reference to FIGS. 4 and 5, the drain layer having the annular structure and the drain layer having the horseshoe shape (inverted U shape) are combined with the first and second reference examples, respectively. May be divided into a plurality of parts, and a drain structure having a ring structure composed of a plurality of divided drain layers or a horseshoe structure may be used.

  Further, the present invention is not limited to the IGBT of the above reference example, and can be applied to other bipolar elements such as npn and pnp transistors and GTO and EST.

  Next, vertical IGBTs according to first to fifth embodiments of the present invention will be described.

(First embodiment)
A vertical IGBT according to the first embodiment of the present invention will be described with reference to FIG.

In the vertical IGBT shown in FIG. 27, a p-type drain layer 1202 is formed on the entire drain side of the device. On the other hand, in the present embodiment, the p-type drain layer 110 is formed not on the entire drain side but on a part of the n-type buffer layer 103. Accordingly, the drain electrode 111 is formed not on the entire collector side but on the p-type drain layer 110. The other n ⁻ type base layer 104, p type base layer 105, n ⁺ type source layer 106, gate insulating film 107, gate electrode 108, and source electrode 109 are the same as the n ⁻ type base layer 1204, p shown in FIG. This is the same as the type base layer 1205, the n ⁺ type source layer 1206, the gate insulating film 1207, the gate electrode 1208, and the source electrode 1209, and description thereof is omitted.

Here, the surface concentration (Cp) of the p-type drain layer 110 is set so that a complete ohmic contact can be obtained with the drain electrode 111.
Cp> 1 × 10 ¹⁹ cm ⁻³
It forms so that it may satisfy. This numerical value is based on the description of the following literature.

SMSze, physics of Semiconductor Devices 2nd Edition, p.305, 1981
By making the p-type drain layer 110 as described above, the hole injection efficiency from the drain electrode 111 can be adjusted by the area ratio, not by the concentration of the p-type drain layer 110. FIG. It is possible to solve the problem of the process margin related to the ohmic junction and the dose variation in the IGBT shown in FIG.

(Second Embodiment)
FIG. 10 shows a cross section of a vertical IGBT according to the second embodiment of the present invention. Compared to the first embodiment, the gate electrode 108 is a planar type in the first embodiment, but the gate electrode 118 is a trench type in the first embodiment. By making the gate electrode 118 on the source side into such a trench type, the channel density of the MOS can be increased and the amount of carriers on the source electrode 119 side can be increased. The structures of the p-type drain layer 110 and the drain electrode 111 on the drain side are the same as those in the first embodiment, and a description thereof is omitted.

(Third embodiment)
FIG. 11 shows a longitudinal section of a vertical IGBT according to the third embodiment of the present invention. In this embodiment, on the source side, the gate electrode 118 is a trench type similar to the seventh embodiment, but the source electrode 129 connected to the p-type base layer 115 and the n ⁺ -type source layer 126 is fixed. It is different in that the number is reduced by thinning out at the rate of. As a result, the hole discharge resistance can be increased to facilitate electron injection. Such a structure on the source side is proposed in the following document in order to increase the carrier amount on the source side.

M. Kitagawa et al., "A 4500V Injection Enhanced Insulated Gate Bipolar Transistor (IEGT) in a Mode Similar to a Thyristor", IEDM'93, pp.679-682, 1993
The structures of the p-type drain layer 110 and the drain electrode 111 on the drain side are the same as those in the first and second embodiments, and a description thereof is omitted.

(Fourth embodiment)
FIG. 12 shows a vertical cross section of a vertical IGBT according to the fourth embodiment of the present invention.

  Compared to the first embodiment shown in FIG. 9, the difference is that a barrier metal layer 112 is formed between the drain electrode 111 and the p-type drain layer 110. Other configurations are the same as those of the first embodiment, and a description thereof will be omitted.

  In order to suppress injection of holes from the drain side, it is necessary to increase the surface concentration of the p-type drain layer 110 and to form a shallow diffusion on the surface of the n-type buffer layer 103. However, when the drain electrode 111 is formed of aluminum which is usually used, aluminum sucks out silicon and penetrates, and the amount of injected holes cannot be controlled. Therefore, in this embodiment, by inserting a barrier metal layer 112 (for example, TiN, TiW, Ti) between the drain electrode 111 and the p-type drain layer 110, aluminum in the drain electrode 111 sucks silicon. Can be reduced.

  Here, the same effect can be obtained even if the barrier metal layer 112 is provided between the drain electrode 111 and the p-type drain layer 110 in the second embodiment or the third embodiment.

(Fifth embodiment)
FIG. 13 shows a vertical sectional structure of a vertical semiconductor device according to the fifth embodiment of the present invention.

In the present embodiment, an n-type buffer layer 202 is formed relatively deeply on one surface (the lower surface side in the figure) of the n ⁻ -type substrate 201, and a p-type drain layer 209 is connected to the n-type buffer layer 202. It is characterized in that it is formed by introducing impurities into the bottom surface portion of the trench type groove 207 formed in (1). The impurity profile in the depth direction in this case is shown in FIG.

  First, according to the present embodiment, since the deep n-type buffer layer 202 is formed, the entire substrate can be made thick and have sufficient strength.

Further, according to the present embodiment, the p-type drain layer 209 is formed on the bottom surface portion of the groove 207 formed in the n-type buffer layer 202, so that the thickness from the n-type buffer layer 202 to the upper surface of the n ⁻ -type substrate 201 is increased. The thickness can be made sufficiently thin.

Specifically, for example, an n-type buffer layer 202 having a thickness of 100 to 350 μm is formed by diffusing impurities on the lower surface side of the n ⁻ type substrate 201 having a thickness of 150 to 400 μm in the drawing, and the n-type buffer layer 202 has a depth. A groove 207 of 90 to 340 μm is formed. When impurities are introduced into the bottom surface of the groove 207 to form the p-type drain layer 209, the thickness from the n-type buffer layer 202 to the upper surface of the n ⁻ -type substrate 201 becomes sufficiently thin, such as about 50 to 60 μm.

  Further, since the drain layer 209 is formed separately, lower loss can be realized.

  Next, a method for manufacturing a vertical semiconductor device according to the present embodiment will be briefly described for each process. However, since the source side process is the same as the conventional process, the description of this part is omitted.

As shown in FIG. 15, for example, an n ⁻ -type substrate 201 having a thickness of 150 to 400 μm is prepared, and an n-type buffer layer 202 is formed by diffusing impurities from the lower surface in the figure. Next, as shown in FIG. 16, the surface of the n-type buffer layer 202 is oxidized to form a silicon oxide film 203. Then, the silicon oxide film 203 is etched to selectively remove a portion where a groove is to be formed.

  As shown in FIG. 17, anisotropic etching is performed using the remaining silicon oxide film 203 as a mask to form a trench-type groove 207.

  As shown in FIG. 18, the entire surface on the n-type buffer layer 202 side is oxidized to form a silicon oxide film 208. When this silicon oxide film 208 is etched back, as shown in FIG. 19, the silicon oxide film 208 remains on the side wall of the groove 207, and the silicon oxide film 208 on the bottom of the groove 207 and the surface of the n-type buffer layer 202 is removed. The

  When boron is ion-implanted from this state and annealed, a p-type drain layer 209 is formed at the bottom of the trench 207 as shown in FIG. 20, and a p-type drain layer 210 is simultaneously formed on the surface of the n-type buffer layer 202. Is done. Thereafter, as shown in FIG. 13, a buried drain electrode 211 is formed in the groove 207, and a drain electrode 212 is formed on the entire surface.

Incidentally, regarding the formation of the n-type buffer layer 202, for example, a thick n ^- type substrate 201 such as 650 μm is diffused and formed thick, and then ground to a desired thickness. Also good.

  Alternatively, as shown in FIG. 21, a high-resistance epitaxial layer 221 may be formed on the surface of the n-type buffer layer 202. The impurity profile in this case is shown in FIG.

In this embodiment mode, the gate structure is a trench type. However, as shown in FIG. 23, a p-type base layer 231, an n ⁺ -type source layer 232, a source electrode 235, a gate insulating film 233, and a gate electrode 234 are provided. It may be a planar type.

  The above-described embodiments are merely examples, and various modifications can be made without departing from the technical scope of the present invention.

The top view of the horizontal type IGBT concerning the 1st reference example of this invention. FIG. 2 is a longitudinal sectional view of a lateral IGBT along the line A-A ′ in FIG. 1. The top view of the horizontal IGBT concerning the 2nd reference example of this invention. The top view which showed the modification of horizontal type IGBT concerning the said 1st reference example. The top view which showed the modification of horizontal IGBT concerning the said 2nd reference example. The top view of horizontal IGBT concerning the 3rd reference example of this invention. The top view of the horizontal IGBT concerning the 4th reference example of this invention. The top view of the horizontal IGBT concerning the 5th reference example of this invention. 1 is a longitudinal sectional view of a vertical IGBT according to a first embodiment of the present invention. The longitudinal cross-sectional view of the vertical IGBT concerning the 2nd Embodiment of this invention. The longitudinal cross-sectional view of the vertical IGBT concerning the 3rd Embodiment of this invention. The longitudinal cross-sectional view of the vertical IGBT concerning the 4th Embodiment of this invention. The longitudinal cross-sectional view of the vertical IGBT concerning the 5th Embodiment of this invention. Explanatory drawing which showed the density | concentration profile of the same vertical IGBT. The longitudinal cross-sectional view which showed the process of manufacturing vertical IGBT concerning the said 5th Embodiment. The longitudinal cross-sectional view which showed the process of manufacturing vertical IGBT concerning the said 5th Embodiment. The longitudinal cross-sectional view which showed the process of manufacturing vertical IGBT concerning the said 5th Embodiment. The longitudinal cross-sectional view which showed the process of manufacturing vertical IGBT concerning the said 5th Embodiment. The longitudinal cross-sectional view which showed the process of manufacturing vertical IGBT concerning the said 5th Embodiment. The longitudinal cross-sectional view which showed the process of manufacturing vertical IGBT concerning the said 5th Embodiment. The longitudinal cross-sectional view which showed the modification of vertical IGBT concerning the said 5th Embodiment. Explanatory drawing which showed the density | concentration profile of the same vertical IGBT. The longitudinal cross-sectional view which showed the other modification of the vertical IGBT concerning the said 5th Embodiment. The top view of the conventional horizontal IGBT. FIG. 25 is a cross-sectional view of a lateral IGBT along the line A-A ′ of FIG. 24. The graph which shows the relationship between the area of a drain layer, and the ON voltage of IGBT obtained by experiment. The top view of the conventional vertical IGBT. Explanatory drawing which showed the density | concentration profile of the same vertical IGBT.

Explanation of symbols

1 SOI substrate 2 Support substrate (silicon)
3 buried oxide film 4 silicon active layer 14 n ⁻ type base layer 15 n type buffer layers 16, 16 a, 36, 36 a, 46, 56, 66, 106 p type drain layer 17 p type base layer 18 n ⁺ type source layer 19 Gate insulating film 20 Gate electrode 21 Insulating film 22 Drain wiring 23 Gate wiring 24 Source wiring 25 Contact hole Lb Width of n-type buffer layer (1/2 width)
56a, 66a p-type drain layer portion 103 n-type buffer layer 104 n-type base layer 105, 115 p-type base layer 106, 116, 126 n-type source layer 107, 117 gate insulating film 108, 118 gate electrodes 109, 119, 129 Source electrode 110 P-type drain layer 111 Drain electrode 112 Barrier metal 201 n ⁻ type semiconductor substrate 202 n type buffer layer 203 and 208 Silicon oxide film 207 Groove 209 and 210 P type drain layer 211 Embedded drain electrode 212 Drain electrode 221 n ⁻ type Epitaxial layer 231 p-type base layer 231
232 n-type source layer 233 Gate insulating film 234 Gate electrode 235 Source electrode

Claims (2)

A first conductivity type semiconductor substrate having a higher resistance than the first conductivity type buffer layer;
The first conductivity type buffer layer formed on one surface of the first conductivity type semiconductor substrate; a plurality of first grooves formed on the other surface portion of the first conductivity type semiconductor substrate;
A second conductivity type base layer formed shallower than the first groove in the other surface portion of the first conductivity type semiconductor substrate;
A first conductivity type source layer formed on both sides of each of the first grooves in the surface portion of the second conductivity type base layer;
A first insulating film formed on a side wall and a bottom surface of the first groove;
A gate electrode formed so as to be embedded in the first trench through the first insulating film;
A source electrode formed to connect to the first conductivity type source layer and the second conductivity type base layer;
A second groove formed in the first conductivity type buffer layer;
A second insulating film formed on a side wall of the second groove;
A second conductivity type first drain layer formed on a bottom surface portion of the second groove;
A second conductivity type second drain layer formed shallower than the second groove in the surface portion of the first conductivity type buffer layer;
A buried drain electrode formed so as to be buried in the second trench through the second insulating film and connected to the second drain type first drain layer;
A vertical semiconductor device comprising: the second conductivity type second drain layer; and a drain electrode connected to the buried drain electrode. A first conductivity type semiconductor substrate having a higher resistance than the first conductivity type buffer layer;
The first conductivity type buffer layer formed on one surface of the first conductivity type semiconductor substrate, and the second conductivity type base layer selectively formed on the other surface portion of the first conductivity type semiconductor substrate. When,
A first conductivity type source layer selectively formed on a surface portion of the second conductivity type base layer;
A gate insulating film formed on the second conductivity type base layer between the first conductivity type source layer and the first conductivity type semiconductor substrate;
A gate electrode formed on the second conductivity type base layer via the gate insulating film;
A source electrode formed to connect to the first conductivity type source layer and the second conductivity type base layer;
A groove formed in the first conductivity type buffer layer;
An insulating film formed on the sidewall of the groove;
A second conductivity type first drain layer formed on the bottom surface of the groove;
A second conductivity type second drain layer formed shallower than the groove in the surface portion of the first conductivity type buffer layer;
A buried drain electrode formed so as to be buried in the trench through the insulating film and connected to the second drain type first drain layer;
A vertical semiconductor device comprising: the second conductivity type second drain layer; and a drain electrode connected to the buried drain electrode.

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