JP6528640B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

  The present invention relates to an insulated gate semiconductor device having a trench gate structure.

  In the field of power electronics, semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used as switching elements for controlling power supply to loads such as motors. One of the insulated gate semiconductor devices for power control is a trench gate MOSFET formed by embedding a gate electrode in a semiconductor layer.

In the trench gate type MOSFET, it is possible to realize low resistance by improving the channel density, and in the trench gate type MOSFET described in Patent Document 1, the trench is formed in a lattice shape to realize low resistance. ing.
Here, in the trench gate type MOSFET, a gate electrode made of polysilicon or the like is embedded in the trench via the gate insulating film, and a channel is formed in a base region in contact with the trench. In order to turn on this trench gate type MOSFET, a voltage that inverts the base region is applied to the gate electrode, and a voltage applied to the gate electrode is applied to the base region through the gate insulating film. The electric field generated by this voltage forms a channel in the base region.

Japanese Patent Application Publication No. 2007-531246

  In a trench gate type MOSFET in which trenches are formed in a lattice, intersections are generated by the lattice. There are corners in the channel at the intersection. When a voltage is applied to the gate electrode, an electric field is concentrated at the corner of the channel, and an electric field larger than the gate insulating film other than the corner is applied. Therefore, the corner channel is turned on earlier than in the other places. Since the threshold voltage of the entire device is determined at the place where the device is turned on most quickly, as a result, the threshold voltage of the entire device is lowered, and the tradeoff relationship between the on resistance and the threshold voltage is deteriorated. Could lead to a malfunction of the system.

  The present invention has been made to solve the above-mentioned problems, and the corner of the intersection is first turned on while the lattice trench structure having a large channel density is maintained, and the threshold voltage is lowered. To provide a semiconductor device in which the trade-off relationship between on-resistance and threshold voltage is improved.

A semiconductor device according to the present invention includes a semiconductor substrate, a drift layer of a first conductivity type provided on the semiconductor substrate, a first base region of a second conductivity type located on the surface side of the drift layer, and A source region of a first conductivity type located in the base region of the gate, a trench sidewall formed of a plurality of planes penetrating the first base region and the source region, and formed in a lattice shape; The gate insulating film formed in contact with the side wall of the trench, the gate electrode embedded in the trench via the gate insulating film, and the side wall of the trench other than the corner portion having a higher impurity concentration than the impurity concentration of the first base region formed in a portion in contact, and a second base region of a second conductivity type, said second base region 0.1μm from the trench sidewalls It is characterized in that is formed with a width of 0.5 [mu] m.

  According to the semiconductor device of the present invention, the impurity concentration of the base region in contact with the gate insulating film at the corner is made higher than that at other than the corner, so that the partial threshold voltage of the channel formed near the corner is high. It is possible to prevent the corner from turning on first. In addition, channels other than the corner can be set to appropriate threshold voltages, and the trade-off between on-resistance and threshold voltage can be improved.

It is a top view which shows a part of active region of trench gate type MOSFET concerning Embodiment 1 of this invention. It is sectional drawing of a part of active region of trench gate type MOSFET which concerns on Embodiment 1 of this invention. It is a figure which shows the voltage-current characteristic in the ON state of the trench gate type MOSFET which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of trench gate type | mold MOSFET which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of trench gate type | mold MOSFET which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of trench gate type | mold MOSFET which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of trench gate type | mold MOSFET which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of trench gate type | mold MOSFET which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of trench gate type | mold MOSFET which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of trench gate type | mold MOSFET which concerns on Embodiment 1 of this invention. It is a top view of a part of cell region for demonstrating the manufacturing method of trench gate type MOSFET concerning Embodiment 1 of this invention. It is sectional drawing of a part of active region of trench gate type MOSFET which concerns on Embodiment 2 of this invention. It is a top view of a part of active region of trench gate type MOSFET concerning Embodiment 2 of this invention.

Embodiment 1
First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described.
FIG. 1 is a top view schematically showing a part of an active region of a trench gate type MOSFET which is a semiconductor device according to a first embodiment. As shown in FIG. 1, in the active region of the trench gate type MOSFET of the present embodiment, there is a portion in which nine square cells are arranged side by side as viewed from the top. 2 is a cross-sectional view schematically showing a part of the active region of the trench gate type MOSFET according to the first embodiment, and an AA cross-sectional view shown by an alternate long and short dash line in FIG. 1B corresponds to FIG. 2B, and a B-B cross-sectional view shown by a two-dot chain line in FIG. Here, the B-B cross-sectional view is a cross-sectional view including, in particular, corner portions of the intersections of the trenches arranged in a lattice.
In FIG. 1, the source electrode, the interlayer insulating film, and the contact hole are not shown so that the cell configuration of the trench gate type MOSFET can be easily understood.

The configuration of the cell of the trench MOSFET according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG.
In the trench type MOSFET which is a semiconductor device according to the first embodiment of the present invention, n type epitaxial layer 2 made of silicon carbide is formed on the first main surface of low resistance n type silicon carbide semiconductor substrate 1. It is done. A p-type first base region 3 made of silicon carbide is formed in part of the surface layer portion of the epitaxial layer 2. A region of the epitaxial layer 2 below the first base region 3 where the first base region 3 is not formed is the drift layer 2a.

  An n-type source region 4 is formed in part of the surface layer portion of the first base region 3. A trench 5 is formed in the epitaxial layer 2 in a portion where the first base region 3 and the source region 4 are formed so as to penetrate the source region 4 and the first base region 3. The trenches 5 are formed in a lattice shape so as to intersect vertically and horizontally when viewed from the top. The intervals between adjacent trenches 5 are equal. The bottom of the trench 5 reaches the drift layer 2 a below the first base region 3. Inside the trench, a gate insulating film 6 is formed in contact with the inner wall so as to cover the inner wall including the bottom and the side wall. A gate electrode 7 is formed on the inner side of the gate insulating film 6 opposite to the inner wall of the trench.

An interlayer insulating film 8 is formed on the surface of the epitaxial layer 2 so as to cover the gate electrode 7. In interlayer insulating film 8, contact holes 81 reaching source region 4 and first base region 3 are formed. Source electrode 9 provided on interlayer insulating film 8 is formed to fill contact hole 81 and connected to source region 4 and first base region 3. As described above, in FIG. 1, the interlayer insulating film 8, the source electrode 9, and the contact hole 81 on the epitaxial layer 2 are omitted, so the contact hole 81 is not shown in FIG. The contact hole 81 shown is a rectangular space in top view.
In addition, drain electrode 10 is formed on a second main surface which is a surface opposite to the first main surface of silicon carbide semiconductor substrate 1.

As shown in FIG. 1, the gate electrodes 7 are arranged in a grid in top view. In the cell provided in the active region of the trench gate MOSFET, each of the sections separated by the gate electrode 7 functions as a trench gate type MOSFET.
Although not shown, a termination region is provided outside the active region as viewed from the top, and the trench gate type MOSFET is composed of an active region and a termination region.

Here, in the trench gate type MOSFET according to the present embodiment, as shown in FIG. 2B, the p-type second MOSFET is faced to the corner portion formed at the intersection of the lattice-shaped trenches. Base region 14 is formed. The second base region 14 is not formed at a position in contact with the trench sidewall other than the corner, and the first base region 3 is formed. The impurity concentration of the second base region is set higher than the impurity concentration of the first base region 3.
The width of the second base region 14, that is, the distance from the trench sidewall is desirably equal to or greater than the width at which the channel is formed, and may be, for example, 0.1 μm to 0.5 μm.

Next, the operation of the trench gate MOSFET which is the semiconductor device of the present embodiment will be described.
In the trench gate type MOSFET, when a voltage is applied to the gate electrode 7, a channel in which current flows is formed in the base region 3 in contact with the gate insulating film 6. When a channel is formed, drain current starts to flow. In general, the gate voltage when a certain drain current flows is defined as a threshold voltage.

  FIG. 3 shows the drain current 28 with respect to the gate voltage of the trench gate type MOSFET of the present embodiment in comparison with the drain current 29 of the trench gate type MOSFET of the conventional structure. Here, the conventional trench gate type MOSFET means that the second base region 14 higher than the impurity concentration of the first base region 3 is not formed at the intersection of the trenches. Further, in FIG. 3, a broken line straight line is a drain current value 30 for determining the threshold voltage.

  As shown in FIG. 3, in the trench gate type MOSFET of the conventional structure, the electric field applied to the corner of the intersection of the trenches 5 formed in the lattice form of the trench gate type MOSFET is compared with a place other than the corner Because the area becomes larger, the vicinity of the corner is turned on earlier than the others, and a bump occurs in the drain current 29. The threshold voltage also depends on the impurity concentration of the first base region 3, and as the impurity concentration of the first base region 3 increases, the threshold voltage also increases.

Here, the relationship between the impurity concentration of Al implanted to form the second base region 14 and the width of the second base region 14 and the effect will be described.
The p-type (second conductivity type) impurity concentration of the second base region 14 is higher than the p-type (second conductivity type) impurity concentration of the first base region 3. In this case, when the trench MOSFET is turned on, the channel is formed with a certain width. If the width of the second base region 14 is too small, the threshold voltage can not be sufficiently increased and the channel in the corner is turned on first, so the second base region 14 is reversed by the channel. It needs to be more than the width. Furthermore, when the p-type (second conductivity type) impurity concentration of the second base region 14 is low, the threshold voltage is lower than the threshold voltage other than that at the corner, so that the impurity concentration does not turn on in the electric field applied to the corner It is necessary to do more than that.

The relationship between the p-type (second conductivity type) impurity concentration of the second base region 14 and the p-type (second conductivity type) impurity concentration of the first base region 3 is important. For example, the local Vth of the MOSFET in that portion may be different by 0.5 V or more from the p-type impurity concentration of the second base region 14 and the impurity concentration of the first base region 3. For that purpose, for example, the second conductivity type impurity concentration of the second base region 14 may be higher than the second conductivity type impurity concentration of the first base region 3 by 5 × 10 ¹⁶ cm ⁻³ or more. In this way, it is possible to prevent the channel from turning on earlier at the corner.

  In the trench gate type MOSFET according to the present embodiment, the concentration of the p-type (second conductivity type) impurity in the second base region 14 near the corner of the intersection of the trench 5 is higher than that in the first base region 3. doing. For this reason, the same gate voltage as that except for the corner is applied to the gate electrode 7 at the corner of the intersection of the trench 5, and the electric field applied to the gate insulating film 6 at the corner is larger than that other than the corner Even in this case, since the partial threshold voltage in the vicinity of the corner can be set high, it is possible to prevent the threshold voltage from being lowered without the corner being first turned on with respect to portions other than the corner. Therefore, as shown in FIG. 3, it is possible to obtain a trench gate type MOSFET having a drain current-gate voltage characteristic with a high threshold voltage without bumps.

  Subsequently, a method of manufacturing the trench gate type MOSFET according to the present embodiment will be sequentially described with reference to FIGS. 4 to 10 are schematic cross-sectional views of the MOSFET in each step for illustrating the method of manufacturing the trench gate type MOSFET according to the present embodiment. FIG. 11 is a plan view showing the shape of an ion implantation mask for forming the second base region 14 in the process of FIG. (A) and (b) of each figure of FIGS. 4-10 is sectional drawing corresponding to the AA cross section of FIG. 1, and a BB cross section, respectively.

First, as shown in FIG. 4, epitaxial layer 2 is formed on silicon carbide substrate 1. Here, an n-type (first conductivity type) low resistance silicon carbide substrate 1 having a polytype of 4H is prepared, and an n-type (first conductivity type) is formed thereon by a chemical vapor deposition (CVD) method. Type) silicon carbide epitaxial layer 2 was epitaxially grown. The n-type (first conductivity type) impurity concentration of the epitaxial layer 2 is 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , and the thickness is 5 to 50 μm.

  Subsequently, p-type (second conductivity type) first base region 3 and n-type (first conductivity type) source region 4 are formed by ion implanting a predetermined dopant on the surface of epitaxial layer 2 . Here, the first base region 3 of p-type (second conductivity type) is formed by ion implantation of aluminum (Al) which is a p-type (second conductivity type) impurity. The depth of the ion implantation of Al is about 0.5 to 3 μm within the range not exceeding the thickness of the epitaxial layer 2. The impurity concentration of Al to be implanted is made higher than the n-type (first conductivity type) impurity concentration of the epitaxial layer 2. At this time, the region of the epitaxial layer 2 deeper than the implantation depth of Al becomes the drift layer 2a. That is, the region in the epitaxial layer 2 in which the first base region 3 of the p-type (second conductivity type) is not formed is the drift layer 2a.

The n-type (first conductivity type) source region 4 is formed by ion implantation of nitrogen (N), which is an n-type (first conductivity type) impurity, on the surface of the first base region 3. The source region 4 is formed in a lattice-like pattern corresponding to the layout of the gate electrode 7 (trench 5) to be formed later as shown in FIG. Therefore, when the gate electrode 7 is formed, the source regions 4 are disposed on both sides of the gate electrode 7. The ion implantation depth of N is made shallower than the thickness of the first base region 3. The impurity concentration of N to be implanted is higher than the p-type (second conductivity type) impurity concentration of the first base region 3 and is in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 5, Al, which is a p-type (second conductivity type) impurity, is ion-implanted into the surface of the epitaxial layer 2 through the first implantation mask 16 to lower the source region 4. A second base region 14 of p type (second conductivity type) is formed. The second base region 14 is formed near the corner at the intersection of the trench to be formed later.
FIG. 11 is a top view for illustrating the method for manufacturing the trench MOSFET according to the present embodiment. In the present embodiment, as shown in FIG. 5, the second base region 14 is formed by performing ion implantation through the first implantation mask 16 opened near the corner.

  The second base region 14 is formed across the corner where the second base region 14 is to be formed, as shown in FIG. 5, corresponding to the layout of the trench 5 to be formed later. Are formed in a rectangular pattern according to the arrangement of Further, the width of the second base region 14 is formed concentrically outward from the trench sidewall at the corner portion forming the second base region 14 so as to have a width of 0.1 μm or more and 0.5 μm or less.

  Subsequently, as shown in FIG. 6, an etching mask 11 made of a silicon oxide film is deposited on the surface of the epitaxial layer 2 to a thickness of about 1 to 2 μm, and a resist mask 12 made of a resist material is formed thereon. The resist mask 12 is formed in a pattern in which the formation region of the trench 5 is opened by photolithography. Since the trenches 5 are in the form of a lattice, the resist mask 12 has a matrix-like pattern obtained by inverting it.

  Next, as shown in FIG. 7, the etching mask 11 is patterned by reactive ion etching (RIE) processing using the resist mask 12 as a mask. That is, the pattern of the resist mask 12 is transferred to the etching mask 11 made of a silicon oxide film. The patterned etching mask 11 serves as a mask in an etching process for forming the next trench 5.

  Subsequently, as shown in FIG. 8, a trench 5 penetrating the source region 4 and the first base region 3 is formed in the epitaxial layer 2 by RIE using the patterned etching mask 11 as a mask. A second base region 14 is formed in part of the first base region 3. The depth of the trench 5 is deeper than the portion where the second base region 14 is formed so as to reach the drift layer 2 a, and is about 0.5 to 3 μm.

  Next, after removing the resist mask 12 and the etching mask 11 shown in FIG. 8, annealing is performed to activate the ion-implanted N and Al in the above steps using a heat treatment apparatus. This annealing is performed under conditions of 1300 to 1900 ° C. and 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) gas.

  Subsequently, as shown in FIG. 9, after forming the gate insulating film 6 on the entire surface of the epitaxial layer 2 including the inside of the trench 5, low resistance polysilicon to be the gate electrode 7 is deposited by low pressure CVD. The gate insulating film 6 and the gate electrode 7 are formed inside the trench 5 by patterning or etching back. The silicon oxide film to be the gate insulating film 6 may be formed by thermally oxidizing the surface of the epitaxial layer 2 by a thermal oxidation method, or may be formed on the epitaxial layer 2 and inside the trench 5 by a deposition method .

  Next, as shown in FIG. 10, an interlayer insulating film 8 made of a silicon oxide film is formed on the entire surface of the epitaxial layer 2 by a low pressure CVD method, and the gate electrode 7 is covered. Next, the interlayer insulating film 8 is patterned to form contact holes 81 reaching the source region 4 and the first base region 3. In FIG. 10, a region surrounded by a dotted line corresponds to the contact hole 81.

  Then, an electrode material such as an Al alloy is deposited on the epitaxial layer 2 to form the source electrode 9 on the interlayer insulating film 8 and in the contact hole 81. Further, an electrode material such as an Al alloy is deposited on the lower surface of silicon carbide substrate 1 to form drain electrode 10, whereby a trench gate type MOSFET having the configuration shown in FIGS. 1 and 2 can be obtained.

  According to the semiconductor device of the present embodiment, since the impurity concentration of the second base region 14 near the corner is made higher than the impurity concentration of the first base region 3, a voltage is applied to the gate electrode 7. Even when the electric field applied to the gate insulating film 6 at the corners of the intersections of the trenches arranged in a grid pattern is larger than that at other places, the threshold voltage of the channel near the corners is the corner Since the threshold voltage of the channel other than the channel is higher than that of the channel other than the channel, it is possible to prevent the threshold voltage from being lowered without the corner being in the on state first.

  In the present embodiment, the trench type MOSFET having a structure in which epitaxial layer 2 and silicon carbide substrate 1 have the same first conductivity type has been described, but in the present invention, epitaxial layer 2 and silicon carbide substrate 1 The present invention is also applicable to a trench gate type IGBT having a structure having different conductivity types. For example, when the silicon carbide substrate 1 is p-type of the second conductivity type while the epitaxial layer 2 shown in FIG. 1 is n-type of the first conductivity type, a trench type IGBT is formed. In that case, the source region 4 and the source electrode 9 of the trench MOSFET correspond to the emitter region and the emitter electrode of the trench gate IGBT, respectively, and the drain electrode 10 corresponds to the collector electrode.

In the present embodiment, the semiconductor device made of a silicon carbide semiconductor has been described as an example, but the material of the semiconductor may be another material, and even if it is another wide band gap semiconductor device good.
Further, in the present embodiment, although the first conductivity type is n-type and the second conductivity type is p-type, the first conductivity type may be p-type and the second conductivity type may be n-type.

  Furthermore, in the present embodiment, an example of the active region having a square cell as viewed from the upper surface has been described, but the cell may have another structure, and the basic cell may be rectangular or hexagonal. good. Also, the arrangement of cells has been described using an example in which the cells are regularly arranged in the vertical and horizontal directions. However, the arrangement is such that the cells in adjacent columns are shifted, and the second base region is formed at the corner of the cells. Then, the same effect is achieved. Further, the boundary between the first base region 3 and the second base region may not be sharp, and the impurity concentration may change continuously over a certain width.

  In addition, in the manufacturing method, the first base region 3 may be formed by an epitaxial growth method. Also in this case, the impurity concentration and thickness of the first base region 3 may be equivalent to those formed by ion implantation.

Second Embodiment
The configuration of a trench gate type MOSFET which is a silicon carbide semiconductor device in a second embodiment of the present invention will be described. 12 and 13 are respectively a top view of a part of an active region of a trench gate type MOSFET which is a semiconductor device according to a second embodiment of the present invention, and a schematic sectional view of a part of the active region. An AA sectional view shown by an alternate long and short dash line in FIG. 12 corresponds to FIG. 13 (a), and a BB sectional view shown by an alternate long and two short dashes line in FIG. 1 corresponds to FIG. Here, the B-B cross-sectional view is a cross-sectional view including, in particular, corner portions of the intersections of the trenches arranged in a lattice.

  As shown in FIGS. 12 and 13, in the trench gate type MOSFET of the present embodiment, the second base region 14 described in the first embodiment is provided at the intersection of the trenches formed in a lattice shape, instead of being provided. Source region 4 is formed apart from the trench sidewall, and source region 4 is formed in contact with the trench sidewall at locations other than the intersection. The other points are the same as in the first embodiment, and thus detailed description will be omitted.

  As shown in FIGS. 12 and 13, in the trench gate type MOSFET of the present embodiment, source region 4 is formed apart from the trench sidewall at the intersection of the trenches, but the distance is 0.1 μm. It is good if it is above.

  According to the semiconductor device in the present embodiment, since source region 4 is formed at a position away from the corner, the channel length near the corner becomes long, the threshold voltage rises, and the channel resistance rises. Do. That is, it becomes difficult to turn on the channel near the corner. Therefore, even when the electric field applied to the gate insulating film 6 at the corner of the intersection of the trenches arranged in a lattice when the voltage is applied to the gate electrode 7 is larger than that at other places, Since the partial threshold voltage of the channel near the corner becomes high and the channel resistance becomes high, the influence of this part on the threshold voltage can be reduced and the threshold voltage of the entire device can be prevented from being lowered.

  The semiconductor device of the present embodiment can be manufactured by eliminating the step of manufacturing the second base region 14 in the first embodiment and forming the formation region of the source region 4 as shown in the present embodiment. The other points are the same as the method of manufacturing the semiconductor device of the first embodiment.

  According to the method for manufacturing a semiconductor device in the second embodiment of the present invention, the step of forming the second base region 14 in the first embodiment of the present invention is not necessary. Thus, it is possible to obtain a low cost semiconductor device with reduced manufacturing cost.

  1 silicon carbide substrate, 2 epitaxial layer, 2a drift layer, 3 first base region, 4 source region, 5 trench, 6 gate insulating film, 7 gate electrode, 8 interlayer insulating film, 9 source electrode, 10 drain electrode, 11 Etch mask, 12 resist mask, 14 second base region, 81 contact holes.

Claims (5)

A semiconductor substrate,
A drift layer of the first conductivity type provided on the semiconductor substrate;
A first base region of the second conductivity type located on the surface side of the drift layer;
A source region of a first conductivity type located in the first base region;
A trench formed in a lattice shape, having a trench sidewall consisting of a plurality of planes penetrating the first base region and the source region;
A gate insulating film formed in contact with the side wall of the trench in the trench;
A gate electrode embedded in the trench via the gate insulating film;
The second conductivity type, having an impurity concentration higher than the impurity concentration of the first base region formed at a location in contact with the trench sidewall other than the corner at a location in contact with a corner in the intersection of the trench And a second base area ,
The semiconductor device characterized in that the second base region is formed with a width of 0.1 μm to 0.5 μm from the trench sidewall . Said second conductivity type impurity concentration of the second base region, the semiconductor according to claim 1, wherein the high 5 × 10 ¹⁶ cm ^-3 or more than the second conductivity type impurity concentration of said first base region apparatus. The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon carbide semiconductor device, and the drift layer is made of silicon carbide. Growing an epitaxial layer of a first conductivity type to be a drift layer of a first conductivity type on a semiconductor substrate;
Forming a first base region of the second conductivity type in a surface layer portion of the epitaxial layer;
Forming a source region of a first conductivity type in a surface layer portion of the first base region;
Forming in the drift layer a second base region of a second conductivity type, the impurity concentration of which is higher than that of the first base region;
The trench penetrating the first base region and the source region is formed in a grid shape, and is deeper than the second base region such that a corner at the intersection of the trenches contacts the second base region, Forming by etching;
Forming a gate insulating film in contact with a trench sidewall in the trench;
Embedding a gate electrode in the trench via the gate insulating film;
Equipped with
The method of manufacturing a semiconductor device, wherein the second base region is formed with a width of 0.1 μm to 0.5 μm from the trench sidewall . The method for manufacturing a semiconductor device according to claim 4 , wherein the semiconductor substrate and the drift layer are made of silicon carbide.

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