CN111640786B - LIGBT device with multiple grooves - Google Patents
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- CN111640786B CN111640786B CN202010535106.7A CN202010535106A CN111640786B CN 111640786 B CN111640786 B CN 111640786B CN 202010535106 A CN202010535106 A CN 202010535106A CN 111640786 B CN111640786 B CN 111640786B
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- 210000000746 body region Anatomy 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 claims description 2
- 238000009826 distribution Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 238000009827 uniform distribution Methods 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Abstract
The invention relates to a LIGBT device with multiple grooves, and belongs to the technical field of power semiconductors. According to the LIGBT device with the multiple grooves, the shape of the body region of the second conduction type is changed through groove etching, doping with uniform distribution of the body region is achieved, the shape of a junction of the drift region of the first conduction type and the body region of the second conduction type can be improved, so that the electric field distribution of the contact region of the drift region and the body region is optimized, the reverse blocking voltage and overcurrent capacity of the device are improved, and the area of a chip can be reduced.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to an LIGBT device with multiple grooves.
Background
The Lateral Insulated Gate Transistor (LIGBT) is a composite power Semiconductor device composed of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and a Bipolar Junction Transistor (BJT), and combines the characteristics of high input impedance of the MOSFET and modulation of BJT conductance. The high-voltage power supply has the advantages of low conducting voltage, low driving power consumption, strong current capability, high voltage-resistant characteristic, good thermal stability, integration and the like, and is widely applied to intelligent power integrated circuits of automobile electronics, switching power supplies, panel displays, motor drives and the like. However, the LIGBT of the prior art, as shown in fig. 1, has a problem of uneven diffusion distribution of the second conductivity type body region, thereby reducing the over-current capability and breakdown voltage of the whole device.
Disclosure of Invention
The invention aims to solve the technical problem in the prior art and provides a LIGBT device with multiple grooves.
In order to solve the above technical problem, an embodiment of the present invention provides a LIGBT device with multiple trenches, including a second conductive type substrate, a first conductive type drift region, a second conductive type body region, a highly doped second conductive type body contact region, a first conductive type emitter region, a second conductive type collector region, a dielectric layer, an emitter, a planar gate structure, and a collector;
the first conductive type drift region is located on the second conductive type substrate; the second conductive type body region is located in the first conductive type drift region and on the second conductive type substrate; the top layer of the second conduction type body region, which is in mutual contact with the side surface of the first conduction type emitter region, is positioned on one side, far away from the first conduction type drift region, of the highly doped second conduction type body contact region; the second conduction type collector region is positioned on one side, far away from the second conduction type body region, of the top layer of the first conduction type drift region;
the emitter electrode is located on the highly doped second conductivity type body contact region and a first portion of the first conductivity type emitter region; the planar gate structure is positioned on the second part of the first conductive type emitter region, the second conductive type body region and part of the first conductive type drift region; the collector electrode is positioned on the second conduction type collector region;
the dielectric layer is positioned on the first conduction type drift region between the emitter, the planar gate structure and the collector;
the high-doping second conductive type body contact area is arranged in the second conductive type body area, the first conductive type emitter area is arranged in the second conductive type body area, and the second conductive type body area is formed by the second conductive type polysilicon groove area in a diffused mode.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the planar gate structure comprises the gate oxide layer and a polysilicon gate electrode positioned on the gate oxide layer.
Further, the dielectric layer is silicon dioxide.
Furthermore, in the preparation process, the transverse width, the longitudinal length, the interval or the number of the grooves of the second conductive type polycrystalline silicon groove regions are adjusted by changing a photolithography mask.
Further, the first conductive type is an N type, and the second conductive type is a P type.
Further, the first conductive type is a P type, and the second conductive type is an N type.
The invention has the beneficial effects that: according to the LIGBT device with the multiple grooves, the groove process is adopted to manufacture the body region of the second conduction type, so that the doping concentration distribution of the body region is approximately uniformly distributed, more electric field lines passing through the drift region can be terminated in the body region of the second conduction type, the shape of a junction of the drift region of the first conduction type and the body region of the second conduction type in a contact mode can be improved, the electric field distribution of the contact region of the drift region and the body region is optimized, the overcurrent capacity and breakdown voltage of the whole device are increased, and the chip area can be reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional LIGBT;
fig. 2 is a schematic diagram of a first structure of a LIGBT device with multiple trenches, according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a second structure of a LIGBT device with multiple trenches according to an embodiment of the present invention.
In the drawings, the components represented by the respective reference numerals are listed below:
201. a second conductive type substrate, 202, a first conductive type drift region, 203, a second conductive type body region, 204, a highly doped second conductive type body contact region, 205, a first conductive type emitter region, 206, a second conductive type collector region, 207, a gate oxide layer, 208, a dielectric layer, 209, an emitter, 210, a polysilicon gate electrode, 211, a collector, 212, a second conductive type polysilicon trench region, 301-1 to 301-N are the lateral width of each trench of the plurality of second conductive type polysilicon trench regions, 403-1 to 403-N-1 are the spacing between adjacent trenches in the plurality of second conductive type polysilicon trench regions, wherein N is a positive integer.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 2, a LIGBT device with multiple trenches according to a first embodiment of the present invention includes a second conductive type substrate 201, a first conductive type drift region 202, a second conductive type body region 203, a highly doped second conductive type body contact region 204, a first conductive type emitter region 205, a second conductive type collector region 206, a dielectric layer 208, an emitter 209, a planar gate structure and a collector 211;
the first conductive-type drift region 202 is located on the second conductive-type substrate 201; the second conductive-type body region 203 is located in the first conductive-type drift region 202 and on the second conductive-type substrate 201; the top layer of the second conductive type body region 203, where the side surfaces of the highly doped second conductive type body contact region 204 and the first conductive type emitter region 205 are in contact with each other, is located on the side away from the first conductive type drift region 202; the second-conductivity-type collector region 206 is located on a side of the top layer of the first-conductivity-type drift region 202 away from the second-conductivity-type body region 203;
the emitter electrode 209 is located on a first portion of the highly doped second conductivity type body contact region 204 and first conductivity type emitter region 205; the planar gate structure is located on a second portion of the first conductive type emitter region 205, the second conductive type body region 203, and a portion of the first conductive type drift region 202; the collector electrode 211 is located on the second conductive-type collector region 206;
the dielectric layer 208 is positioned on the first conductive type drift region 202 between the emitter 209, the planar gate structure and the collector 211;
the semiconductor device further comprises a second conductive type polysilicon trench region 212, a plurality of second conductive type polysilicon trench regions 212 are arranged in the second conductive type body region 203 at intervals and are arranged below the highly doped second conductive type body contact region 204 and the first conductive type emitter region 205, and the second conductive type body region 203 is formed by diffusing the second conductive type polysilicon trench regions 212.
In the above embodiments, the first conductive type may be an N type, and the second conductive type may be a P type. The second conductive type polysilicon trench region 212 is formed by etching a trench, and the trench is filled with second conductive type polysilicon, preferably, the longitudinal lengths of the plurality of second conductive type polysilicon trench regions 212 are the same, and the distances between adjacent trenches in the plurality of second conductive type polysilicon trench regions 212 are the same;
the second conductive-type body region 203 is preferably formed by high temperature annealing diffusion of a second conductive-type polysilicon trench region 212.
Taking an N-type LIGBT as an example, the working principle of the invention is explained as follows:
according to the LIGBT device with the multiple trenches, provided by the invention, the multiple trenches are formed in the N-type drift region 202 through etching, the P-type polycrystalline silicon is filled in the trenches to form the P-type polycrystalline silicon trench region 212, and then the P-type body region 203 is formed through high-temperature annealing and diffusion, so that more electric field lines passing through the drift region can be terminated in the P-type body region 203, and the overall overcurrent capacity of the device is improved.
When the forward bias voltage applied to the polysilicon gate electrode 210 exceeds the threshold voltage, the surface of the P-type body region 203 below the polysilicon gate electrode 210 is inverted and forms a channel, electrons in the N-type emitter region 205 enter the N-type drift region 202 through the channel, and the NMOS portion in the LIGBT is turned on; meanwhile, when a sufficient forward voltage is applied to the collector 211, a PN junction formed by the P-type collector region 206 and the N-type drift region 202 is turned on, so that a large number of holes are injected into the N-type drift region 202 by the P-type collector region 206, and the LIGBT structure is turned on.
The electrode connection mode when the reverse blocking is carried out is as follows: the polysilicon gate electrode 210 is shorted to the emitter 209 and the emitter 209 is forward biased. When the device is reverse voltage-resistant, the doping effect of uniform distribution is formed by annealing the deposited P-type polycrystalline silicon in the P-type polycrystalline silicon groove region 212, so that the appearance of junctions at two sides of the P-type body region 203 and the N-type drift region 202 is improved, the reverse breakdown voltage is improved, the whole area of the device can be reduced, the leakage of a substrate is reduced, and the on-resistance of the whole device is improved.
Optionally, as shown in fig. 2, the planar gate structure includes the gate oxide layer 207 and a polysilicon gate electrode 210 thereon.
Optionally, the dielectric layer 208 is silicon dioxide.
Alternatively, as shown in fig. 3, during the preparation process, the lateral width, the longitudinal length, the pitch, or the number of trenches of the second conductivity type polysilicon trench regions 212 may be adjusted by changing photolithography.
In the above embodiments, a person skilled in the art can adjust the lateral width, the longitudinal length, the pitch, or the number of trenches of the plurality of second conductivity type polysilicon trench regions 212 according to actual needs.
Optionally, the first conductivity type is an N-type, and the second conductivity type is a P-type.
Optionally, the first conductivity type is a P type, and the second conductivity type is an N type.
According to the LIGBT device with the multiple grooves, the shape of the body region of the second conduction type is changed through groove etching, doping with uniform distribution of the body region is achieved, the shape of a junction of the drift region of the first conduction type and the body region of the second conduction type can be improved, so that the electric field distribution of the contact region of the drift region and the body region is optimized, the reverse blocking voltage and overcurrent capacity of the device are improved, and the area of a chip can be reduced.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. An LIGBT device with multiple grooves comprises a second conduction type substrate (201), a first conduction type drift region (202), a second conduction type body region (203), a highly-doped second conduction type body contact region (204), a first conduction type emitter region (205), a second conduction type collector region (206), a dielectric layer (208), an emitter electrode (209), a planar gate structure and a collector electrode (211);
the first conductivity type drift region (202) is located on the second conductivity type substrate (201); the second conductivity type body region (203) is located in the first conductivity type drift region (202) and on the second conductivity type substrate (201); the top layer of the second conduction type body region (203), which is in mutual contact with the side surface of the first conduction type emitter region (205), is positioned on one side, away from the first conduction type drift region (202), of the highly doped second conduction type body contact region (204); the second-conductivity-type collector region (206) is located on a side of the top layer of the first-conductivity-type drift region (202) away from the second-conductivity-type body region (203);
the emitter (209) is located on a first portion of the highly doped second conductivity type body contact region (204) and first conductivity type emitter region (205); the planar gate structure is located on a second portion of the first conductivity type emitter region (205), the second conductivity type body region (203), and a portion of the first conductivity type drift region (202); the collector electrode (211) is located on the second conductive type collector region (206);
the dielectric layer (208) is positioned on the first conduction type drift region (202) between the emitter (209), the planar gate structure and the collector (211);
the high-doping-type-second-conductivity-type-first-conductivity-type-second-conductivity-type-first-conductivity-type region (203) is arranged in the second-conductivity-type body region (203) at intervals, and the second-conductivity-type-first-conductivity-type-second-conductivity-type-region (212) is formed in a diffused mode.
2. The LIGBT device with multiple trenches of claim 1, wherein the planar gate structure comprises a gate oxide layer (207) and a polysilicon gate electrode (210) thereon.
3. The LIGBT device with multiple trenches of claim 1, wherein the dielectric layer (208) is silicon dioxide.
4. The LIGBT device with multiple trenches as claimed in any one of claims 1 to 3, wherein a lateral width, a longitudinal length, a pitch, or a number of trenches of the second conductivity type polysilicon trench region (212) is adjusted by changing a photolithography during a fabrication process.
5. The LIGBT device with multiple trenches of any one of claims 1-3, wherein the first conductivity type is N-type and the second conductivity type is P-type.
6. The LIGBT device with multiple trenches of any one of claims 1-3, wherein the first conductivity type is P-type and the second conductivity type is N-type.
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| CN202010535106.7A CN111640786B (en) | 2020-06-12 | 2020-06-12 | LIGBT device with multiple grooves |
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| CN202010535106.7A CN111640786B (en) | 2020-06-12 | 2020-06-12 | LIGBT device with multiple grooves |
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| CN111640786B true CN111640786B (en) | 2021-11-23 |
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| US7772100B2 (en) * | 2005-03-24 | 2010-08-10 | Nxp B.V. | Method of manufacturing a semiconductor device having a buried doped region |
| CN102034707B (en) * | 2009-09-29 | 2014-01-01 | 比亚迪股份有限公司 | Method for manufacturing IGBT |
| CN102130165B (en) * | 2010-01-18 | 2013-03-13 | 上海华虹Nec电子有限公司 | Source region of LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN103208530B (en) * | 2013-03-11 | 2016-04-27 | 江苏应能微电子有限公司 | Low electric capacity ultra-deep groove transient voltage suppressor structure |
| CN103219386B (en) * | 2013-04-22 | 2016-01-20 | 南京邮电大学 | A kind of lateral power with high K insulation layer |
| CN103295898A (en) * | 2013-05-10 | 2013-09-11 | 江苏应能微电子有限公司 | Method for manufacturing transient voltage suppressor by aid of ultra-deep trench structures |
| CN104617157A (en) * | 2015-01-23 | 2015-05-13 | 应能微电子（上海）有限公司 | Transient voltage suppressor structure with ultra-deep grooves |
| CN106549052B (en) * | 2015-09-17 | 2021-05-25 | 联华电子股份有限公司 | Lateral diffusion metal oxide semiconductor transistor and manufacturing method thereof |
| US9461046B1 (en) * | 2015-12-18 | 2016-10-04 | Texas Instruments Incorporated | LDMOS device with graded body doping |
| CN107546274B (en) * | 2017-08-22 | 2020-01-17 | 电子科技大学 | LDMOS device with step-shaped groove |
| CN109166922B (en) * | 2018-08-28 | 2020-12-18 | 电子科技大学 | Groove type super-junction power terminal structure and preparation method thereof |
| CN109300977A (en) * | 2018-10-08 | 2019-02-01 | 深圳市南硕明泰科技有限公司 | A kind of transistor and preparation method thereof |
| CN111223919A (en) * | 2020-03-27 | 2020-06-02 | 上海维安半导体有限公司 | TVS (transient voltage suppressor) etched by deep groove and filled with high-concentration polycrystalline silicon and manufacturing method thereof |
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