WO2022205556A1 - Insulated gate bipolar transistor device and manufacturing method therefor - Google Patents

Insulated gate bipolar transistor device and manufacturing method therefor Download PDF

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WO2022205556A1
WO2022205556A1 PCT/CN2021/091898 CN2021091898W WO2022205556A1 WO 2022205556 A1 WO2022205556 A1 WO 2022205556A1 CN 2021091898 W CN2021091898 W CN 2021091898W WO 2022205556 A1 WO2022205556 A1 WO 2022205556A1
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width
conductivity type
trenches
present disclosure
bipolar transistor
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PCT/CN2021/091898
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French (fr)
Chinese (zh)
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安俊杰
何志
奥尔甘蒂尼·保罗
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无锡锡产微芯半导体有限公司
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, the present disclosure relates to trench-type insulated gate bipolar transistor devices and methods of fabricating the same.
  • An insulated gate bipolar transistor is a voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and a metal oxide semiconductor field effect transistor (MOSFET).
  • BJT bipolar transistor
  • MOSFET metal oxide semiconductor field effect transistor
  • the main purpose of research on IGBT is to improve the power density and switching speed of IGBT and reduce the power consumption of IGBT.
  • a trench-type IGBT device is proposed in the prior art, which converts the current channel direction in the IGBT from the lateral direction of the device surface to the vertical direction in the device body by adjusting the gate from the horizontal direction to the vertical direction direction, enabling the elimination of the junction field effect transistor (JFET) effect in the IGBT while increasing the channel density and near-surface carrier concentration, which in turn can greatly reduce collector-emitter without increasing turn-off losses (Source) turn-on voltage (Vceon).
  • JFET junction field effect transistor
  • the purpose of the present disclosure is to provide a trench-type insulated gate bipolar transistor (IGBT) device and a manufacturing method thereof that can overcome the above-mentioned problems in the prior art.
  • IGBT insulated gate bipolar transistor
  • an insulated gate bipolar transistor device comprising: a substrate of a first conductivity type; and a plurality of trenches formed downwardly from an upper surface of the substrate to have along a first conductivity type Strip shapes extending in one direction parallel to each other and having a plurality of gate electrodes disposed therein, respectively, wherein an active region is formed between the trenches, and the active region has a source electrode of a first conductivity type extending in a first direction region and a contact region of the second conductivity type, wherein the contact region has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the second width along the The one direction is alternately arranged, and the gate electrode has a uniform third width in the second direction.
  • an insulated gate bipolar transistor device comprising: a substrate of a first conductivity type; and a plurality of trenches formed downwardly from an upper surface of the substrate to have along strip shapes extending in a first direction parallel to each other and having a plurality of gate electrodes disposed therein, respectively, wherein an active region is formed between the trenches, and the active region has a source of a first conductivity type extending in the first direction A pole region and a contact region of the second conductivity type, wherein the gate has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the second width being along the The first directions are alternately arranged, and the contact areas have a uniform third width in the second direction.
  • a method of fabricating an insulated gate bipolar transistor device comprising: forming a plurality of trenches downward from an upper surface of a substrate of a first conductivity type such that the plurality of trenches The grooves have strip shapes extending in parallel with each other in a first direction; a plurality of gate electrodes are respectively provided in the plurality of trenches; and a first A source region of a conductivity type and a contact region of a second conductivity type such that the contact region has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the first width The two widths are alternately arranged along the first direction.
  • the trench-type IGBT device according to the present disclosure does not require complicated layout design and can be fabricated with simplified conventional semiconductor process steps, so that the manufacturing cost can be reduced. Meanwhile, the trench IGBT device according to the present disclosure can reduce saturation current, thereby improving short-circuit performance.
  • FIG. 1A shows a plan view of a trench IGBT device according to a first embodiment of the present disclosure
  • FIG. 1B shows a perspective view of a trench IGBT device according to the first embodiment of the present disclosure
  • FIG. 2 shows a cross-sectional perspective view of the trench IGBT device according to the first embodiment of the present disclosure, taken along line AA' of FIG. 1A;
  • FIG. 3 shows a cross-sectional perspective view of the trench IGBT device according to the first embodiment of the present disclosure, taken along line BB' of FIG. 1A ;
  • FIG. 4 shows an I-V characteristic curve of the trench IGBT device according to the first embodiment of the present disclosure
  • FIG. 5 shows a graph of saturation current of the trench IGBT device according to the first embodiment of the present disclosure
  • FIG. 6 shows a plan view of a trench IGBT device according to a second embodiment of the present disclosure
  • FIG. 7 illustrates a cross-sectional perspective view of a trench IGBT device according to a second embodiment of the present disclosure, taken along line CC' of FIG. 6;
  • FIG. 8 illustrates a cross-sectional perspective view of a trench IGBT device according to a second embodiment of the present disclosure, taken along line DD' of FIG. 6 .
  • first and second are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from another. For example, a first element referred to as a first element in one embodiment could be referred to as a second element in other embodiments without departing from the scope of the appended claims.
  • “About” or “approximately” as used herein includes the stated value as well as the The average value within an acceptable deviation range determined with respect to a particular value. For example, “about” can mean an average within one or more standard deviations, or an average within ⁇ 30%, 20%, 10%, 5% of the stated value.
  • Embodiments are described herein with reference to cross-sectional perspective illustrations that are schematic illustrations of idealized embodiments. Thus, shape variations from the illustrations are contemplated as a result of, for example, manufacturing techniques and/or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of regions as illustrated herein, but are to include deviations from shapes due, for example, to manufacturing. For example, regions shown or described as flat may typically have rough and/or nonlinear features. Also, the acute angles shown can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.
  • FIG. 1A shows a plan view of a trench IGBT device 10 according to a first embodiment of the present disclosure.
  • FIG. 1B shows a perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure.
  • 2 shows a cross-sectional perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure, taken along line AA' of FIG. 1A .
  • FIG. 3 shows a cross-sectional perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure, taken along line BB′ of FIG. 1A .
  • the trench IGBT device 10 may include a substrate 3 of a first conductivity type and a plurality of trenches 4 .
  • a plurality of trenches 4 are formed downward from the upper surface of the substrate to have strip shapes extending in the first direction DR1 parallel to each other and a plurality of gate electrodes G are respectively disposed therein.
  • Active regions are formed between the plurality of trenches 4 and have source regions 7 of the first conductivity type and contact regions 8 of the second conductivity type extending in the first direction DR1.
  • the contact region 8 has a first width WC1 in a second direction DR2 perpendicular to the first direction DR1 and a second width WC2 different from the first width WC1, the first width WC1 and the second width WC2 alternating along the first direction DR1 layout.
  • Each of the plurality of gates G has a uniform third width WG3 in the second direction DR2.
  • first conductivity type As N-type and the second conductivity type as P-type as an example, the present disclosure is not limited thereto. In other embodiments of the present disclosure, the first conductivity type may also be P-type and the second conductivity type may be N-type.
  • the term “heavy doped region” herein generally refers to a region with a doping concentration greater than or equal to 10 18 cm -3 and is represented by the symbol “+”.
  • the term “lightly doped region” herein refers to a region with a doping concentration of less than 10 18 cm -3 , and is represented by the symbol “-”.
  • “n+” indicates an n-type region with a doping concentration greater than or equal to 10 18 cm -3
  • “n-" indicates an n-type region with a doping concentration less than 10 18 cm -3
  • the trench IGBT device 10 includes first cells 10A and second cells 10B alternately arranged along the first direction DR1 .
  • the gate G in the first cell 10A and the gate G in the second cell 10B have a uniform third width WG3 in the second direction DR2.
  • the first width WC1 of the p+ contact region in the first cell 10A in the second direction DR2 may be smaller than the p+ contact region in the second cell 10B The second width WC2 of the contact region in the second direction DR2.
  • FIG. 2 shows a cross-sectional perspective view of the first cell 10A of the trench IGBT device 10
  • FIG. 3 shows a cross-sectional perspective view of the second cell 10B of the trench IGBT device 10 picture.
  • the trench-type IGBT device 10 has vertical trenches 4 arranged in the first direction DR1 and the gate G is arranged in the trenches 4 .
  • the trench 4 may be formed using an etching process.
  • an oxide layer eg, a silicon oxide layer
  • an oxide layer may be formed on the inner surface of the trench 4 as a dielectric layer using, but not limited to, a thermal oxidation process, a physical vapor deposition process, or a chemical vapor deposition process.
  • a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be employed to form the gate G in the trench 4, and the gate G may include, but is not limited to, doped polysilicon.
  • the vertical gate G is used to change the channel from the lateral direction to the vertical direction, the cell size can be reduced to increase the cell density, This makes it possible to increase the overall channel width of the IGBT device and reduce the channel resistance.
  • the area of the polysilicon gate in the trench gate is increased, so that the distributed resistance can be reduced, which is beneficial to improve the switching speed.
  • the trench IGBT device 10 forms an active region between the trenches 4 , and the active region may include a p+ type collector layer 1 , n+ type buffer layer 2 , n- type semiconductor substrate 3 , p- type channel layer 5 , n- type carrier blocking layer 6 , n+ type source (emitter) region 7 and p+ type contact region 8 .
  • the trench type IGBT device 10 may further include a collector metal layer disposed on the p+ type collector layer 1 and connected to the p+ type collector layer 1 electrical contact. Furthermore, the trench IGBT device 10 may further include a source metal layer disposed on and in electrical contact with the n+ type source region 7 and the p+ type contact region 8 . Furthermore, the trench IGBT device 10 may also include a gate electrode, which may be in electrical contact with the vertical gate in the trench 4 in a through-hole manner.
  • the p+ type collector layer 1 may function as a hole injection layer, which forms a forward biased PN junction with the n+ type buffer layer 2 to increase the hole injection effect.
  • the n+ type buffer layer 2 may function as an electric field stop layer for generating electrons that recombine with holes injected from the p+ type collector layer 1 when the IGBT is turned off, thereby improving the turn-off speed.
  • the n-type semiconductor substrate 3 may be a substrate having a high resistivity.
  • the n-type semiconductor substrate 3 may be an FZ wafer or an MCZ wafer.
  • the n-type semiconductor substrate 3 may also include, but is not limited to, a silicon substrate, a silicon carbide, a gallium nitride substrate, or a silicon germanium substrate.
  • the p-type channel layer 5 , the n-type carrier blocking layer 6 and the n+ type source region 7 may be formed between the trenches 4 so as to be in contact with the sidewalls of the trenches 4 .
  • the p-type channel layer 5 is formed on the n-type carrier blocking layer 6
  • the n+ type source region 7 is formed on the p-type channel layer 5 .
  • the depth of the n-type carrier blocking layer 6 in the vertical direction is smaller than the depth of the vertical trench 4 .
  • the lower surface of the n-type carrier blocking layer 6 may be higher than the lower surface of the trench 4 in the vertical direction.
  • the basic structure of the p+ type contact region 8 is formed by ion implantation after etching the trench.
  • the formation of the p+ contact region 8 does not require an additional mask, and the deep trench p+ contact region 8 can effectively improve the latch-up resistance of the trench IGBT device .
  • the p+ type contact region 8 may also be formed in the n+ type source region 7 by, for example, an ion implantation process.
  • the implantation depth of the p+-type contact region 8 can be controlled by the ion implantation energy, in other words, the larger the implantation depth of the p+-type contact region 8, the larger the required ion implantation energy.
  • the implantation depth of the p+-type contact region 8 should not exceed the depth of the p-type channel layer 5 .
  • the depth of the p+ type contact region 8 in the vertical direction may be greater than that of the n+ type source region 7 .
  • the lower surface of the p+ type contact region 8 may be lower than the lower surface of the n+ type source region 7 , but not lower than the lower surface of the p ⁇ type channel layer 5 .
  • the IGBT structure formed according to the above-described embodiment of the present disclosure may be referred to as a carrier storage trench IGBT, in which the n-type carrier blocking layer 6 formed under the p-type channel layer 5 may be used for storage carrier.
  • the hole density decreases as the distance from the source (emitter) decreases.
  • a high hole density can be maintained even on the source side, which can reduce the on-voltage (ie, Vceon) without increasing the turn-off loss.
  • the IGBT structure formed according to the above-described embodiment of the present disclosure due to the layout arrangement of the n+ type source region 7 and the p+ type contact region 8, it is also possible to greatly eliminate the formation of the n+ type source region 7, p-type The latch-up effect of the parasitic NPNP thyristor formed by the channel layer 5 , the n- type semiconductor substrate 3 and the p+ type collector layer 1 .
  • the first cells 10A and the second cells 10B having different widths of the p+ type contact regions 8 are alternately arranged along the first direction DR1 .
  • Trench-type IGBT devices are formed in the first cell 10A and the second cell 10B, respectively.
  • the second width WC2 of the P+ contact region 8 in the second cell 10B may be greater than the first width WC1 of the P+ contact region 8 in the first cell 10A. That is, in the second cell 10B, the distance between the p+ type contact region 8 formed by the ion implantation process and the sidewall of the trench 4 is in the range of about 0.1 ⁇ m to about 0.5 ⁇ m, so that the second cell 10B The channel doping concentration of the IGBT device in the cell 10B is greater than 10 18 cm -3 , so the IGBT device in the second cell 10B is normally off. In contrast, in the first cell 10A, the distance between the p+ type contact region 8 and the sidewall of the trench 4 is greater than about 1.0 ⁇ m, so that the trench IGBT device in the first cell 10A can operate normally.
  • the trench IGBT device according to the first embodiment of the present disclosure has a cell arrangement of normal IGBT devices and normally-off IGBT devices that are alternately arranged in parallel with each other. Therefore, the trench IGBT device according to the first embodiment of the present disclosure can maintain a small saturation current without sacrificing I-V characteristics.
  • the IGBT devices in the second cell 10B are normally off, the gates in the IGBT devices in the second cell 10B can be regarded as dummy gates, so that the gate charge (Qg) can also be reduced.
  • the I-V characteristics of the trench IGBT device can be adjusted.
  • FIG. 4 shows an I-V characteristic curve of the trench IGBT device according to the first embodiment of the present disclosure.
  • FIG. 5 shows a graph of saturation current of the trench IGBT device according to the first embodiment of the present disclosure.
  • the I-V characteristics of the trench IGBT device can be adjusted.
  • the lengths of the first cell 10A and the second cell 10B along the first direction DR1 may be the same. According to the first embodiment of the present disclosure, the lengths of the first cell 10A and the second cell 10B along the first direction DR1 may be different. When the lengths of the first cell 10A and the second cell 10B along the first direction DR1 are different, by adjusting the proportional relationship between the lengths of the first cell 10A and the second cell 10B along the first direction DR1, The I-V characteristics of the trench IGBT device can also be adjusted.
  • the method for manufacturing the trench-type IGBT device 10 according to the first embodiment of the present disclosure may include the step of forming a plurality of trenches 4 downward from the upper surface of the substrate 3 of the first conductivity type such that a plurality of trenches 4 are formed.
  • the trenches 4 have stripe shapes that are parallel to each other extending in the first direction DR1; a plurality of gates G are respectively provided in the plurality of trenches 4; and the active regions formed between the trenches 4 using the same mask
  • the source region 7 of the first conductivity type and the contact region 8 of the second conductivity type are formed in each such that the contact region 8 has a first width WC1 in a second direction DR2 perpendicular to the first direction DR1 and a A second width WC2 of a width WC1, the first width WC1 and the second width WC2 are alternately arranged along the first direction DR1.
  • a trench-type IGBT device can be fabricated on an n-type semiconductor substrate 3 as an FZ wafer or an MCZ wafer.
  • a plurality of trenches 4 extending in the first direction DR1 are formed on the upper surface of the n-type semiconductor substrate 3 by, for example, an etching process.
  • a plurality of gates G having a uniform third width WG3 along the second direction DR2 are formed in the plurality of trenches 4 by, for example, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process .
  • an n-type carrier blocking layer 6, a p-type channel layer 5, and an n+-type source electrode are sequentially formed by high-energy ion implantation on the upper surface of the n-type semiconductor substrate 3 between the plurality of trenches 4
  • an n+-type buffer layer 2 is formed by high-energy ion implantation and a p+-type collector layer 1 is formed by low-energy ion implantation in sequence to complete the trench IGBT device, wherein the n+-type buffer layer is It can be implanted in a variety of ion forms, such as protons, phosphorus, etc.
  • the number of cells in the trench IGBT device according to the first embodiment of the present disclosure can be adjusted according to application scenarios and application scopes.
  • FIG. 6 shows a plan view of a trench IGBT device 20 according to a second embodiment of the present disclosure.
  • FIG. 7 shows a cross-sectional perspective view of the trench IGBT device 20 according to the second embodiment of the present disclosure, taken along line CC′ of FIG. 6 .
  • FIG. 8 shows a cross-sectional perspective view of the trench IGBT device 20 according to the second embodiment of the present disclosure, taken along the line DD′ of FIG. 6 .
  • the trench IGBT device 20 may include a substrate 3 of a first conductivity type and a plurality of trenches 4 .
  • a plurality of trenches 4 are formed downward from the upper surface of the substrate to have strip shapes extending in the first direction DR1 parallel to each other and a plurality of gate electrodes G are respectively disposed therein.
  • Active regions are formed between the plurality of trenches 4 and have source regions 7 of the first conductivity type and contact regions 8 of the second conductivity type extending in the first direction DR1.
  • Each of the plurality of gates G has a first width WG1 in a second direction DR2 perpendicular to the first direction DR1 and a second width WG2 different from the first width along the The first directions DR1 are alternately arranged.
  • the contact region 8 has a uniform third width WC3 in the second direction DR2.
  • first conductivity type is N-type and the second conductivity type is P-type as an example to describe the second embodiment of the present disclosure
  • present disclosure is not limited thereto.
  • first conductivity type may also be P-type and the second conductivity type may be N-type.
  • the trench IGBT device 20 includes first cells 20A and second cells 20B alternately arranged along the first direction DR1 .
  • the p+ contact region in the first cell 20A and the p+ contact region in the second cell 10B have a uniform third width WC3 in the second direction DR2.
  • the first width WG1 of the gate G in the first cell 20A in the second direction DR2 may be smaller than that of the gate G in the second cell 10B The second width WG2 of the pole G in the second direction DR2.
  • the gate G has a first width WG1 and a second width WG2 alternately arranged along the first direction DR1, and the p+ contact region has a uniform third width along the first direction DR1
  • the second embodiment of the present disclosure is basically the same as the first embodiment of the present disclosure, so details of the structure of the trench IGBT device 20 according to the second embodiment of the present disclosure are not made here. further detailed description.
  • the first cells 20A and the second cells 20B having different widths of the gate G are alternately arranged along the first direction DR1.
  • Trench-type IGBT devices are formed in the first cell 20A and the second cell 20B, respectively.
  • the second width WG2 of the gate G in the second cell 20B may be greater than the first width WC1 of the gate G in the first cell 20A. That is, in the second cell 20B, the distance between the p+ type contact region 8 formed by the ion implantation process and the sidewall of the trench 4 is in the range of about 0.1 ⁇ m to about 0.5 ⁇ m, so that the second cell 20B The channel doping concentration of the IGBT device in the cell 20B is greater than 10 18 cm -3 , so the IGBT device in the second cell 20B is normally off. In contrast, in the first cell 20A, the distance between the p+ type contact region 8 and the sidewall of the trench 4 is greater than about 1.0 ⁇ m, so that the trench IGBT device in the first cell 20A can operate normally.
  • the trench IGBT device according to the second embodiment of the present disclosure has a cell arrangement of normal IGBT devices and normally-off IGBT devices which are alternately arranged in parallel with each other. Therefore, the trench IGBT device according to the second embodiment of the present disclosure can maintain a small saturation current without sacrificing I-V characteristics.
  • the IGBT devices in the second cell 20B are normally off, the gates in the IGBT devices in the second cell 20B can be regarded as dummy gates, thereby also reducing the gate charge (Qg).
  • the I-V characteristics of the trench IGBT device can be adjusted.
  • the lengths of the first cell 20A and the second cell 20B along the first direction DR1 may be the same. According to the second embodiment of the present disclosure, the lengths of the first cell 20A and the second cell 20B along the first direction DR1 may be different. When the lengths of the first cell 20A and the second cell 20B along the first direction DR1 are different, by adjusting the proportional relationship between the lengths of the first cell 20A and the second cell 20B along the first direction DR1, The I-V characteristics of the trench IGBT device can also be adjusted.
  • the method for fabricating the trench IGBT device 20 according to the second embodiment of the present disclosure is substantially the same as the method for fabricating the trench IGBT device 10 according to the first embodiment of the present disclosure, except for the difference
  • the fact is that the etching mask used to form the trench 4 needs to be adjusted according to the shape change of the gate G, but this does not add additional process steps.
  • the trench-type IGBT device according to the present disclosure does not require complicated layout design and can be fabricated with simplified conventional semiconductor process steps, so that the manufacturing cost can be reduced. Meanwhile, the trench IGBT device according to the present disclosure can reduce saturation current, thereby improving short-circuit performance. In addition, by adjusting the relevant parameters in the trench IGBT device, the I-V characteristics of the trench IGBT device can be easily adjusted.

Abstract

The content of the present disclosure relates to an insulated gate bipolar transistor (IGBT) device and a manufacturing method therefor. According to the content of the present disclosure, the IGBT device comprises: a substrate, which is a first conductivity type; and a plurality of trenches, which are formed downward from an upper surface of the substrate to have strip shapes in parallel with one another extending in a first direction, each strip shape having a plurality of gates arranged therein. An active region is formed between the trenches, and has a source region of a first conductivity type and a contact region of a second conductivity type, which extend in the first direction, wherein the contact region has a first width in a second direction perpendicular to the first direction and has a second width different from the first width; the first width and the second width are alternately arranged in the first direction; and the trenches have a uniform third width in the second direction.

Description

绝缘栅双极型晶体管装置及其制备方法Insulated gate bipolar transistor device and method of making the same 技术领域technical field
本公开内容涉及半导体的技术领域，特别地，本公开内容涉及沟槽型绝缘栅双极型晶体管装置及其制备方法。The present disclosure relates to the technical field of semiconductors, and in particular, the present disclosure relates to trench-type insulated gate bipolar transistor devices and methods of fabricating the same.
背景技术Background technique
绝缘栅双极型晶体管(IGBT)是由双极型三极管(BJT)和金属氧化物半导体场效应管(MOSFET)组成的电压驱动型功率半导体器件,其兼有MOSFET的高输入阻抗和BJT的低导通电压两方面的优点，被广泛地应用于轨道交通、智能电网、航空航天、电动汽车、新能源设备等领域。An insulated gate bipolar transistor (IGBT) is a voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and a metal oxide semiconductor field effect transistor (MOSFET). The advantages of the two aspects of the on-voltage are widely used in rail transit, smart grid, aerospace, electric vehicles, new energy equipment and other fields.
目前，针对IGBT的研究的目的主要在于提高IGBT的功率密度和开关速度以及降低IGBT的功耗。为此，现有技术中提出了一种沟槽型IGBT装置，其通过将栅极从水平方向调整为垂直方向而将IGBT中的电流沟道方向从器件表面的横向方向转换为器件体内的垂直方向，使得能够消除IGBT中的结型场效应晶体管(JFET)效应，同时能够增加沟道密度和近表面载流子浓度，进而可以在不增加关断损耗的情况下极大地降低集电极发射极(源极)导通电压(Vceon)。At present, the main purpose of research on IGBT is to improve the power density and switching speed of IGBT and reduce the power consumption of IGBT. To this end, a trench-type IGBT device is proposed in the prior art, which converts the current channel direction in the IGBT from the lateral direction of the device surface to the vertical direction in the device body by adjusting the gate from the horizontal direction to the vertical direction direction, enabling the elimination of the junction field effect transistor (JFET) effect in the IGBT while increasing the channel density and near-surface carrier concentration, which in turn can greatly reduce collector-emitter without increasing turn-off losses (Source) turn-on voltage (Vceon).
然而，对于沟槽型IGBT，高沟道密度以及随之带来的低导通电压Vceon会提高饱和电流，因而可能对IGBT的短路性能造成不利影响。因此，通常需要在进行版图设计时采用伪栅和/或伪阱的伪区(dummy area)以平衡短路电流和导通损耗之间的折衷关系。然而，这会增加版图设计的复杂度并且增加制造成本。However, for trench IGBTs, the high channel density and consequent low on-voltage Vceon increases the saturation current, which may adversely affect the short-circuit performance of the IGBT. Therefore, dummy areas of dummy gates and/or dummy wells are usually required to balance the trade-off relationship between short-circuit current and conduction loss during layout design. However, this increases layout complexity and increases manufacturing costs.
发明内容SUMMARY OF THE INVENTION
在下文中给出了关于本公开内容的简要概述，以便提供关于本公开内容的某些方面的基本理解。但是，应当理解，此概述并非关于本公开内容的穷举性概述，也非意在确定本公开内容的关键性部分或重要部分，更非意在限定本公开内容的范围。此概述的目的仅在于以简化的形式给出关于 本公开内容的某些发明构思，以此作为稍后给出的更详细的描述的前序。The following presents a brief summary of the present disclosure in order to provide a basic understanding of certain aspects of the present disclosure. It should be understood, however, that this summary is not an exhaustive overview of the disclosure, nor is it intended to identify key or critical portions of the disclosure, nor is it intended to limit the scope of the disclosure. Its sole purpose is to present some inventive concepts related to the present disclosure in a simplified form as a prelude to the more detailed description that is presented later.
本公开内容的目的在于提供能够克服现有技术中存在的上述问题的沟槽型绝缘栅双极型晶体管(IGBT)装置及其制备方法。The purpose of the present disclosure is to provide a trench-type insulated gate bipolar transistor (IGBT) device and a manufacturing method thereof that can overcome the above-mentioned problems in the prior art.
根据本公开内容的一个方面，提供了一种绝缘栅双极型晶体管装置，其包括：第一导电类型的衬底；以及多个沟槽，从衬底的上表面向下形成以具有沿第一方向延伸的彼此平行的条形形状并且其中分别设置有多个栅极，其中，在沟槽之间形成有源区，并且有源区具有沿第一方向延伸的第一导电类型的源极区和第二导电类型的接触区，其中，接触区具有在垂直于第一方向的第二方向上的第一宽度和不同于第一宽度的第二宽度，第一宽度和第二宽度沿第一方向交替布置，以及栅极具有在第二方向上的均匀的第三宽度。According to one aspect of the present disclosure, there is provided an insulated gate bipolar transistor device comprising: a substrate of a first conductivity type; and a plurality of trenches formed downwardly from an upper surface of the substrate to have along a first conductivity type Strip shapes extending in one direction parallel to each other and having a plurality of gate electrodes disposed therein, respectively, wherein an active region is formed between the trenches, and the active region has a source electrode of a first conductivity type extending in a first direction region and a contact region of the second conductivity type, wherein the contact region has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the second width along the The one direction is alternately arranged, and the gate electrode has a uniform third width in the second direction.
根据本公开内容的另一方面，提供了一种绝缘栅双极型晶体管装置，其包括：第一导电类型的衬底；以及多个沟槽，从衬底的上表面向下形成以具有沿第一方向延伸的彼此平行的条形形状并且其中分别设置有多个栅极，其中，在沟槽之间形成有源区，并且有源区具有沿第一方向延伸的第一导电类型的源极区和第二导电类型的接触区，其中，栅极具有在垂直于第一方向的第二方向上的第一宽度和不同于第一宽度的第二宽度，第一宽度和第二宽度沿第一方向交替布置，以及接触区具有在第二方向上的均匀的第三宽度。According to another aspect of the present disclosure, there is provided an insulated gate bipolar transistor device comprising: a substrate of a first conductivity type; and a plurality of trenches formed downwardly from an upper surface of the substrate to have along strip shapes extending in a first direction parallel to each other and having a plurality of gate electrodes disposed therein, respectively, wherein an active region is formed between the trenches, and the active region has a source of a first conductivity type extending in the first direction A pole region and a contact region of the second conductivity type, wherein the gate has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the second width being along the The first directions are alternately arranged, and the contact areas have a uniform third width in the second direction.
根据本公开内容的又一方面，提供了一种制备绝缘栅双极型晶体管装置的方法，其包括：从第一导电类型的衬底的上表面向下形成多个沟槽，使得多个沟槽具有沿第一方向延伸的彼此平行的条形形状；在多个沟槽中分别设置多个栅极；以及使用同一掩模在沟槽之间形成的有源区的每个中形成第一导电类型的源极区和第二导电类型的接触区，使得接触区具有在垂直于第一方向的第二方向上的第一宽度和不同于第一宽度的第二宽度，第一宽度和第二宽度沿第一方向交替布置。According to yet another aspect of the present disclosure, there is provided a method of fabricating an insulated gate bipolar transistor device comprising: forming a plurality of trenches downward from an upper surface of a substrate of a first conductivity type such that the plurality of trenches The grooves have strip shapes extending in parallel with each other in a first direction; a plurality of gate electrodes are respectively provided in the plurality of trenches; and a first A source region of a conductivity type and a contact region of a second conductivity type such that the contact region has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the first width The two widths are alternately arranged along the first direction.
根据本公开内容的沟槽型IGBT装置不需要复杂的版图设计并且可以以简化的常规半导体工艺步骤制备，从而能够降低制造成本。同时，根据本公开内容的沟槽型IGBT装置能够降低饱和电流，从而改善短路性能。The trench-type IGBT device according to the present disclosure does not require complicated layout design and can be fabricated with simplified conventional semiconductor process steps, so that the manufacturing cost can be reduced. Meanwhile, the trench IGBT device according to the present disclosure can reduce saturation current, thereby improving short-circuit performance.
附图说明Description of drawings
所包括的附图用于提供本公开内容的进一步理解，并且被并入本说明书中构成本说明书的一部分。附图示出了本公开内容的实施方式，连同下面的描述一起用于说明本公开内容的原理。在附图中：The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure, and together with the following description serve to explain the principles of the disclosure. In the attached image:
图1A示出了根据本公开内容的第一实施方式的沟槽型IGBT装置的平面视图；1A shows a plan view of a trench IGBT device according to a first embodiment of the present disclosure;
图1B示出了根据本公开内容的第一实施方式的沟槽型IGBT装置的透视图；FIG. 1B shows a perspective view of a trench IGBT device according to the first embodiment of the present disclosure;
图2示出了沿图1A的线AA'截取的根据本公开内容的第一实施方式的沟槽型IGBT装置的剖面透视图；2 shows a cross-sectional perspective view of the trench IGBT device according to the first embodiment of the present disclosure, taken along line AA' of FIG. 1A;
图3示出了沿图1A的线BB'截取的根据本公开内容的第一实施方式的沟槽型IGBT装置的剖面透视图；3 shows a cross-sectional perspective view of the trench IGBT device according to the first embodiment of the present disclosure, taken along line BB' of FIG. 1A ;
图4示出了根据本公开内容的第一实施方式的沟槽型IGBT装置的I-V特性曲线；FIG. 4 shows an I-V characteristic curve of the trench IGBT device according to the first embodiment of the present disclosure;
图5示出了根据本公开内容的第一实施方式的沟槽型IGBT装置的饱和电流的曲线；FIG. 5 shows a graph of saturation current of the trench IGBT device according to the first embodiment of the present disclosure;
图6示出了根据本公开内容的第二实施方式的沟槽型IGBT装置的平面视图；6 shows a plan view of a trench IGBT device according to a second embodiment of the present disclosure;
图7示出了沿图6的线CC'截取的根据本公开内容的第二实施方式的沟槽型IGBT装置的剖面透视图；以及7 illustrates a cross-sectional perspective view of a trench IGBT device according to a second embodiment of the present disclosure, taken along line CC' of FIG. 6; and
图8示出了沿图6的线DD'截取的根据本公开内容的第二实施方式的沟槽型IGBT装置的剖面透视图。8 illustrates a cross-sectional perspective view of a trench IGBT device according to a second embodiment of the present disclosure, taken along line DD' of FIG. 6 .
具体实施方式Detailed ways
在本说明书中，还将理解，当一个部件(或区域、层、部分)被称为相对于其他元件，诸如在其他元件“上”，“连接到”或“耦接到”其他元件时，该一个部件可以直接设置在该一个部件上/直接连接到/直接耦接到该一个部件，或者还可以存在居间的第三部件。相反，当在本说明书中元件(或区域、层、部分等)被称为相对于其他元件，诸如“直接”在其他元件“上”，“直接连接到”或“直接耦接到”其他元件时，在它们之间没 有设置居间的元件。In this specification, it will also be understood that when an element (or region, layer, section) is referred to as being "on," "connected to," or "coupled to" other elements relative to other elements, The one component may be disposed directly on/connected/coupled directly to the one component, or there may also be an intervening third component. Conversely, when an element (or region, layer, section, etc.) is referred to in this specification as being relative to other elements, such as being "directly on", "directly connected to" or "directly coupled to" the other element , there is no intervening element between them.
现将在下文中参照附图更全面地描述本公开内容，在附图中示出了各实施方式。然而，本公开内容可以以许多不同的方式实施，并且不应被解释为限于本文阐述的实施方式。相反，这些实施方式被提供使得本公开内容将是详尽的和完整的，并且将向本领域技术人员全面传达本公开内容的范围。通篇相同的附图标记表示相同的元件。再者，在附图中，为了清楚地说明，部件的厚度、比率和尺寸被放大。The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numbers refer to the same elements throughout. Also, in the drawings, the thicknesses, ratios and sizes of components are exaggerated for clarity of explanation.
本文使用的术语仅用于描述具体实施方式的目的，而非旨在成为限制。除非上下文清楚地另有所指，否则如本文使用的“一”、“一个”、“该”和“至少一个”并非表示对数量的限制，而是旨在包括单数和复数二者。例如，除非上下文清楚地另有所指，否则“一个元件”的含义与“至少一个元件”相同。“至少一个”不应被解释为限制“一”或“一个”。“或”意指“和/或”。术语“和/或”包括相关联的列出项中的一个或更多个的任何和全部组合。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, "a," "an," "the," and "at least one" do not denote limitations of quantity, but are intended to include both the singular and the plural, unless the context clearly dictates otherwise. For example, "an element" is synonymous with "at least one element" unless the context clearly dictates otherwise. "At least one" should not be construed as limiting "a" or "an." "Or" means "and/or". The term "and/or" includes any and all combinations of one or more of the associated listed items.
将理解，尽管在本文中使用诸如“第一”和“第二”的术语描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于使一个部件区别于其他部件。例如，在不偏离所附权利要求的范围的情况下，在一个实施方式中被称为第一元件的第一元件可以在其他实施方式中被称为第二元件。It will be understood that, although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from another. For example, a first element referred to as a first element in one embodiment could be referred to as a second element in other embodiments without departing from the scope of the appended claims.
再者，“下面”、“下方”、“上方”、“上”等用于说明图中所示的部件的关系关联。这些术语可以是相对的概念并且基于图中呈现的方向来描述。In addition, "below", "below", "above", "upper" and the like are used to describe the relationship between components shown in the drawings. These terms may be relative concepts and are described based on the directions presented in the figures.
考虑到所讨论的测量以及与特定量的测量相关联的误差(即，测量系统的限制)，如本文中使用的“约”或“大致”包含所陈述的值以及如本领域普通技术人员所确定的关于特定值的可接受的偏差范围内的平均值。例如，“约”可以意指一个或更多个标准偏差内的平均值，或者所陈述的值的±30％、20％、10％、5％内的平均值。"About" or "approximately" as used herein includes the stated value as well as the The average value within an acceptable deviation range determined with respect to a particular value. For example, "about" can mean an average within one or more standard deviations, or an average within ±30%, 20%, 10%, 5% of the stated value.
除非另有限定，否则本文使用的所有术语(包括技术术语和科学术语)具有与本领域技术人员所通常理解的含义相同的含义。如共同使用的词典中限定的术语应被解释为具有与相关的技术上下文中的含义相同的含义，并且除非在说明书中明确限定，否者不在理想化的或者过于正式的意义上 将这些术语解释为具有正式的含义。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Terms as defined in commonly used dictionaries should be construed as having the same meaning as in the relevant technical context, and unless explicitly defined in the specification, these terms are not to be interpreted in an idealized or overly formal sense to have a formal meaning.
“包括”或“包含”的含义指明了性质、数量、步骤、操作、元件、部件或它们的组合，但是并未排除其他的性质、数量、步骤、操作、元件、部件或它们的组合。The meaning of "comprising" or "comprising" specifies properties, quantities, steps, operations, elements, components, or combinations thereof, but does not exclude other properties, numbers, steps, operations, elements, components, or combinations thereof.
本文参照作为理想化的实施方式的示意图的剖面透视图描述了实施方式。从而，预见到作为例如制造技术和/或公差的结果的、相对于图示的形状变化。因此，本文描述的实施方式不应被解释为限于如本文示出的区域的具体形状，而是应包括因例如制造导致的形状的偏差。例如，被示出或描述为平坦的区域可以典型地具有粗糙和/或非线性特征。而且，所示出的锐角可以被倒圆。因此，图中所示的区域在本质上是示意性的，并且它们的形状并非旨在示出区域的精确形状并且并非旨在限制权利要求的范围。Embodiments are described herein with reference to cross-sectional perspective illustrations that are schematic illustrations of idealized embodiments. Thus, shape variations from the illustrations are contemplated as a result of, for example, manufacturing techniques and/or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of regions as illustrated herein, but are to include deviations from shapes due, for example, to manufacturing. For example, regions shown or described as flat may typically have rough and/or nonlinear features. Also, the acute angles shown can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.
在下文中，将参照附图描述根据本公开内容的示例性实施方式。Hereinafter, exemplary embodiments according to the present disclosure will be described with reference to the accompanying drawings.
图1A示出了根据本公开内容的第一实施方式的沟槽型IGBT装置10的平面视图。图1B示出了根据本公开内容的第一实施方式的沟槽型IGBT装置10的透视图。图2示出了沿图1A的线AA'截取的根据本公开内容的第一实施方式的沟槽型IGBT装置10的剖面透视图。图3示出了沿图1A的线BB'截取的根据本公开内容的第一实施方式的沟槽型IGBT装置10的剖面透视图。FIG. 1A shows a plan view of a trench IGBT device 10 according to a first embodiment of the present disclosure. FIG. 1B shows a perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure. 2 shows a cross-sectional perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure, taken along line AA' of FIG. 1A . FIG. 3 shows a cross-sectional perspective view of the trench IGBT device 10 according to the first embodiment of the present disclosure, taken along line BB′ of FIG. 1A .
参照图1A至图3，根据本公开容的第一实施方式的沟槽型IGBT装置10可以包括第一导电类型的衬底3以及多个沟槽4。多个沟槽4从衬底的上表面向下形成以具有沿第一方向DR1延伸的彼此平行的条形形状并且其中分别设置有多个栅极G。在多个沟槽4之间形成有源区，并且有源区具有沿第一方向DR1延伸的第一导电类型的源极区7和第二导电类型的接触区8。接触区8具有在垂直于第一方向DR1的第二方向DR2上的第一宽度WC1和不同于第一宽度WC1的第二宽度WC2，第一宽度WC1和第二宽度WC2沿第一方向DR1交替布置。多个栅极G中的每个具有在第二方向DR2上的均匀的第三宽度WG3。1A to 3 , the trench IGBT device 10 according to the first embodiment of the present disclosure may include a substrate 3 of a first conductivity type and a plurality of trenches 4 . A plurality of trenches 4 are formed downward from the upper surface of the substrate to have strip shapes extending in the first direction DR1 parallel to each other and a plurality of gate electrodes G are respectively disposed therein. Active regions are formed between the plurality of trenches 4 and have source regions 7 of the first conductivity type and contact regions 8 of the second conductivity type extending in the first direction DR1. The contact region 8 has a first width WC1 in a second direction DR2 perpendicular to the first direction DR1 and a second width WC2 different from the first width WC1, the first width WC1 and the second width WC2 alternating along the first direction DR1 layout. Each of the plurality of gates G has a uniform third width WG3 in the second direction DR2.
本领域技术人员应理解，尽管本文以第一导电类型为N型并且第二导电类型为P型为例描述了本公开内容的第一实施方式，但是本公开内容不限于此。在本公开内容的其他实施方式中，第一导电类型也可以为P型 并且第二导电类型可以为N型。Those skilled in the art should understand that although the first embodiment of the present disclosure is described herein by taking the first conductivity type as N-type and the second conductivity type as P-type as an example, the present disclosure is not limited thereto. In other embodiments of the present disclosure, the first conductivity type may also be P-type and the second conductivity type may be N-type.
此外，本领域技术人员应理解，在本文中术语“重掺杂区域”通常是指掺杂浓度大于或等于10 18cm -3的区域，并且用符号“+”表示。此外，在本文中术语“轻掺杂区域”是指掺杂浓度小于10 18cm -3的区域，并且用符号“-”表示。例如，“n+”表示掺杂浓度大于或等于10 18cm -3的n型区域，“n-”表示掺杂浓度小于10 18cm -3的n型区域 In addition, those skilled in the art will understand that the term "heavy doped region" herein generally refers to a region with a doping concentration greater than or equal to 10 18 cm -3 and is represented by the symbol "+". Furthermore, the term "lightly doped region" herein refers to a region with a doping concentration of less than 10 18 cm -3 , and is represented by the symbol "-". For example, "n+" indicates an n-type region with a doping concentration greater than or equal to 10 18 cm -3 , and "n-" indicates an n-type region with a doping concentration less than 10 18 cm -3
具体地，如图1A中所示，根据本公开容的第一实施方式的沟槽型IGBT装置10包括沿第一方向DR1交替设置的第一元胞10A和第二元胞10B。如图1A中所示，第一元胞10A中的栅极G和第二元胞10B中的栅极G具有在第二方向DR2上的均匀的第三宽度WG3。此外，如图1A中所示，根据本公开容的第一实施方式，第一元胞10A中的p+接触区在第二方向DR2上的第一宽度WC1可以小于第二元胞10B中的p+接触区在第二方向DR2上的第二宽度WC2。Specifically, as shown in FIG. 1A , the trench IGBT device 10 according to the first embodiment of the present disclosure includes first cells 10A and second cells 10B alternately arranged along the first direction DR1 . As shown in FIG. 1A , the gate G in the first cell 10A and the gate G in the second cell 10B have a uniform third width WG3 in the second direction DR2. Furthermore, as shown in FIG. 1A , according to the first embodiment of the present disclosure, the first width WC1 of the p+ contact region in the first cell 10A in the second direction DR2 may be smaller than the p+ contact region in the second cell 10B The second width WC2 of the contact region in the second direction DR2.
参照图2和图3，图2示出了沟槽型IGBT装置10的第一元胞10A的剖面透视图，而图3示出了沟槽型IGBT装置10的第二元胞10B的剖面透视图。Referring to FIGS. 2 and 3 , FIG. 2 shows a cross-sectional perspective view of the first cell 10A of the trench IGBT device 10 , and FIG. 3 shows a cross-sectional perspective view of the second cell 10B of the trench IGBT device 10 picture.
如图2和图3中所示，根据本公开容的第一实施方式的沟槽型IGBT装置10具有设置在沿第一方向DR1延伸的垂直沟槽4，栅极G设置在沟槽4中。根据本公开内容的实施方式，可以采用刻蚀工艺形成沟槽4。此外，可以采用但不限于热氧化工艺、物理气相沉积工艺或化学气相沉积工艺在沟槽4的内表面上形成氧化层(例如，氧化硅层)作为介质层。As shown in FIGS. 2 and 3 , the trench-type IGBT device 10 according to the first embodiment of the present disclosure has vertical trenches 4 arranged in the first direction DR1 and the gate G is arranged in the trenches 4 . According to an embodiment of the present disclosure, the trench 4 may be formed using an etching process. In addition, an oxide layer (eg, a silicon oxide layer) may be formed on the inner surface of the trench 4 as a dielectric layer using, but not limited to, a thermal oxidation process, a physical vapor deposition process, or a chemical vapor deposition process.
根据本公开内容的实施方式，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺在沟槽4中形成栅极G，栅极G可以包括但不限于掺杂多晶硅。According to an embodiment of the present disclosure, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be employed to form the gate G in the trench 4, and the gate G may include, but is not limited to, doped polysilicon.
在根据本公开内容的第一实施方式中的沟槽型IGBT装置10中，由于采用垂直栅极G将沟道从横向方向变为垂直方向，因此可以减小元胞尺寸以提高元胞密度，使得可以增加IGBT装置的沟道总体宽度并且减小沟道电阻。另一方面，沟槽栅极中的多晶硅栅的面积增大，使得可以减少分布电阻，有利于提高开关速度。In the trench IGBT device 10 according to the first embodiment of the present disclosure, since the vertical gate G is used to change the channel from the lateral direction to the vertical direction, the cell size can be reduced to increase the cell density, This makes it possible to increase the overall channel width of the IGBT device and reduce the channel resistance. On the other hand, the area of the polysilicon gate in the trench gate is increased, so that the distributed resistance can be reduced, which is beneficial to improve the switching speed.
参照图2和图3，根据本公开容的第一实施方式的沟槽型IGBT装置10在沟槽4之间形成有源区，有源区可以从底部到顶部包括p+型集电极 层1、n+型缓冲层2、n-型半导体衬底3、p-型沟道层5、n-型载流子阻挡层6、n+型源极(发射极)区7和p+型接触区8。Referring to FIGS. 2 and 3 , the trench IGBT device 10 according to the first embodiment of the present disclosure forms an active region between the trenches 4 , and the active region may include a p+ type collector layer 1 , n+ type buffer layer 2 , n- type semiconductor substrate 3 , p- type channel layer 5 , n- type carrier blocking layer 6 , n+ type source (emitter) region 7 and p+ type contact region 8 .
尽管图中没有示出，但是在本公开内容的第一实施方式中，沟槽型IGBT装置10还可以包括集电极金属层，其设置在p+型集电极层1上并且与p+型集电极层1电接触。此外，沟槽型IGBT装置10还可以包括源极金属层，其设置在n+型源极区7和p+型接触区8上并且与n+型源极区7和p+型接触区8电接触。此外，沟槽型IGBT装置10还可以包括栅极电极，其可以以通孔方式与沟槽4中的垂直栅极电接触。Although not shown in the drawings, in the first embodiment of the present disclosure, the trench type IGBT device 10 may further include a collector metal layer disposed on the p+ type collector layer 1 and connected to the p+ type collector layer 1 electrical contact. Furthermore, the trench IGBT device 10 may further include a source metal layer disposed on and in electrical contact with the n+ type source region 7 and the p+ type contact region 8 . Furthermore, the trench IGBT device 10 may also include a gate electrode, which may be in electrical contact with the vertical gate in the trench 4 in a through-hole manner.
根据本公开内容的实施方式，p+型集电极层1可以用作空穴注入层，其与n+型缓冲层2形成正向偏置的PN结以增加空穴注入效应。此外，根据本公开内容的实施方式，n+型缓冲层2可以用作电场截止层，用于在IGBT关断时产生与从p+型集电极层1注入的空穴复合的电子，从而提高关断速度。According to an embodiment of the present disclosure, the p+ type collector layer 1 may function as a hole injection layer, which forms a forward biased PN junction with the n+ type buffer layer 2 to increase the hole injection effect. In addition, according to the embodiment of the present disclosure, the n+ type buffer layer 2 may function as an electric field stop layer for generating electrons that recombine with holes injected from the p+ type collector layer 1 when the IGBT is turned off, thereby improving the turn-off speed.
根据本公开内容的实施方式，n-型半导体衬底3可以是具有高电阻率的衬底。例如，n-型半导体衬底3可以是FZ晶片或MCZ晶片。此外，根据本公开内容的实施方式，n-型半导体衬底3还可以包括但不仅限于硅衬底、碳化硅、氮化镓衬底或锗硅衬底。According to an embodiment of the present disclosure, the n-type semiconductor substrate 3 may be a substrate having a high resistivity. For example, the n-type semiconductor substrate 3 may be an FZ wafer or an MCZ wafer. In addition, according to an embodiment of the present disclosure, the n-type semiconductor substrate 3 may also include, but is not limited to, a silicon substrate, a silicon carbide, a gallium nitride substrate, or a silicon germanium substrate.
根据本公开内容的实施方式，p-型沟道层5、n-型载流子阻挡层6和n+型源极区7可以在沟槽4之间形成，使得与沟槽4的侧壁接触。根据本公开内容的实施方式，p-型沟道层5在n-型载流子阻挡层6上形成，并且n+型源极区7在p-型沟道层5上形成。According to an embodiment of the present disclosure, the p-type channel layer 5 , the n-type carrier blocking layer 6 and the n+ type source region 7 may be formed between the trenches 4 so as to be in contact with the sidewalls of the trenches 4 . According to an embodiment of the present disclosure, the p-type channel layer 5 is formed on the n-type carrier blocking layer 6 , and the n+ type source region 7 is formed on the p-type channel layer 5 .
根据本公开内容的实施方式，n-型载流子阻挡层6在垂直方向上的深度小于垂直沟槽4的深度。换言之，在垂直方向上，n-型载流子阻挡层6的下表面可以高于沟槽4的下表面。According to an embodiment of the present disclosure, the depth of the n-type carrier blocking layer 6 in the vertical direction is smaller than the depth of the vertical trench 4 . In other words, the lower surface of the n-type carrier blocking layer 6 may be higher than the lower surface of the trench 4 in the vertical direction.
根据本公开内容的实施方式，p+型接触区8的基本结构是通过在刻蚀沟槽之后进行离子注入形成的。通过刻蚀沟槽之后进行离子注入的方式，p+型接触区8的形成不需要使用额外的掩模，同时深沟槽的p+接触区8能够有效地提高沟槽型IGBT装置的抗闩锁能力。According to the embodiment of the present disclosure, the basic structure of the p+ type contact region 8 is formed by ion implantation after etching the trench. By performing ion implantation after etching the trench, the formation of the p+ contact region 8 does not require an additional mask, and the deep trench p+ contact region 8 can effectively improve the latch-up resistance of the trench IGBT device .
根据本公开内容的实施方式，p+型接触区8还可以通过例如离子注入工艺在n+型源极区7中形成。可以通过离子注入能量来控制p+型接触区8的注入深度，换言之，p+型接触区8的注入深度越大，则所需的离子注 入能量越大。本领域技术人员应认识到，p+型接触区8的注入深度不应超过p-型沟道层5的深度。According to an embodiment of the present disclosure, the p+ type contact region 8 may also be formed in the n+ type source region 7 by, for example, an ion implantation process. The implantation depth of the p+-type contact region 8 can be controlled by the ion implantation energy, in other words, the larger the implantation depth of the p+-type contact region 8, the larger the required ion implantation energy. Those skilled in the art will realize that the implantation depth of the p+-type contact region 8 should not exceed the depth of the p-type channel layer 5 .
根据本公开内容的实施方式，p+型接触区8在垂直方向上的深度可以大于n+型源极区7的深度。换言之，在垂直方向上，p+型接触区8的下表面可以低于n+型源极区7的下表面，但是不低于p-型沟道层5的下表面。According to an embodiment of the present disclosure, the depth of the p+ type contact region 8 in the vertical direction may be greater than that of the n+ type source region 7 . In other words, in the vertical direction, the lower surface of the p+ type contact region 8 may be lower than the lower surface of the n+ type source region 7 , but not lower than the lower surface of the p− type channel layer 5 .
根据本公开内容的上述实施方式形成的IGBT结构可被称为载流子存储沟槽型IGBT，其中在p-型沟道层5下方形成的n-型载流子阻挡层6可以用于存储载流子。在传统的沟槽型IGBT装置中，空穴密度随着距源极(发射极)的距离减小而减小。然而，在根据本公开内容的上述实施方式形成的沟槽型IGBT装置中，即使在源极侧仍可以保持高的空穴密度，这样可以减小导通电压(即Vceon)而不增加关断损耗。The IGBT structure formed according to the above-described embodiment of the present disclosure may be referred to as a carrier storage trench IGBT, in which the n-type carrier blocking layer 6 formed under the p-type channel layer 5 may be used for storage carrier. In conventional trench IGBT devices, the hole density decreases as the distance from the source (emitter) decreases. However, in the trench IGBT devices formed according to the above-described embodiments of the present disclosure, a high hole density can be maintained even on the source side, which can reduce the on-voltage (ie, Vceon) without increasing the turn-off loss.
此外，在根据本公开内容的上述实施方式形成的IGBT结构中，由于n+型源极区7和p+型接触区8的版图设置，还可以极大地消除由n+型源极区7、p-型沟道层5、n-型半导体衬底3和p+型集电极层1形成的寄生NPNP晶闸管的闩锁(latch-up)效应。In addition, in the IGBT structure formed according to the above-described embodiment of the present disclosure, due to the layout arrangement of the n+ type source region 7 and the p+ type contact region 8, it is also possible to greatly eliminate the formation of the n+ type source region 7, p-type The latch-up effect of the parasitic NPNP thyristor formed by the channel layer 5 , the n- type semiconductor substrate 3 and the p+ type collector layer 1 .
此外，如图1A中所示，具有不同的p+型接触区8的宽度的第一元胞10A和第二元胞10B沿第一方向DR1交替设置。在第一元胞10A和第二元胞10B中分别形成沟槽型IGBT器件。Furthermore, as shown in FIG. 1A , the first cells 10A and the second cells 10B having different widths of the p+ type contact regions 8 are alternately arranged along the first direction DR1 . Trench-type IGBT devices are formed in the first cell 10A and the second cell 10B, respectively.
如上文所述，第二元胞10B中的P+接触区8的第二宽度WC2可以大于第一元胞10A中的P+接触区8的第一宽度WC1。也就是说，在第二元胞10B中，通过离子注入工艺形成的p+型接触区8与沟槽4的侧壁之间的距离在约0.1μm至约0.5μm的范围内，使得第二元胞10B中的IGBT器件的沟道掺杂浓度大于10 18cm -3，因此第二元胞10B中的IGBT器件是常断的。相反，在第一元胞10A中，p+型接触区8与沟槽4的侧壁之间的距离大于约1.0μm，使得第一元胞10A中的沟槽型IGBT器件能够正常操作。 As described above, the second width WC2 of the P+ contact region 8 in the second cell 10B may be greater than the first width WC1 of the P+ contact region 8 in the first cell 10A. That is, in the second cell 10B, the distance between the p+ type contact region 8 formed by the ion implantation process and the sidewall of the trench 4 is in the range of about 0.1 μm to about 0.5 μm, so that the second cell 10B The channel doping concentration of the IGBT device in the cell 10B is greater than 10 18 cm -3 , so the IGBT device in the second cell 10B is normally off. In contrast, in the first cell 10A, the distance between the p+ type contact region 8 and the sidewall of the trench 4 is greater than about 1.0 μm, so that the trench IGBT device in the first cell 10A can operate normally.
也就是说，根据本公开内容的第一实施方式的沟槽型IGBT装置具有交替设置的彼此并联的正常的IGBT器件和常断的IGBT器件的元胞布置。因此，根据本公开内容的第一实施方式的沟槽型IGBT装置可以在不牺牲I-V特性的情况下保持小的饱和电流。此外，由于第二元胞10B中的IGBT 器件是常断的，因此第二元胞10B中的IGBT器件中的栅极可被视为伪栅，从而还可以减少栅极电荷(Qg)。因此，在根据本公开内容的第一实施方式的沟槽型IGBT装置中无需再另外添加用于平衡短路电流和导通损耗之间的折衷关系的伪区，使得能够简化制造工艺并且减小芯片面积。That is, the trench IGBT device according to the first embodiment of the present disclosure has a cell arrangement of normal IGBT devices and normally-off IGBT devices that are alternately arranged in parallel with each other. Therefore, the trench IGBT device according to the first embodiment of the present disclosure can maintain a small saturation current without sacrificing I-V characteristics. In addition, since the IGBT devices in the second cell 10B are normally off, the gates in the IGBT devices in the second cell 10B can be regarded as dummy gates, so that the gate charge (Qg) can also be reduced. Therefore, there is no need to additionally add a dummy region for balancing the trade-off relationship between short-circuit current and conduction loss in the trench IGBT device according to the first embodiment of the present disclosure, so that the manufacturing process can be simplified and the chip size can be reduced area.
根据本公开内容的第一实施方式，通过调整第一元胞10A中的p+型接触区8的第一宽度WC1与n+型源极区7沿第二方向DR2的第四宽度WE4之间的比例关系，可以对沟槽型IGBT装置的I-V特性进行调整。According to the first embodiment of the present disclosure, by adjusting the ratio between the first width WC1 of the p+ type contact region 8 in the first cell 10A and the fourth width WE4 of the n+ type source region 7 along the second direction DR2 relationship, the I-V characteristics of the trench IGBT device can be adjusted.
图4示出了根据本公开内容的第一实施方式的沟槽型IGBT装置的I-V特性曲线。图5示出了根据本公开内容的第一实施方式的沟槽型IGBT装置的饱和电流的曲线。FIG. 4 shows an I-V characteristic curve of the trench IGBT device according to the first embodiment of the present disclosure. FIG. 5 shows a graph of saturation current of the trench IGBT device according to the first embodiment of the present disclosure.
如图4和图5中所示，通过改变第一宽度WC1和第四宽度WE4之间的比例关系，可以调整沟槽型IGBT装置的I-V特性。As shown in FIGS. 4 and 5 , by changing the proportional relationship between the first width WC1 and the fourth width WE4 , the I-V characteristics of the trench IGBT device can be adjusted.
根据本公开内容的第一实施方式，第一元胞10A和第二元胞10B沿第一方向DR1的长度可以是相同的。根据本公开内容的第一实施方式，第一元胞10A和第二元胞10B沿第一方向DR1的长度可以是不同的。在第一元胞10A和第二元胞10B沿第一方向DR1的长度不同的情况下，通过调整第一元胞10A和第二元胞10B沿第一方向DR1的长度之间的比例关系，同样可以对沟槽型IGBT装置的I-V特性进行调整。According to the first embodiment of the present disclosure, the lengths of the first cell 10A and the second cell 10B along the first direction DR1 may be the same. According to the first embodiment of the present disclosure, the lengths of the first cell 10A and the second cell 10B along the first direction DR1 may be different. When the lengths of the first cell 10A and the second cell 10B along the first direction DR1 are different, by adjusting the proportional relationship between the lengths of the first cell 10A and the second cell 10B along the first direction DR1, The I-V characteristics of the trench IGBT device can also be adjusted.
用于制造根据本公开内容的第一实施方式的沟槽型IGBT装置10的方法可以包括如下步骤：从第一导电类型的衬底3的上表面向下形成多个沟槽4，使得多个沟槽4具有沿第一方向DR1延伸的彼此平行的条形形状；在多个沟槽4中分别设置多个栅极G；以及使用同一掩模在沟槽4之间形成的有源区的每个中形成第一导电类型的源极区7和第二导电类型的接触区8，使得接触区8具有在垂直于第一方向DR1的第二方向DR2上的第一宽度WC1和不同于第一宽度WC1的第二宽度WC2，第一宽度WC1和第二宽度WC2沿第一方向DR1交替布置。The method for manufacturing the trench-type IGBT device 10 according to the first embodiment of the present disclosure may include the step of forming a plurality of trenches 4 downward from the upper surface of the substrate 3 of the first conductivity type such that a plurality of trenches 4 are formed. The trenches 4 have stripe shapes that are parallel to each other extending in the first direction DR1; a plurality of gates G are respectively provided in the plurality of trenches 4; and the active regions formed between the trenches 4 using the same mask The source region 7 of the first conductivity type and the contact region 8 of the second conductivity type are formed in each such that the contact region 8 has a first width WC1 in a second direction DR2 perpendicular to the first direction DR1 and a A second width WC2 of a width WC1, the first width WC1 and the second width WC2 are alternately arranged along the first direction DR1.
例如，可以在作为FZ晶片或MCZ晶片的n-型半导体衬底3上制造沟槽型IGBT装置。首先，在n-型半导体衬底3的上表面上通过例如刻蚀工艺形成沿第一方向DR1延伸的多个沟槽4。随后，在多个沟槽4中通过例如物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成多个栅极G，多个栅极G具有沿第二方向DR2的均匀的第三宽度WG3。随后， 在多个沟槽4之间在n-型半导体衬底3的上表面上依次通过高能离子注入形成n-型载流子阻挡层6、p-型沟道层5、n+型源极区7和p+型接触区8，其中n+型源极区7和p+型接触区8可以使用同一个掩模形成，因此可以简化工艺步骤。最后，在n-型半导体衬底3的下表面上依次通过高能离子注入形成n+型缓冲层2和低能量离子注入形成p+型集电极层1以完成沟槽型IGBT装置，其中n+型缓冲层可以为多种离子形式的注入，如质子，磷等。For example, a trench-type IGBT device can be fabricated on an n-type semiconductor substrate 3 as an FZ wafer or an MCZ wafer. First, a plurality of trenches 4 extending in the first direction DR1 are formed on the upper surface of the n-type semiconductor substrate 3 by, for example, an etching process. Subsequently, a plurality of gates G having a uniform third width WG3 along the second direction DR2 are formed in the plurality of trenches 4 by, for example, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process . Subsequently, an n-type carrier blocking layer 6, a p-type channel layer 5, and an n+-type source electrode are sequentially formed by high-energy ion implantation on the upper surface of the n-type semiconductor substrate 3 between the plurality of trenches 4 The region 7 and the p+ type contact region 8, wherein the n+ type source region 7 and the p+ type contact region 8 can be formed using the same mask, thus simplifying the process steps. Finally, on the lower surface of the n-type semiconductor substrate 3, an n+-type buffer layer 2 is formed by high-energy ion implantation and a p+-type collector layer 1 is formed by low-energy ion implantation in sequence to complete the trench IGBT device, wherein the n+-type buffer layer is It can be implanted in a variety of ion forms, such as protons, phosphorus, etc.
根据本公开内容的第一实施方式的沟槽型IGBT装置中的元胞的数量可以根据应用场景以及适用范围进行调整。The number of cells in the trench IGBT device according to the first embodiment of the present disclosure can be adjusted according to application scenarios and application scopes.
图6示出了根据本公开内容的第二实施方式的沟槽型IGBT装置20的平面视图。图7示出了沿图6的线CC'截取的根据本公开内容的第二实施方式的沟槽型IGBT装置20的剖面透视图。图8示出了沿图6的线DD'截取的根据本公开内容的第二实施方式的沟槽型IGBT装置20的剖面透视图。FIG. 6 shows a plan view of a trench IGBT device 20 according to a second embodiment of the present disclosure. FIG. 7 shows a cross-sectional perspective view of the trench IGBT device 20 according to the second embodiment of the present disclosure, taken along line CC′ of FIG. 6 . FIG. 8 shows a cross-sectional perspective view of the trench IGBT device 20 according to the second embodiment of the present disclosure, taken along the line DD′ of FIG. 6 .
参照图6至图8，根据本公开容的第二实施方式的沟槽型IGBT装置20可以包括第一导电类型的衬底3以及多个沟槽4。多个沟槽4从衬底的上表面向下形成以具有沿第一方向DR1延伸的彼此平行的条形形状并且其中分别设置有多个栅极G。在多个沟槽4之间形成有源区，并且有源区具有沿第一方向DR1延伸的第一导电类型的源极区7和第二导电类型的接触区8。多个栅极G中的每个具有在垂直于第一方向DR1的第二方向DR2上的第一宽度WG1和不同于第一宽度的第二宽度WG2，第一宽度WG1和第二宽度WG2沿第一方向DR1交替布置。接触区8具有在第二方向DR2上的均匀的第三宽度WC3。6 to 8 , the trench IGBT device 20 according to the second embodiment of the present disclosure may include a substrate 3 of a first conductivity type and a plurality of trenches 4 . A plurality of trenches 4 are formed downward from the upper surface of the substrate to have strip shapes extending in the first direction DR1 parallel to each other and a plurality of gate electrodes G are respectively disposed therein. Active regions are formed between the plurality of trenches 4 and have source regions 7 of the first conductivity type and contact regions 8 of the second conductivity type extending in the first direction DR1. Each of the plurality of gates G has a first width WG1 in a second direction DR2 perpendicular to the first direction DR1 and a second width WG2 different from the first width along the The first directions DR1 are alternately arranged. The contact region 8 has a uniform third width WC3 in the second direction DR2.
本领域技术人员应理解，尽管本文以第一导电类型为N型并且第二导电类型为P型为例描述了本公开内容的第二实施方式，但是本公开内容不限于此。在本公开内容的其他实施方式中，第一导电类型也可以为P型并且第二导电类型可以为N型。Those skilled in the art should understand that although the first conductivity type is N-type and the second conductivity type is P-type as an example to describe the second embodiment of the present disclosure, the present disclosure is not limited thereto. In other embodiments of the present disclosure, the first conductivity type may also be P-type and the second conductivity type may be N-type.
具体地，如图6中所示，根据本公开容的第二实施方式的沟槽型IGBT装置20包括沿第一方向DR1交替设置的第一元胞20A和第二元胞20B。如图6中所示，第一元胞20A中的p+接触区和第二元胞10B中的p+接触区具有在第二方向DR2上的均匀的第三宽度WC3。此外，如图6中所示， 根据本公开容的第二实施方式，第一元胞20A中的栅极G在第二方向DR2上的第一宽度WG1可以小于第二元胞10B中的栅极G在第二方向DR2上的第二宽度WG2。Specifically, as shown in FIG. 6 , the trench IGBT device 20 according to the second embodiment of the present disclosure includes first cells 20A and second cells 20B alternately arranged along the first direction DR1 . As shown in FIG. 6 , the p+ contact region in the first cell 20A and the p+ contact region in the second cell 10B have a uniform third width WC3 in the second direction DR2. Furthermore, as shown in FIG. 6 , according to the second embodiment of the present disclosure, the first width WG1 of the gate G in the first cell 20A in the second direction DR2 may be smaller than that of the gate G in the second cell 10B The second width WG2 of the pole G in the second direction DR2.
除了在本公开内容的第二实施方式中，栅极G具有沿第一方向DR1的交替设置的第一宽度WG1和第二宽度WG2，而p+接触区具有沿第一方向DR1的均匀的第三宽度WC3之外，本公开内容的第二实施方式与本公开内容的第一实施方式基本上相同，因此本文对根据本公开内容的第二实施方式的沟槽型IGBT装置20的结构的细节不作进一步的详细描述。Except in the second embodiment of the present disclosure, the gate G has a first width WG1 and a second width WG2 alternately arranged along the first direction DR1, and the p+ contact region has a uniform third width along the first direction DR1 Except for the width WC3, the second embodiment of the present disclosure is basically the same as the first embodiment of the present disclosure, so details of the structure of the trench IGBT device 20 according to the second embodiment of the present disclosure are not made here. further detailed description.
如图6中所示，具有不同的栅极G的宽度的第一元胞20A和第二元胞20B沿第一方向DR1交替设置。在第一元胞20A和第二元胞20B中分别形成沟槽型IGBT器件。As shown in FIG. 6 , the first cells 20A and the second cells 20B having different widths of the gate G are alternately arranged along the first direction DR1. Trench-type IGBT devices are formed in the first cell 20A and the second cell 20B, respectively.
如上文所述，第二元胞20B中的栅极G的第二宽度WG2可以大于第一元胞20A中的栅极G的第一宽度WC1。也就是说，在第二元胞20B中，通过离子注入工艺形成的p+型接触区8与沟槽4的侧壁之间的距离在约0.1μm至约0.5μm的范围内，使得第二元胞20B中的IGBT器件的沟道掺杂浓度大于10 18cm -3，因此第二元胞20B中的IGBT器件是常断的。相反，在第一元胞20A中，p+型接触区8与沟槽4的侧壁之间的距离大于约1.0μm，使得第一元胞20A中的沟槽型IGBT器件能够正常操作。 As described above, the second width WG2 of the gate G in the second cell 20B may be greater than the first width WC1 of the gate G in the first cell 20A. That is, in the second cell 20B, the distance between the p+ type contact region 8 formed by the ion implantation process and the sidewall of the trench 4 is in the range of about 0.1 μm to about 0.5 μm, so that the second cell 20B The channel doping concentration of the IGBT device in the cell 20B is greater than 10 18 cm -3 , so the IGBT device in the second cell 20B is normally off. In contrast, in the first cell 20A, the distance between the p+ type contact region 8 and the sidewall of the trench 4 is greater than about 1.0 μm, so that the trench IGBT device in the first cell 20A can operate normally.
也就是说，根据本公开内容的第二实施方式的沟槽型IGBT装置具有交替设置的彼此并联的正常的IGBT器件和常断的IGBT器件的元胞布置。因此，根据本公开内容的第二实施方式的沟槽型IGBT装置可以在不牺牲I-V特性的情况下保持小的饱和电流。此外，由于第二元胞20B中的IGBT器件是常断的，因此第二元胞20B中的IGBT器件中的栅极可被视为伪栅，从而还可以减少栅极电荷(Qg)。因此，在根据本公开内容的第二实施方式的沟槽型IGBT装置中无需再另外添加用于平衡短路电流和导通损耗之间的折衷关系的伪区，使得能够简化制造工艺并且减小芯片面积。That is, the trench IGBT device according to the second embodiment of the present disclosure has a cell arrangement of normal IGBT devices and normally-off IGBT devices which are alternately arranged in parallel with each other. Therefore, the trench IGBT device according to the second embodiment of the present disclosure can maintain a small saturation current without sacrificing I-V characteristics. In addition, since the IGBT devices in the second cell 20B are normally off, the gates in the IGBT devices in the second cell 20B can be regarded as dummy gates, thereby also reducing the gate charge (Qg). Therefore, there is no need to additionally add a dummy region for balancing the trade-off relationship between short-circuit current and conduction loss in the trench IGBT device according to the second embodiment of the present disclosure, so that the manufacturing process can be simplified and the chip size can be reduced area.
根据本公开内容的第二实施方式，通过调整第一元胞20A中的p+型接触区8的第三宽度WC3与n+型源极区7沿第二方向DR2的第四宽度WE4之间的比例关系，可以对沟槽型IGBT装置的I-V特性进行调整。According to the second embodiment of the present disclosure, by adjusting the ratio between the third width WC3 of the p+ type contact region 8 in the first cell 20A and the fourth width WE4 of the n+ type source region 7 along the second direction DR2 relationship, the I-V characteristics of the trench IGBT device can be adjusted.
根据本公开内容的第二实施方式，第一元胞20A和第二元胞20B沿第一方向DR1的长度可以是相同的。根据本公开内容的第二实施方式， 第一元胞20A和第二元胞20B沿第一方向DR1的长度可以是不同的。在第一元胞20A和第二元胞20B沿第一方向DR1的长度不同的情况下，通过调整第一元胞20A和第二元胞20B沿第一方向DR1的长度之间的比例关系，同样可以对沟槽型IGBT装置的I-V特性进行调整。According to the second embodiment of the present disclosure, the lengths of the first cell 20A and the second cell 20B along the first direction DR1 may be the same. According to the second embodiment of the present disclosure, the lengths of the first cell 20A and the second cell 20B along the first direction DR1 may be different. When the lengths of the first cell 20A and the second cell 20B along the first direction DR1 are different, by adjusting the proportional relationship between the lengths of the first cell 20A and the second cell 20B along the first direction DR1, The I-V characteristics of the trench IGBT device can also be adjusted.
用于制造根据本公开内容的第二实施方式的沟槽型IGBT装置20的方法与用于制造根据本公开内容的第一实施方式的沟槽型IGBT装置10的方法基本上相同，不同之处在于用于形成沟槽4的刻蚀掩模需要根据栅极G的形状变化进行调整，但是这并未增加额外的工艺步骤。The method for fabricating the trench IGBT device 20 according to the second embodiment of the present disclosure is substantially the same as the method for fabricating the trench IGBT device 10 according to the first embodiment of the present disclosure, except for the difference The fact is that the etching mask used to form the trench 4 needs to be adjusted according to the shape change of the gate G, but this does not add additional process steps.
根据本公开内容的沟槽型IGBT装置不需要复杂的版图设计并且可以以简化的常规半导体工艺步骤制备，从而能够降低制造成本。同时，根据本公开内容的沟槽型IGBT装置能够降低饱和电流，从而改善短路性能。此外，通过对沟槽型IGBT装置中的相关参数进行调整，可以容易地对沟槽型IGBT装置的I-V特性进行调整。The trench-type IGBT device according to the present disclosure does not require complicated layout design and can be fabricated with simplified conventional semiconductor process steps, so that the manufacturing cost can be reduced. Meanwhile, the trench IGBT device according to the present disclosure can reduce saturation current, thereby improving short-circuit performance. In addition, by adjusting the relevant parameters in the trench IGBT device, the I-V characteristics of the trench IGBT device can be easily adjusted.
尽管参照本公开内容的示例性实施方式描述了本公开内容，但是本领域技术人员将理解，在不偏离权利要求中阐述的本公开内容的精神和范围的情况下，可以进行各种修改和变化。Although the present disclosure has been described with reference to the exemplary embodiments thereof, those skilled in the art will appreciate that various modifications and changes can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims .

Claims (11)

  1. 一种绝缘栅双极型晶体管装置，包括：An insulated gate bipolar transistor device, comprising:
    第一导电类型的衬底；以及a substrate of the first conductivity type; and
    多个沟槽，从所述衬底的上表面向下形成以具有沿第一方向延伸的彼此平行的条形形状并且其中分别设置有多个栅极，其中，在所述沟槽之间形成有源区，并且所述有源区具有沿所述第一方向延伸的第一导电类型的源极区和第二导电类型的接触区，a plurality of trenches formed downward from the upper surface of the substrate to have strip shapes parallel to each other extending in a first direction and respectively disposed therein a plurality of gate electrodes, wherein the trenches are formed between the trenches an active region, and the active region has a source region of a first conductivity type and a contact region of a second conductivity type extending along the first direction,
    其特征在于，It is characterized in that,
    所述接触区具有在垂直于所述第一方向的第二方向上的第一宽度和不同于所述第一宽度的第二宽度，所述第一宽度和所述第二宽度沿所述第一方向交替布置，以及The contact area has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the second width along the first width. alternating in one direction, and
    所述多个栅极中的每个具有在所述第二方向上的均匀的第三宽度。Each of the plurality of gates has a third uniform width in the second direction.
  2. 根据权利要求1所述的绝缘栅双极型晶体管装置，其特征在于，The insulated gate bipolar transistor device of claim 1, wherein:
    所述有源区包括第一导电类型的载流子阻挡层和设置在所述载流子阻挡层上的第二导电类型的沟道层，以及the active region includes a carrier blocking layer of a first conductivity type and a channel layer of a second conductivity type disposed on the carrier blocking layer, and
    所述源极区和所述接触区设置在所述沟道层上。The source region and the contact region are disposed on the channel layer.
  3. 根据权利要求1所述的绝缘栅双极型晶体管装置，其特征在于，The insulated gate bipolar transistor device of claim 1, wherein:
    所述接触区的深度大于所述源极区的深度。The depth of the contact region is greater than the depth of the source region.
  4. 根据权利要求1所述的绝缘栅双极型晶体管装置，其特征在于，The insulated gate bipolar transistor device of claim 1, wherein:
    所述第二宽度大于所述第一宽度，以及the second width is greater than the first width, and
    具有所述第二宽度的接触区的第二绝缘栅双极型晶体管元胞的沟道掺杂浓度大于10 18cm -3，使得所述第二绝缘栅双极型晶体管元胞是常断的。 The channel doping concentration of the second IGBT cell having the contact region of the second width is greater than 10 18 cm −3 such that the second IGBT cell is normally off .
  5. 根据权利要求1所述的绝缘栅双极型晶体管装置，其特征在于包括：The insulated gate bipolar transistor device of claim 1, comprising:
    源极金属层，与所述源极区和所述接触区接触。a source metal layer in contact with the source region and the contact region.
  6. 根据权利要求1所述的绝缘栅双极型晶体管装置，其特征在于，在所述衬底的下表面上设置有第二导电类型的集电极层和第一导电类型的电场截止层。The insulated gate bipolar transistor device according to claim 1, wherein a collector layer of the second conductivity type and an electric field stop layer of the first conductivity type are provided on the lower surface of the substrate.
  7. 根据权利要求6所述的绝缘栅双极型晶体管装置，其特征在于包括：The insulated gate bipolar transistor device of claim 6, comprising:
    集电极金属层，与所述集电极层接触。a collector metal layer in contact with the collector layer.
  8. 根据权利要求1所述的绝缘栅双极型晶体管装置，其特征在于，The insulated gate bipolar transistor device of claim 1, wherein:
    所述第一导电类型是N型并且所述第二导电类型是P型。The first conductivity type is N-type and the second conductivity type is P-type.
  9. 一种绝缘栅双极型晶体管装置，包括：An insulated gate bipolar transistor device, comprising:
    第一导电类型的衬底；以及a substrate of the first conductivity type; and
    多个沟槽，从所述衬底的上表面向下形成以具有沿第一方向延伸的彼此平行的条形形状并且其中分别设置有多个栅极，其中，在所述沟槽之间形成有源区，并且所述有源区具有沿所述第一方向延伸的第一导电类型的源极区和第二导电类型的接触区，a plurality of trenches formed downward from the upper surface of the substrate to have strip shapes parallel to each other extending in a first direction and respectively disposed therein a plurality of gate electrodes, wherein the trenches are formed between the trenches an active region, and the active region has a source region of a first conductivity type and a contact region of a second conductivity type extending along the first direction,
    其特征在于，It is characterized in that,
    所述多个栅极中的每个具有在垂直于所述第一方向的第二方向上的第一宽度和不同于所述第一宽度的第二宽度，所述第一宽度和所述第二宽度沿所述第一方向交替布置，以及Each of the plurality of gates has a first width in a second direction perpendicular to the first direction and a second width different from the first width, the first width and the first width two widths are alternately arranged along the first direction, and
    所述接触区具有在所述第二方向上的均匀的第三宽度。The contact area has a uniform third width in the second direction.
  10. 根据权利要求9所述的绝缘栅双极型晶体管装置，其特征在于，The insulated gate bipolar transistor device of claim 9, wherein:
    所述第二宽度大于所述第一宽度，以及the second width is greater than the first width, and
    具有所述第二宽度的栅极的第二绝缘栅双极型晶体管元胞的沟道掺杂浓度大于10 18cm -3，使得所述第二绝缘栅双极型晶体管元胞是常断的。 The channel doping concentration of the second IGBT cell with the gate of the second width is greater than 10 18 cm -3 , so that the second IGBT cell is normally off .
  11. 一种制备绝缘栅双极型晶体管装置的方法，其特征在于包括：A method for preparing an insulated gate bipolar transistor device, comprising:
    从第一导电类型的衬底的上表面向下形成多个沟槽，使得所述多个沟槽具有沿第一方向延伸的彼此平行的条形形状；forming a plurality of trenches downward from the upper surface of the substrate of the first conductivity type such that the plurality of trenches have strip shapes extending in the first direction parallel to each other;
    在所述多个沟槽中分别设置多个栅极；以及Disposing a plurality of gates in the plurality of trenches, respectively; and
    使用同一掩模在所述沟槽之间形成的有源区的每个中形成第一导电类型的源极区和第二导电类型的接触区，使得所述接触区具有在垂直于所述第一方向的第二方向上的第一宽度和不同于所述第一宽度的第二宽度，所述第一宽度和所述第二宽度沿所述第一方向交替布置。A source region of the first conductivity type and a contact region of the second conductivity type are formed in each of the active regions formed between the trenches using the same mask such that the contact region has a direction perpendicular to the first conductivity type. A first width in a second direction of one direction and a second width different from the first width, the first widths and the second widths are alternately arranged along the first direction.
PCT/CN2021/091898 2021-03-29 2021-05-06 Insulated gate bipolar transistor device and manufacturing method therefor WO2022205556A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1879222A (en) * 2003-11-12 2006-12-13 丰田自动车株式会社 Trench gate field effect devices
CN1950947A (en) * 2004-05-12 2007-04-18 株式会社丰田中央研究所 Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1879222A (en) * 2003-11-12 2006-12-13 丰田自动车株式会社 Trench gate field effect devices
CN1950947A (en) * 2004-05-12 2007-04-18 株式会社丰田中央研究所 Semiconductor device

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