CN216871981U

CN216871981U - High-pressure-resistant silicon carbide device

Info

Publication number: CN216871981U
Application number: CN202220756934.8U
Authority: CN
Inventors: 王中健; 曹远迎
Original assignee: Chengdu Gongcheng Semiconductor Co ltd
Current assignee: Chengdu Gongcheng Semiconductor Co ltd
Priority date: 2022-04-01
Filing date: 2022-04-01
Publication date: 2022-07-01
Anticipated expiration: 2032-04-01

Abstract

The utility model discloses a high-pressure resistant silicon carbide device, which comprises: the silicon carbide epitaxial layer is provided with improved injection regions at intervals, and a blocking injection region and a source injection region are sequentially arranged above the silicon carbide epitaxial layer and the improved injection regions; a plurality of first grooves and second grooves which are arranged at intervals are etched on the injection improving region, the injection blocking region and the source electrode injection region; an oxide layer grows on the surface of the first groove, a grid polycrystalline silicon electrode is arranged on the oxide layer, and an insulating layer covers the grid polycrystalline silicon electrode; the second groove is provided with a polycrystalline silicon filling area; the source electrode injection region and the insulating layer are covered with the source electrode metal electrode, so that the problems of low reverse voltage and complex process in the prior art are solved.

Description

High-pressure-resistant silicon carbide device

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a high-voltage-resistant silicon carbide device.

Background

The silicon carbide has excellent high temperature resistance and heat conduction characteristic, can realize lower conduction loss when used as a wide bandgap material, and can meet various application requirements. The high critical field characteristics of silicon carbide materials enable silicon carbide power devices to have higher doping concentration and thinner drift layer thickness compared with conventional silicon devices under the same voltage, thereby realizing lower on-resistance. The silicon carbide MOSFET has low switching loss and high working frequency, and is very suitable for the application requirements of power electronics.

However, silicon carbide MOSFET devices suffer from low channel mobility due to the high interface state density at the gate oxide/silicon carbide interface. Meanwhile, due to the material characteristics of the silicon carbide device, deep ion implantation is difficult to realize, and serious lattice damage is easily caused. With the mature technology, the voltage platform required by the application market is higher and higher, and the withstand voltage structure design of the silicon carbide device in the prior art cannot meet the application of the power device under the future higher voltage condition.

SUMMERY OF THE UTILITY MODEL

The utility model provides a high-voltage-resistant silicon carbide device, which solves the problems of low reverse voltage and complex process in the prior art.

In order to solve the technical problem, the utility model provides the following technical scheme:

a high voltage resistant silicon carbide device comprising: the silicon carbide epitaxial layer is provided with improved injection regions at intervals, and a blocking injection region and a source injection region are sequentially arranged above the silicon carbide epitaxial layer and the improved injection regions; a plurality of first grooves and second grooves which are arranged at intervals are etched on the injection improving region, the injection blocking region and the source injection region;

an oxide layer grows on the surface of the first groove, a grid polycrystalline silicon electrode is arranged on the oxide layer, and an insulating layer covers the grid polycrystalline silicon electrode; the second groove is provided with a polycrystalline silicon filling area;

the source electrode injection region and the insulating layer are covered with a source electrode metal electrode.

Preferably, the doping types of the silicon carbide substrate, the silicon carbide epitaxial layer, the source electrode injection region, the grid polycrystalline silicon electrode and the improved injection region are a first conductivity type, and the doping types of the blocking injection region and the polycrystalline silicon filling region are a second conductivity type; the first conductivity type is N-type, and the second conductivity type is P-type.

Preferably, the doping types of the silicon carbide substrate, the silicon carbide epitaxial layer, the source electrode injection region and the grid polysilicon electrode are a first conductivity type, and the doping types of the blocking injection region and the polysilicon filling region are a second conductivity type; the first conductivity type is P-type and the second conductivity type is N-type.

Preferably, the back surface of the silicon carbide substrate is covered with a drain metal electrode.

Preferably, the thickness of the blocking injection region is 250-1500 nm.

Preferably, the improved implant region has a rectangular cross-section.

When the high-voltage resistant silicon carbide device works, the device can be started by applying positive voltage on the grid polycrystalline silicon electrode. Electrons enter from the source metal electrode, enter the device from the source injection region, form an electron channel on the interface of the blocking injection region and the oxidation layer, and form conduction through the silicon carbide epitaxial layer, the silicon carbide substrate and the drain metal electrode.

Compared with the prior art, the utility model has the following advantages:

the high-voltage resistant silicon carbide device disclosed by the utility model is based on the design of the grid groove and a plurality of voltage resistant structures, so that the on-resistance of the device can be reduced under the condition of keeping higher reverse voltage resistance. The discontinuous distribution of the injection region is improved, so that the conduction loss of the device can be further reduced on the premise of keeping the threshold voltage. Meanwhile, a plurality of structures are realized under one layer of photoetching plate, and the manufacturing cost is saved.

The utility model is a trench gate structure, and the channel mobility on the surface of the gate oxide of the trench gate is usually 2-3 times greater than that in a planar gate structure. In addition, the trench gate structure design of the present invention can achieve a smaller cell pitch than planar gate MOSFET structures that are currently dominant in the commercial production market. In combination with the advantages of reduced pitch and increased channel mobility, the on-resistance of the trench-gate MOSFET design is significantly reduced compared to conventional planar-gate MOSFET designs.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the utility model and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the utility model and together with the description serve to explain the principles of the utility model. In the drawings:

FIG. 1 is a schematic top view of the present invention with the insulating layer and source metal electrode omitted;

FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1 (including an insulating layer and a source metal electrode);

reference numbers and corresponding structural designations in the drawings:

101. a silicon carbide substrate; 102. a silicon carbide epitaxial layer; 103. a source injection region; 104. blocking the injection region; 105. an oxide layer; 106. a gate polysilicon electrode; 107. a polysilicon filling region; 108. an insulating layer; 109. a source metal electrode; 110. a drain metal electrode; 111. the implanted region is improved.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not used as limitations of the present invention.

Example 1

As shown in fig. 1-2, the first conductivity type is N-type, and the second conductivity type is P-type, for example, a high voltage resistant silicon carbide device includes: the silicon carbide epitaxial layer comprises a silicon carbide substrate 101 and a silicon carbide epitaxial layer 102 arranged on the silicon carbide substrate 101, wherein the doping concentration and type of the silicon carbide substrate 101 are N +, the doping concentration and type of the silicon carbide epitaxial layer 102 are N-, improved implantation regions 111 are arranged on the silicon carbide epitaxial layer 102 at intervals, and a blocking implantation region 104 and a source implantation region 103 are sequentially arranged above the silicon carbide epitaxial layer 102 and the improved implantation regions 111; the doping concentration and type of the improved implantation region 111 are N, and the cross section of the improved implantation region 111 is rectangular. The discontinuous distribution of the implantation region 111 is improved, so that the conduction loss of the device can be further reduced on the premise of keeping the threshold voltage.

The concentration and doping type of the blocking injection region 104 are P, and the thickness of the blocking injection region 104 is 250-1500 nm; the concentration and the doping type of the source electrode injection region 103 are N +, a plurality of first grooves and second grooves which are arranged at intervals are etched on the improved injection region 111, the blocking injection region 104 and the source electrode injection region 103;

an oxide layer 105 grows on the surface of the first groove, a grid polysilicon electrode 106 is arranged on the oxide layer 105, the concentration and doping type of the grid polysilicon electrode 106 are N +, and an insulating layer 108 covers the grid polysilicon electrode 106; the second trench is provided with a polysilicon filling region 107, the concentration and doping type of which are P +;

the source implantation region 103 and the insulating layer 108 are covered with a source metal electrode 109, and the back surface of the silicon carbide substrate 101 is covered with a drain metal electrode 110.

In this embodiment, the MOSFET is a normally-off MOSFET, and in a specific implementation, the device can be turned on by applying a positive voltage to the gate polysilicon electrode 106. Electrons enter from the source metal electrode 109, enter the device from the source injection region 103, form an electron channel at the interface between the blocking injection region 104 and the oxide layer 105, and make conduction through the silicon carbide epitaxial layer 102, the silicon carbide substrate 101, and the drain metal electrode 110.

Example 2

This example differs from example 1 in that: the first conductivity type is P-type, the second conductivity type is N-type, the doping types of the silicon carbide substrate 101, the silicon carbide epitaxial layer 102, the source implantation region 103, the gate polysilicon electrode 106 and the improved implantation region 111 are the first conductivity type, the doping types of the blocking implantation region 104 and the polysilicon filling region 107 are the second conductivity type, more specifically, the doping concentration and the type of the silicon carbide substrate 101 are P +, the doping concentration and the type of the silicon carbide epitaxial layer 102 are P-, the doping concentration and the type of the improved implantation region 111 are P, the doping concentration and the doping type of the blocking implantation region 104 are N, the doping concentration and the doping type of the source implantation region 103 are P +, the doping concentration and the doping type of the gate polysilicon electrode 106 are P +, and the polysilicon filling region 107 has N +.

In this embodiment, the MOSFET is a normally-off MOSFET, and in specific implementation, the device can be turned on by applying a negative voltage to the gate polysilicon electrode 106. Holes enter the device from the source metal electrode 109 and from the source injection region 103, a hole channel is formed at the interface between the blocking injection region 104 and the oxide layer 105, and conduction is established through the silicon carbide epitaxial layer 102, the silicon carbide substrate 101, and the drain metal electrode 110.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A high voltage resistant silicon carbide device comprising: the silicon carbide epitaxial layer structure comprises a silicon carbide substrate (101) and a silicon carbide epitaxial layer (102) arranged on the silicon carbide substrate (101), and is characterized in that improved implantation regions (111) are arranged on the silicon carbide epitaxial layer (102) at intervals, and a blocking implantation region (104) and a source implantation region (103) are sequentially arranged above the silicon carbide epitaxial layer (102) and the improved implantation regions (111); a plurality of first grooves and second grooves which are arranged at intervals are etched on the improved injection region (111), the blocking injection region (104) and the source injection region (103);

an oxide layer (105) grows on the surface of the first groove, a grid polycrystalline silicon electrode (106) is arranged on the oxide layer (105), and an insulating layer (108) covers the grid polycrystalline silicon electrode (106); the second trench is provided with a polysilicon filling region (107);

the source injection region (103) and the insulating layer (108) are covered with a source metal electrode (109).

2. The silicon carbide device with high voltage endurance as claimed in claim 1, wherein the doping types of the silicon carbide substrate (101), the silicon carbide epitaxial layer (102), the source implantation region (103), the gate polysilicon electrode (106) and the improvement implantation region (111) are of a first conductivity type, and the doping types of the blocking implantation region (104) and the polysilicon filling region (107) are of a second conductivity type; the first conductivity type is N-type, and the second conductivity type is P-type.

3. The silicon carbide device with high voltage resistance according to claim 1, wherein the doping types of the silicon carbide substrate (101), the silicon carbide epitaxial layer (102), the source implantation region (103) and the gate polysilicon electrode (106) are a first conductivity type, and the doping types of the blocking implantation region (104) and the polysilicon filling region (107) are a second conductivity type; the first conductivity type is P-type and the second conductivity type is N-type.

4. A high voltage resistant silicon carbide device according to claim 1 wherein the back side of the silicon carbide substrate (101) is covered with a drain metal electrode (110).

5. The silicon carbide device as claimed in claim 1, wherein the blocking implant region (104) has a thickness of about 250 nm and about 1500 nm.

6. A high voltage resistant silicon carbide device according to claim 1 wherein the modified implant region (111) is rectangular in cross-section.