TWI571959B - Power trench mosfet with mproved uis performance and preparation method thereof - Google Patents

Description

Trench type power semiconductor device with improved UIS performance and preparation method thereof

The present invention relates to a semiconductor device for a metal-oxide-semiconductor field-effect transistor (MOSFET) for power conversion, and more particularly, the present invention is directed to providing a better non-clamping power A trench power semiconductor device with switching capability of Unclamped Inductive Switching (UIS) optimizes the collapse breakdown capability of the trench power semiconductor device and provides a method of fabricating the device.

In power semiconductor devices, based on the transistor cell density and various other advantages, the gate can be formed in a trench extending downward from the surface of the semiconductor germanium substrate, a typical example being a trench metal oxide semiconductor. Field effect transistors (MOSFETs), others include, for example, trenched insulated gate bipolar transistors, etc., which have a common feature, which includes various types of trenches with various functions, but for the device itself. The characteristics of the structure, in some cases, the electric field strength at the bottom of many trenches shows the highest electric field level of the device, at the point where the voltage rises to the avalanche breakdown of the device, at the corner of the trench Collision ionization occurs during the breakdown and breakdown, and breakdown or breakdown occurs to generate a breakdown current. Abrupt breakdown generally leads to a hot carrier effect. When breakdown occurs near the gate oxide layer, a negative consequence is that hot carriers can be trapped and injected into the gate oxide layer, which can damage or break the gate. The oxide layer induces long-term reliability problems with power devices. In addition, such a groove It is often the limiting factor for devices to achieve high breakdown voltages.

Another problem is that if breakdown occurs in the termination region during a low current level burst breakdown, the device does not interfere with device performance, and the device does not need to worry about safe operation. However, during some special work periods, such as non-clamping inductive switching (UIS) switching, the current of the inductor in the circuit system does not change, causing the device to withstand some relatively large voltage strength, which is equivalent to the device being high. During a current level collapse breakdown event, a limited area of the termination area is likely to be unable to handle power loss safely and efficiently, because it is impossible for one power device to reduce the area of the effective transistor unit of the device and to infinitely allocate an excessive area to the termination area. The consequence is that the breakdown of the termination zone can affect the Safe Operating Area (SOA) of the device as a negative effect, which is something we don't expect to happen.

In view of the various difficult problems faced by the prior art, the present invention recognizes that it is necessary to limit the device to a safe working area (SOA) and to set the optimal non-clamping inductive switching (UIS) condition to readjust the distribution. The electric field strength of the device makes the power conversion device have better SOA and good UIS capability, so the present invention proposes various implementations in the subsequent content under this premise.

In one embodiment, the present invention provides a method of fabricating a trench power semiconductor device, comprising the steps of: providing a semiconductor substrate or substrate/substrate comprising a bottom substrate and an epitaxial layer over the underlying substrate Etching the epitaxial layer to form an annular isolation trench and an active trench inside the isolation trench, and an active-to-terminal transition region between the active trench and the isolation trench near the isolation trench Between an active region and a termination region; filling a conductive material into the isolation trench and preparing a gate in the active trench; depositing an insulating blunt The layer is overlying the semiconductor substrate; etching the insulating passivation layer and the mesa structure of the transition region and the active region, forming a first contact hole extending through the insulating passivation layer and extending downward into the active area mesa structure, and forming a through The insulating passivation layer extends downward to the second contact hole in the transition region mesa structure; the depth value and the width value of the first contact hole are respectively corresponding to the depth value and the width value of the second contact hole.

In the above method, the semiconductor substrate has a first conductivity type, and a dopant is implanted on top of the epitaxial layer to form a body layer of a second conductivity type before depositing the insulating passivation layer; and then at least in the body of the active region The top implant of the layer implants a top doped layer of a first conductivity type.

In the above method, in the step of forming the first and second contact holes, further comprising: covering a mask over the insulating passivation layer and forming at least the first and second openings in the mask; using the first opening While the first contact hole is etched, the second contact hole is also etched by the second opening, and the first opening is larger than the second opening.

In the above method, in the step of forming the first and second contact holes, further comprising: covering a first mask over the insulating passivation layer and forming at least a first opening in the first mask to the first opening Etching a first contact hole; after peeling off the first mask, covering a second mask over the insulating passivation layer and forming at least a second opening in the second mask, and etching the second opening to form a second contact hole The first opening has a larger opening size than the second opening.

In the above method, dopants having the same doping type as the bulk layer but having a higher doping concentration are implanted into the body layers of the transition region and the active region through the first and second contact holes to form a body contact region; Due to the smaller depth value and width value of the second contact hole relative to the first contact hole, the body contact area formed around the bottom of the second contact hole is formed around the bottom of the first contact hole The body contact area is shallower in depth and has a smaller diffusion range.

In one embodiment, the present invention provides a trench power semiconductor device comprising: a semiconductor substrate comprising a bottom substrate and an epitaxial layer over the underlying substrate; and an annular isolation trench disposed in the epitaxial layer And an active trench located inside the isolation trench, having an active-to-terminal transition region between an active trench and the isolation trench adjacent the isolation trench, between an active region and a termination region An insulating layer lining the isolation trench, the bottom and sidewalls of the active trench, and a conductive material disposed within the isolation trench, and a gate disposed within the active trench; a layer overlying the semiconductor substrate An insulating passivation layer; a first contact hole extending through the insulating passivation layer and extending into the active area mesa structure, a second contact hole extending through the insulating passivation layer and extending downward into the transition region mesa structure; the first contact hole The depth value and the width value are respectively corresponding to the depth value and the width value of the second contact hole.

In the above trench power semiconductor device, the metal plugs disposed in the first and second contact holes, and the metal plugs disposed in the contact holes of the conductive material in the insulating passivation layer aligned with the isolation trench are insulated and passivated The top metal electrode is electrically contacted over the active region, the transition region, and the isolation trench over the layer.

In the above trench power semiconductor device, the semiconductor substrate has a first conductivity type, a body layer of a second conductivity type is formed on top of the epitaxial layer, and a first conductivity type is formed at least on top of the body layer of the active region a top doped layer; wherein the first and second contact holes terminate within the body layer.

In the above trench type power semiconductor device, a body contact region of a second conductivity type is implanted around a bottom of the first and second contact holes; wherein a depth of the body contact region around the bottom of the second contact hole, a diffusion range, Correspondingly corresponding to the body around the bottom of the first contact hole The depth and diffusion range of the contact area should be small. During the transition of the device during the non-clamping inductive switching (UIS), when the breakdown breakdown occurs, the PN junction between the active region body layer and the epitaxial layer collapses and does not trigger the bottom corner of the isolation trench. Sudden breakdown.

In the above trench power semiconductor device, the gate disposed in the active trench includes a shield gate located in the lower portion of the active trench and a control gate located in the upper portion of the active trench, and is in the shield gate and the control An insulating layer is disposed between the gates to insulate them; the shield gate has the same potential as the conductive material in the isolation trench.

In another alternative embodiment, the present invention discloses a trench power semiconductor device comprising: a semiconductor substrate comprising a bottom substrate and an epitaxial layer over the bottom substrate; having a plurality of first a trench, and a first mesa disposed between adjacent first trenches and a second mesa disposed between the first trench and the second trench, wherein the first, second, and third trenches are epitaxial An upper surface of the layer extends into the epitaxial layer; a source region extending from the upper surface of the epitaxial layer to a first depth in the epitaxial layer, the source region having exactly the same conductivity type as the epitaxial layer Extending the entire width of the first mesa; providing a first body region extending downward from the bottom of the source region to a second depth in the epitaxial layer, the first body region having a conductivity type opposite to the epitaxial layer and extending a whole width of the first mesa; a second body region extending from the upper surface of the epitaxial layer to a third depth in the epitaxial layer, the second body region having a conductivity type opposite to the epitaxial layer and extending the second mesa of a width; a first contact hole extending from the upper surface of the epitaxial layer through the source region to the first body region, the first contact hole being filled with a conductive material; extending from the upper surface of the epitaxial layer to the second portion of the second body region The contact hole is filled with a conductive material; wherein the depth value and the width value of the first contact hole are respectively larger than the depth value and the width value of the second contact hole.

In the above trench power semiconductor device, the first trench is an active trench filled with a conductive material, and the conductive material in the first trench is insulated from the epitaxial layer and forms a trench gate.

In the above trench power semiconductor device, the second trench is filled with a conductive material, the conductive material in the second trench is insulated from the epitaxial layer, and the second trench forms an isolation trench.

In the above trench power semiconductor device, the third depth and the second depth have the same depth.

In the above trench power semiconductor device, the body conductive type doped region or the body contact region disposed at the bottom of the first contact hole is further included, and the doping concentration thereof is higher than the doping concentration of the first body region.

The trench power semiconductor device further includes a body conductive type doped region or a body contact region disposed at a bottom of the second contact hole, the doping concentration of which is higher than a doping concentration of the second body region.

In the above trench power semiconductor device, the third trench surrounds the first and second trenches.

In the above trench type power semiconductor device, the conductive material filling the first contact hole is electrically connected to the conductive material filling the second contact hole.

In the above trench type power semiconductor device, the third trench which is a termination trench is filled with a conductive material, and the conductive material in the third trench is insulated from the epitaxial layer.

The trench power semiconductor device further includes a third contact hole disposed in a body region at the top of the epitaxial layer outside the third trench, wherein the third contact hole is filled with a conductive material The material is electrically connected to the conductive material filling the third trench.

100‧‧‧Bottom substrate

101‧‧‧Terminal trench

101a, 102a‧‧‧ conductive materials

101b, 102b‧‧‧ insulation

102‧‧‧Isolation trench

103‧‧‧Active trench

103a‧‧‧Shield gate

103b~103d‧‧‧Insulation

103e‧‧‧Control gate

103-1‧‧‧Active trench

110‧‧‧ Epilayer

120‧‧‧ body layer

125‧‧‧ edge

130‧‧‧Top doped layer

140‧‧‧Insulation passivation layer

200‧‧‧ terminal area

250‧‧‧Transition zone

250a‧‧‧ countertop structure

300‧‧‧Active area

300a‧‧‧ countertop structure

400‧‧‧ mask

400a~400e‧‧‧ openings

401‧‧‧ first mask

402‧‧‧second mask

501~505‧‧‧Contact hole

504a‧‧‧ contact hole 504 extending into the semiconductor substrate

504’‧‧‧Contact hole

505a‧‧‧ contact hole 505 extending into the semiconductor substrate

555‧‧‧Metal embolism

601, 601', 602‧‧ ‧ body contact area

611‧‧‧Metal field plate

612‧‧‧Top metal electrode

613‧‧‧Bottom metal electrode

700,700’‧‧‧Crash current

Figure 1 is a partial top plan view of the device of the present invention including termination trenches, isolation trenches, and active trenches.

2A~2J are schematic flow diagrams of a method for fabricating a trench MOSFET device.

Figures 3A-3B are based on the steps of Figures 2A-2J but using two masks to make contact holes of different depths and widths.

Fig. 4A shows the general electric field strength near the corner of an isolation trench at the same width and depth of the contact hole between the terminal region and the active region interface and the contact hole of the active region.

Fig. 4B is a schematic view showing the flow of the collapse current at the corner of the isolation trench at the junction of the terminal region to the active region interface in the structure of Fig. 4A.

Figure 5A shows the approximate electric field strength near the corner of an isolation trench at the interface between the contact hole of the termination region and the active region interface and the contact hole of the active region at different widths and depths.

Fig. 5B is a schematic view showing the flow of the collapse current at the time of the collapse breakdown at the corner of the isolation trench at the termination region to the active region interface in the structure of Fig. 5A.

In FIG. 2A, in a trench MOSFET device, a semiconductor substrate includes a heavily doped underlying substrate 100, and an epitaxial layer 110 including a relatively lower doping concentration relative to the underlying substrate 100. The conductivity doping type is the same, the subsequent content is N+ bottom lining The epitaxial layer 110 of the bottom 100 and N- is illustrated as an example. The epitaxial layer 110 is etched by a mask having an opening pattern, not shown in the figure, to form a termination trench 101, an isolation trench 102, and a recess extending downward from the upper surface of the epitaxial layer 110, respectively. A plurality of active trenches 103 whose bottoms terminate in epitaxial layer 110. For a more detailed understanding of the layout between the various trenches, in the top view of FIG. 1, a partial view of a semiconductor substrate of a single wafer having an edge 125 indicated by a dashed line and a semiconductor substrate The inner side of the annular isolation trench 102 is formed with a plurality of active trenches 103 in the semiconductor substrate, outside the isolation trench 102 is the termination region 200 of the semiconductor substrate, and the termination region 200 surrounds the isolation trench 102, and An annular termination trench 101 is formed in the termination region 200 adjacent the edge 125.

In FIG. 2B, an insulating layer 101b is formed on the sidewalls and the bottom of the termination trench 101, and an insulating layer 102b is formed on the sidewalls and the bottom of the isolation trench 102, and at the sidewall and bottom of each active trench 103. An insulating layer 103b is formed, and these insulating layers 101b, 102b, 103b may be formed simultaneously, for example, a cerium oxide layer grown by a thermal oxidation process. In the steps of FIGS. 2B-2C, it is necessary to fill a conductive material inside each trench, for example, filling the doped polysilicon material into the termination trench 101, the isolation trench 102, and the active trench 103. However, it is necessary to perform an etch back of the conductive material on the upper portion of each active trench 103 for removal, and only the conductive material of the lower portion of each active trench 103 is reserved to form a shield gate (Shield Gate; SG 103a, thereafter, an insulating material such as SiO2 is prepared by low pressure chemical vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition (PECVD), and is filled in the active trench 103. The upper portion is covered in the gap space formed by removing the conductive material to cover the shield gate 103a. And then etch back the insulating material in the gap space and the original insulating layer 103b of the upper sidewall of the active trench 103, remove them, and only remain above the shield gate 103a. An insulating layer 103c. Thereafter, a dense insulating layer 103d such as SiO2 is formed as a gate oxide layer on the sidewall of the upper portion of the active trench 103, and a conductive material is refilled in the gap space in the upper portion of each active trench 103 to prepare a control. Gate 103e. In the active trench 103, the insulating layer 103d as the gate oxide layer is thinner than the insulating layer 103b remaining on the sidewall of the lower portion of the active trench 103, and the control gate 103e overlaps the shield gate 103a, but They are electrically insulated from each other by the insulating layer 103c therebetween. The control gate 103e serves as an effective gate electrode of the MOSFET transistor unit, but each of the shield gates 103a is coupled to the source electrode of the MOSFET and is equipotential with the source, so that the parasitic between the gate and the drain can be appropriately reduced. Capacitor Cgd.

In FIG. 2C, field effect transistor units are formed in the active region 300, and the active trench 103 serves as a MOSFET transistor unit or a gate trench of the unit cell, and is prepared in the active region 300 of the semiconductor substrate. One such active trench 103. There is an active-to-terminal transition region 250 between an active trench 103-1 and the isolation trench 102 near the isolation trench 102, the transition region 250 of the semiconductor substrate Between the active area 300 and the terminal area 200, in many cases, the transition area 250 can also be considered to function as a terminal structure. In order to distinguish, in all of the active trenches 103, the active trenches 103-1 are defined as the outermost trenches of all of the active trenches 103 arranged side by side, and also closest to the isolation trenches 102. A portion parallel to the active trench 103, the region between the outermost active trench 103-1 and the isolation trench 102 is defined as a transition region 250. As can be seen from Figures 1 and 2C, on the inside of the isolation trench 102, in addition to the active region 300, there is a transition region 250.

2A~2C are only exemplarily given to the method of preparing the filling material in the corresponding trench or controlling the gate and shielding gate, but in fact, the structure of the 2C figure is prepared, and the method is not unique, and Many implementations can be implemented, and considering these steps is not the heaviest of the present invention. The content is required, so it is only a rough introduction.

The isolation trench 102 and the active trench 103-1 adjacent thereto define a mesa structure (Mesa) 250a between the semiconductor substrates, and any adjacent active trenches 103 define adjacent two A mesa structure 300a of the semiconductor substrate between the source trenches 103.

In FIG. 2D, a body layer 120 and a top doped layer 130 are prepared, wherein the top doped layer 130 is embodied or formed in the active region 300 as a source region of the transistor unit. For example, in a blanket implant, a P-type dopant ion is implanted on top of the entire epitaxial layer 110 to prepare a P-type body layer 120 on top of the epitaxial layer 110, surrounding the trenches. Around the upper side wall. Thereafter, an N+ type dopant ion is then implanted onto the top of the body layer 120 of the active region 300, and an N+ type top doped layer 130 is prepared on top of the body layer 120 of the active region 300, surrounding Around the upper sidewall of the active trench 103, in the illustrated embodiment, the doped layer 130 is implanted only within the mesa structure 300a, but not within the mesa structure 250a outside the active trench 103-1. The doped layer 130 is implanted. Note that the implantation depth of the body layer 120 is to ensure that its interface with the epitaxial layer 110 near the active trench 103 is slightly higher than the bottom surface of the control gate 103e so as to be along the active trench in the body layer 120. The sidewalls of 103 form a vertical inversion layer to establish the channel. Although not specifically explained, it should be understood that ion implantation is also often accompanied by a step of annealing diffusion. Although in the embodiment of FIG. 2D, only the top doped layer 130 is formed in the body layer 120 of the active region 300, the doped layer 130 is not formed on the top of the bulk region 120 of the transition region 250 and the termination region 200, but In some other optional embodiments, the top doping layer 130 may be formed together at the top of the body layer 120 of the transition region 250 and the termination region 200 in a holistic manner. In this case, no ion implantation step is required. An extra mask is used in the middle.

In FIG. 2E, an insulating passivation layer 140 is deposited over the semiconductor substrate, The upper surface of the epitaxial layer 110 is covered while also overlying the termination trenches 101, the isolation trenches 102, and the active trenches 103. The insulating passivation layer 140 is typically prepared, for example, by depositing a low temperature oxide (LTO) and/or a boronic acid containing barium glass (BPSG). In FIG. 2F, a plurality of masks 400 are overlaid on the insulating passivation layer 140, such as a photoresist layer or photoresist, and after exposure and development by known photolithography techniques, a plurality of layers are prepared in the mask 400. Openings (400a~400e). In these openings, the opening 400a is aligned with the partial body layer 120 outside the termination trench 101 of the termination region 200, the opening 400b is aligned with the conductive material 101a filled in the termination trench 101, and the opening 400c is aligned with the isolation trench 102. The inner conductive material 102a is filled, the opening 400d is aligned with the mesa structure 250a, and the opening 400e is aligned with the mesa structure 300a. Moreover, openings for some other functions in the mask 400 are not shown, such as openings for aligning the gate material filled in the gate pickup.

One aspect of the present invention resides in that the size of the opening 400e is made larger than the size of the opening 400d. For convenience of distinction, the opening 400e may sometimes be referred to as a first opening and the opening 400d as a second opening.

In FIG. 2G, a contact hole is prepared by anisotropic dry etching using the mask 400 as an etch mask, and the insulating passivation layer 140 and the semiconductor substrate are sequentially etched downward, and etching is terminated in the body layer 120. With the opening 400d, the contact hole 504 forming the mesa structure 250a of the alignment region is etched, and the contact hole 505 of the active region mesa structure 300a is etched by the opening 400e. For convenience of distinction, the contact hole 505 may be referred to as a first contact hole, the contact hole 504 is defined as a second contact hole, and the contact hole 501 is defined as a third contact hole.

The prepared contact hole 504 extends through the insulating passivation layer 140 and into the mesa structure 250a and terminates within the body layer 120 of the transition region mesa structure 250a. The prepared contact hole 505 penetrates through the insulating passivation layer 140 and extends into the mesa structure 300a and penetrates the top doped layer of the active region 130 and terminate within the body layer 120 of the active area mesa structure 300a. Since the opening 400e is larger than the opening size of the opening 400d, the etching rate of the material exposed under the opening 400e is much faster than the etching rate of the material under the opening 400d, and the faster etching rate can further form deeper contact. hole. Therefore, in the etching step of the contact hole, two effects are generated, one of which is that the depth value of the active region contact hole 505 is larger than the depth value of the transition region contact hole 504, and the second is the width value of the contact hole 505 or The transverse cross-sectional dimension is larger than the width value or lateral cross-sectional dimension of the contact hole 504. As can be seen from the 2G diagram, the portion 505a of the contact hole 505 extending into the semiconductor substrate is much deeper than the portion 504a of the contact hole 504 extending into the semiconductor substrate.

In the etching step in the FIG. 2G, the contact holes 501, 502, 503 and the like are also formed by synchronous etching. The contact hole 501 is formed by etching using the opening 400a, the contact hole 502 is formed by etching using the opening 400b, and the contact hole 503 is formed by etching using the opening 400c. Since the opening 400a is located above the local body layer 120 outside the termination trench 101, the formed contact hole 501 penetrates the insulating passivation layer 140 and extends into the body layer 120 in the termination region 200 outside the termination trench 101, if terminated The top doped layer 130 is also implanted on top of the body layer 120 outside the trench 101, and the contact hole 501 also penetrates the top doped layer 130 there. In addition, the contact hole 502 penetrates the insulating passivation layer 140 and exposes the conductive material 101a filled in the termination trench 101. The contact hole 503 penetrates the insulating passivation layer 140 and exposes the conductive material 102a filled in the isolation trench 102.

In Figure 2H, in order to form the body contact regions of the contact holes at the bottom of the active and transition regions, an ion implantation step is performed in which ion implantation or P-type dopants are implemented in a self-aligned manner. The implanted ions are of the same conductivity type as the body layer 120, but are larger than the doping concentration of the body layer 120, and are of the P+ type. The ions implanted in the body layer 120 of the transition region 250 through the contact holes 504 form a body contact region 601 in the mesa structure 250a, which is located at the bottom of the contact hole 504 Around the ministry. The ions implanted in the body layer 120 of the active region 300 through the contact holes 505 form a body contact region 602 in the mesa structure 300a that is located around the bottom of the contact hole 505. Ion implantation is also often accompanied by a step of annealing diffusion. Since the width dimension of the contact hole 505 is larger than the width dimension of the contact hole 504, the total amount of ions injected from the contact hole 505 is also much larger than the total amount of ions injected from the contact hole 504, thereby causing the body contact region 602. The diffusion range is larger than the diffusion range of the body contact region 601, in other words, finally, the volume of the body contact region 602 is larger than the volume of the body contact region 601. In addition, since the portion of the contact hole 504 extending into the substrate itself is relatively shallow, it is apparent that the body contact region 601 at the bottom of the contact hole 504 is naturally deeper than the body contact region 602 at the bottom of the contact hole 505 in the semiconductor substrate. It is much shallower.

In FIG. 2I, in some embodiments, a barrier metal layer is often deposited on the bottom and sidewalls of each of the contact holes 501-505 and on the upper surface of the insulating passivation layer 140, and then a metal material not shown is deposited. (such as tungsten) is overlaid on the barrier metal layer, and a part of the metal material is also simultaneously filled in the respective contact holes 501 to 505, after which the etched metal material removes part of the metal material above the insulating passivation layer 140, but retains each contact The barrier metal layer and the filled metal material in the holes 501 to 505 can form a metal plug 555 or a metal joint.

In FIG. 2J, a metal layer not shown in the figure is prepared and deposited over the entire insulating passivation layer 140. If a barrier metal layer is previously deposited on the upper surface of the insulating passivation layer 140, the metal layer is substantially covered by the potential. Above the metal layer. They are then patterned to divide the metal layer and the barrier metal layer beneath it to form a metal field plate 611 and a top metal electrode 612 that are disconnected and electrically isolated. Further, another metal layer is additionally covered on the bottom surface of the underlying substrate 100 as the bottom metal electrode 613, which forms an ohmic contact with the heavily doped underlying substrate 100. A field plate 611 over the insulating passivation layer 140 is disposed in the termination region 200, to It is less likely to overlap the termination trench 101 and overlap the contact hole 501 so as to be in electrical contact with the metal plug 555 in the contact hole 501 and the metal plug 555 in the contact hole 502, so that the terminal region 200 is located. The body layer 120 outside the termination trench 101 is electrically connected to the conductive material 101a filled in the termination trench 101 at the same potential. If the top of the body layer 120 outside the termination trench 101 is implanted with the top doped layer 130, the top doped layer 130 there is also shorted to the metal plug 555 in the contact hole 501, thereby terminating the trench The conductive material 101a in 101 is in place. The termination trench 101 serves as a channel stop structure.

In addition, top metal electrode 612 over insulating passivation layer 140 is disposed at least in transition region 250 and active region 300 and overlaps at least over isolation trench 102 and overlying mesa structures 250a, 300a. In this case, the metal plug 555 in the contact hole 503 electrically connects the conductive material 102a filled in the isolation trench 102 to the top metal electrode 612, and the metal plug 555 in the contact hole 504 connects the body layer of the transition region 250. 120 is electrically connected to the top metal electrode 602. The metal plug 555 in the contact hole 505 shorts the top doping layer 130 and the body layer 120 as the source regions in the active region 300, and further electrically connects the source region and the body layer 120 to the top metal electrode 612. on. It should be noted that in an optional non-essential embodiment, the strip-shaped active trench 103 may be in communication with a portion of the isolation trench 102 perpendicular to the active trench 103 in an unillustrated dimension so that The shield gate 103a in the lower portion of each active trench 103 is interconnected with the conductive material 102a filled in the isolation trench 102, so it is also electrically connected to the top metal electrode 612. However, the control gate 103e is insulated from the conductive material 102a filled in the isolation trench 102 and is not interconnected. In the unillustrated dimension, the upper control gates 103e of all active trenches 103 are connected to each other and connected to the gate material filled in the gate pick-up trenches, and some contact holes are aligned. The pole picks up the gate material filled in the trench, and a metal plug can be disposed inside the gate, and the gate 103e is controlled It is led onto the gate metal above the insulating passivation layer 140.

Since the top metal electrode 612 serves as the source of the MOSFET device and the bottom metal electrode 613 serves as the drain of the MOSFET device, the body layer 120 including the transition region and the active region inside the isolation trench 102, and the top portion of the active region 300 are doped. The impurity layer 130 is all equipotential to the source (if the transition region 250 has the top doped layer 130, it is also equiaxed with the source), the shielding gate 103a and the conductive material 102a filled in the isolation trench 102 are also connected to the source, etc. Bit.

In the embodiment of FIGS. 3A-3B, the opening 400e (first opening) for etching the contact hole 505 and the opening 400d (second opening) for etching the contact hole 504 are not formed on the same mask. . For example, the first mask 401 may be coated on the insulating passivation layer 140, and the opening 400e in the first mask 401 is formed first, and other openings 400a, 400b, 400c are formed in synchronization, but the opening 400d is not formed. First, the insulating layer 101 and the semiconductor substrate are sequentially etched by the openings 400a, 400b, 400c, and 400e, and the contact holes 501, 502, 503, and 505 are respectively formed correspondingly, and then the first mask 400 is peeled off. Thereafter, another second mask 402 is coated on the insulating passivation layer 140, and an opening 400d is formed in the second mask 402, and the underlying insulating layer 101 and the semiconductor substrate are sequentially etched by the opening 400d to form a contact hole 504. The features of the contact holes 501 to 505 are identical to those of the previous embodiment, and the only difference is that the etching preparation timing is changed.

In addition, in another embodiment not illustrated, the openings 400a, 400b, 400c, 400d may be formed in the first mask 401 to prepare the contact holes 501, 502, 503, 504, and then the first mask is peeled off. 401. A contact hole 505 is then formed by forming an opening 400e in the second mask 402.

Without being limited thereto, it is also possible to select not to form the openings 400a, 400b, 400c in the first mask 401, but to form the openings 400a, 400b, 400c in the second mask 402. First in the first An opening 400e is formed in a mask 401, and after the contact hole 505 is prepared, the first mask 401 is peeled off. Contact openings 501, 502, 503, 504 are then formed by forming openings 400a, 400b, 400c, 400d in second mask 402. Alternatively, the opening 400d is first formed in the first mask 401, and after the contact hole 504 is prepared, the first mask 401 is peeled off. Contact openings 501, 502, 503, 505 are then formed by forming openings 400a, 400b, 400c, 400e in second mask 402.

In summary, any manner is suitable for the present invention as long as it is ensured that the opening 400e has a larger opening size than the opening 400d, thereby making the contact hole 505 deeper and wider than the contact hole 504.

In FIG. 4A, according to the prior art, it is assumed that the portion of the contact hole 504' extending into the mesa structure 250a has a depth D'1 in the semiconductor substrate, and it is assumed that the contact hole 505 extending into the mesa structure 300a is in the semiconductor lining. The portion in the bottom has a depth D2, D'1 = D2. In the UIS load application of the device, the potential of the bottom metal electrode 613 is much higher than the top metal electrode 612, especially during switching events of the device under Unclamped Inductive Switching (UIS). For a detailed understanding of the electric field distribution within the device, a general schematic of the isoelectric field strength at the bottom corners of the isolation trench 102 and the active trench 103 is depicted in FIG. 4A, not only the electric field strength at the bottom corner of the isolation trench 102 is far Far more powerful than the field at the PN junction between the body layer 120 of the active region 300 and the epitaxial layer 110, and the electric field strength at the bottom corner of the isolation trench 102 is also greater than the electric field strength at the bottom corner of the active trench 103. To be large, the bottom corner of the isolation trench 102 will be a major break-through breakdown, which is a bad phenomenon. The breakdown voltage of the transition region 250 is lower than the breakdown voltage of the active region 300, and the high voltage collapse breakdown will occur at the high electric field strength position at the bottom corner of the isolation trench 102 of FIG. 4A, and the breakdown current will flow into the transition region 250. The flow of the collapse current 700 induced near the corner of the bottom of the isolation trench 102 as shown in FIG. 4B, thereby impairing the breakdown resistance performance of the device. In the UIS event, the limited area of the transition zone 250 is difficult to handle. Rate loss, which seriously affects the safe working area of the device SOA.

In FIG. 5A, in accordance with the present invention, the portion 504a of the contact hole 504 extending into the mesa structure 250a has a depth D1 in the semiconductor substrate, and the portion of the contact hole 505 extending into the mesa structure 300a has a portion in the semiconductor substrate. Depth D2, at this time D1 < D2. In the UIS load application of the device, the equal electric field strength at the bottom corner of each of the isolation trench 102 and the active trench 103 and the field strength at the PN junction between the bulk layer 120 of the active region 300 and the epitaxial layer 110 are generally Depicted in Figure 5A. In the body layer 120, the body contact region 601 around the bottom of the contact hole 504 appears to be smaller in volume and shallower in depth than the body contact region 602 around the bottom of the hole 505. 5A shows the electric field strength at the bottom corner of each of the isolation trench 102 and the active trench 103, and the PN junction between the bulk layer 120 and the epitaxial layer 110 in the active region 300, as compared with the case of FIG. 4A. The field strength has changed. It is embodied that the probability of the weakened electric field intensity induced collapse of the isolation trench 102 and the bottom corner of the active trench 103 can be almost completely ignored. Instead, the interface between the body layer 120 and the epitaxial layer 110 in the active region 300 is The PN junction produces the highest vertical electric field at the center of the mesa structure 300a. This central position is also substantially the center position between the adjacent two active trenches 103, and the electric field strength there is greater than the isolation trench 102. The electric field strength at the bottom corner of the source trench 103 is much greater. Therefore, in FIG. 5A, during the switching event of the UIS, the interface between the body layer 120 of the active region and the epitaxial layer 110 (PN junction) is located at the center between the adjacent active trenches 103. The main crash weakness, the bottom corner of the isolation trench 102 will no longer be a breakdown breakdown, causing the bulk-epitaxial PN junction in the active region 300 to trigger a breakdown first, so Figure 5B and 4A In contrast, the high voltage sag breakdown is no longer occurring at the bottom corner of the isolation trench 102. Figure 5B shows the flow tendency of the collapse current 700' induced at the PN junction between the body-epitaxial layer of the active region after high voltage abrupt breakdown. Can be informed that the original 250 in the transition zone with a limited area The current is transferred to the active area 300 having a larger area. This prevents hot carriers generated from the collapsed region from being trapped by the insulating layer 102b, preventing damage to the insulating layer 102b at the bottom of the isolation trench 102, and more importantly, improving the trench MOSFET device due to the transfer of the breakdown current. Rugged. Therefore, it is very necessary to design the contact hole depth of the appropriate transition region and active region, and change the depth position of the body contact region, appropriately change the electric field distribution, and maximize the breakdown voltage of the power MOSFET to improve the UIS of the trench MOSFET. Performance, the inventive spirit of the present invention just meets these requirements.

In the embodiment of FIGS. 5A-5B, it can be learned that the interface between the body layer 120 having the transition region (having the contact hole 504) and the epitaxial layer 110 is still horizontal, whereas the active region (having the contact hole 505) The interface between the body layer 120 and the epitaxial layer 110 is slightly recessed downward, which is largely due to the P-type dopant diffusion of the body contact region 602 causing the body layer 120 to bulge downward. The P-type dopant diffuses the deepest at the center position between the adjacent two active trenches 103, that is, at this center, the body layer 120 extends downward to protrude the deepest. In other words, although the transition region body-epitaxial layer PN junction is still a parallel plane junction, the active region body-epitaxial layer PN junction is no longer an ideal parallel plane junction. Instead, the contour is essentially a curved curved junction. The electric field is more likely to accumulate there, and breakdown or collapse is more likely to occur.

The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and modifications Any and all equivalent ranges and contents within the scope of the claims are considered to be within the spirit and scope of the invention.

100‧‧‧Bottom substrate

110‧‧‧ Epilayer

140‧‧‧Insulation passivation layer

200‧‧‧ terminal area

300‧‧‧Active area

601‧‧‧ Body contact area

602‧‧‧ Body contact area

611‧‧‧Metal field plate

612‧‧‧Top metal electrode

613‧‧‧Bottom metal electrode

Claims (20)

A method of fabricating a trench power semiconductor device, comprising the steps of: providing a semiconductor substrate comprising a bottom substrate and an epitaxial layer over the underlying substrate; etching the epitaxial layer to form an annular isolation trench and a plurality of active trenches located inside the isolation trench, an active-to-terminal transition region between the active trench adjacent the isolation trench and the isolation trench, between an active region and a Between the terminal regions; filling a conductive material into the isolation trench, and preparing a gate in the active trenches; depositing an insulating passivation layer over the semiconductor substrate; and etching the insulating passivation layer and the transition a mesa structure of the active region, forming a first contact hole extending through the insulating passivation layer and extending downward into the mesa structure of the active region, and extending through the insulating passivation layer to the lower portion a second contact hole in the mesa structure of the transition region; wherein the depth value and the width value of the first contact hole are respectively greater than the depth value and the width value of the second contact hole; Body layer, and the second contact hole and a bottom of the first contact hole extends to the body layer. The method of claim 1, wherein the semiconductor substrate has a first conductivity type, and a dopant is implanted on top of the epitaxial layer to form a second conductive layer before depositing the insulating passivation layer. The body layer of the type; and subsequently implanting a dopant at least on top of the body layer of the active region to form a top doped layer that is the first conductivity type. The method of claim 2, further comprising the steps of: respectively, through the first contact hole and the second contact hole, to the transition region and the active region Doping a dopant having the same doping type as the bulk layer but having a higher doping concentration from the body layer to form a body contact region; wherein the second contact hole has a smaller size relative to the first contact hole The depth value and the width value are such that the body contact region formed around the bottom of the second contact hole has a shallower depth and a smaller diffusion range than the body contact region formed around the bottom of the first contact hole. The method of claim 1, wherein in the step of forming the first contact hole and the second contact hole, the method further comprises the steps of: covering a mask over the insulating passivation layer, and at least Forming a first opening and a second opening in the mask; and etching the first contact hole by using the first opening, and simultaneously etching the second contact hole by using the second opening, the first The opening is larger than the size of the second opening. The method of claim 1, wherein in the step of forming the first contact hole and the second contact hole, the method further comprises the step of: covering a first mask over the insulating passivation layer Forming at least a first opening in the first mask, and etching the first contact hole by the first opening; and after peeling off the first mask, covering a second mask over the insulating passivation layer Forming at least a second opening in the second mask, and etching the second contact hole by the second opening; wherein the first opening has a larger opening size than the second opening. A trench power semiconductor device comprising: a semiconductor substrate comprising a bottom substrate and an epitaxial layer over the underlying substrate; an isolation trench disposed in the epitaxial layer and an isolation trench a plurality of active trenches on the inner side, an active trench adjacent the isolation trench and an active trench between the isolation trench a transition region to the terminal between an active region and a termination region; an insulating layer lining the isolation trench, the bottom and sidewalls of the active trenches, and a conductive material disposed in the isolation trench And a gate disposed in the active trenches; an insulating passivation layer overlying the semiconductor substrate; and a first layer extending through the insulating passivation layer and extending down to a mesa structure of the active region a contact hole extending through the insulating passivation layer and extending to a second contact hole in a mesa structure of the transition region; wherein a depth value and a width value of the first contact hole are respectively corresponding to the second contact hole a depth value and a width value; a body layer is formed in the semiconductor substrate, and a bottom of the first contact hole and the second contact hole extends into the body layer. The trench type power semiconductor device according to claim 6, wherein a metal plug provided in the first contact hole and the second contact hole is disposed in the insulating passivation layer to align the isolation trench A metal plug in the contact hole of the conductive material in the trench is in electrical contact with a top metal electrode overlying the active passivation layer, the transition region and the isolation trench. The trench power semiconductor device of claim 6, wherein the semiconductor substrate has a first conductivity type, a body layer of a second conductivity type is formed on top of the epitaxial layer, and at least A top doped layer of the first conductivity type is formed on a top portion of the body layer of the active region; and the first contact hole and the second contact hole terminate in the body layer. The trench type power semiconductor device of claim 8, wherein a body contact region of a second conductivity type is implanted around a bottom of the first contact hole and the second contact hole, respectively; The depth and diffusion range of the body contact area around the bottom of the contact hole Correspondingly, the depth and the diffusion range of the body contact region around the bottom of the first contact hole are smaller. The trench power semiconductor device according to claim 6, wherein the gates disposed in each of the active trenches include a shield gate located at a lower portion of each of the active trenches and are located at each Controlling gates in the upper portion of the active trenches, and an insulating layer between the shielding gates and the control gates to insulate them; and the shielding gates and the conductive material in the isolation trenches have The same potential. A trench power semiconductor device comprising: a semiconductor substrate comprising a bottom substrate and an epitaxial layer over the underlying substrate; a first mesa disposed between adjacent first trenches and a first trench a second mesa between the trench and the second trench, wherein the first, the second and a third trench extend from the upper surface of the epitaxial layer into the epitaxial layer; the first mesa is disposed from the An upper surface of the epitaxial layer extends to a source region of a first depth in the epitaxial layer, the source region having the same conductivity type as the epitaxial layer and extending the entire width of the first mesa; a mesa extending downward from a bottom of the source region to a first body region of a second depth of the epitaxial layer, the first body region having a conductivity type opposite the epitaxial layer and extending the entire first mesa a second body region disposed on the second mesa extending from an upper surface of the epitaxial layer to a third depth of the epitaxial layer, the second body region having a conductivity type opposite to the epitaxial layer and extending the The entire width of the second mesa; from Upper surface of the epitaxial layer through the source region extends a first contact hole reaching the first body region, the first contact hole is filled with a conductive material; And extending from the upper surface of the epitaxial layer to a second contact hole of the second body region, wherein the second contact hole is filled with a conductive material; wherein a depth value and a width value of the first contact hole are respectively greater than the first The depth value and width value of the two contact holes. The trench power semiconductor device of claim 11, wherein the first trench is filled with a conductive material, and a conductive material in the first trench is insulated from the epitaxial layer and forms a trench gate. The trench power semiconductor device of claim 12, wherein the second trench is filled with a conductive material, and the conductive material in the second trench is insulated from the epitaxial layer and forms an isolation trench. The trench power semiconductor device of claim 11, wherein the third depth and the second depth have the same depth. The trench power semiconductor device of claim 14, further comprising a body conductive type doped region disposed at a bottom of the first contact hole and having a higher concentration than the first body region. The trench power semiconductor device of claim 15, further comprising a body conductive type doped region disposed at a bottom of the second contact hole and having a higher concentration than the second body region. The trench power semiconductor device of claim 11, wherein the third trench surrounds the first and second trenches. The trench power semiconductor device of claim 11, wherein the conductive material filling the first contact hole is electrically connected to a conductive material filling the second contact hole. The trench power semiconductor device of claim 11, wherein the third trench is filled with a conductive material, and the conductive material in the third trench is insulated from the epitaxial layer. The trench power semiconductor device of claim 19, further comprising a third contact hole disposed in a body region at the top of the epitaxial layer outside the third trench, wherein the third contact hole is filled A conductive material and is electrically connected to the conductive material filling the third trench.