CN111769157A - High density trench device structure and method of making same - Google Patents

High density trench device structure and method of making same Download PDF

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CN111769157A
CN111769157A CN202010790604.6A CN202010790604A CN111769157A CN 111769157 A CN111769157 A CN 111769157A CN 202010790604 A CN202010790604 A CN 202010790604A CN 111769157 A CN111769157 A CN 111769157A
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source region
type source
region
layer
axis direction
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苏亚兵
马一洁
何鑫鑫
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Shanghai Wei'an Semiconductor Co ltd
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Abstract

The invention discloses a high-density groove device structure and a manufacturing method thereof, and belongs to the field of power semiconductors. Compared with the traditional groove MOSFET structure, the high-density groove device structure has the advantages that the isolation layer is sunk into the groove, the whole groove device structure is used as a source region electrode layer, etching of a source contact hole is not needed, and the whole structure is simplified; the layout mode that the first conduction type source regions and the second conduction type source regions are arranged at intervals along the Y-axis direction breaks through the limitation of the first conduction type source regions and the second conduction type source regions on the cell region size in the transverse direction. The manufacturing method of the high-density groove device structure can be used for manufacturing the ultra-high-density groove MOSFET with the cell density of 0.5um or less, the cell density is improved by more than three times, and the characteristic on-resistance of the device can be integrally reduced by more than 20%.

Description

High density trench device structure and method of making same
Technical Field
The invention relates to the field of power semiconductors, in particular to a high-density groove device structure and a manufacturing method thereof.
Background
The trench power mosfet (trench mos) has a low switching loss and a high switching speed due to its high integration level, low on-resistance, low gate-drain charge density, and large current capacity, and is widely used in low-voltage power fields, such as power management, battery protection, and power devices.
An important index for measuring the power MOSFET is a characteristic on-resistance Rsp, namely the on-resistance of a chip in unit area; the device on-resistance is generally composed of a substrate resistance, an epitaxial layer resistance, a channel resistance, a source-drain contact resistance, and the like, and the channel resistance of the low-voltage MOSFET accounts for about 1/3 in terms of the device resistance. At present, an important measure for reducing the on-resistance of a power device is to increase the cell density, that is, the higher the cell density and the higher the channel density, the higher the channel resistance is, the higher the cell density is, the higher the channel resistance is, the proportion is reduced. The current trench MOSFET has been sub-micron sized on cell size, the 0.9um cell size high density trench MOSFET has matured, and the cell density has reached 120M cell/cm for the 0.9um sub-micron cell size2(ii) a However, as the cell size is reduced to submicron, for example, the cell size is further reduced to deep submicron by a large gradient, the limitation of the photolithography and etching processes and the limitation of the original lateral (X-axis) dimension of the source N +/P + doping of the device face, which hinders the further ultra-high integration development of the trench MOSFET cell density.
As shown in fig. 2, a method for manufacturing a trench MOSFET structure by a conventional process generally includes forming an epitaxial layer 12 on a silicon-based substrate 11, and performing photolithography and etching on the epitaxial layer 12 to form a trench 13; growing a gate oxide layer 14 and depositing and reversely etching a polysilicon electrode 15 in the trench 13, so that an upper interface of the polysilicon is basically flush with the surface of the silicon; self-aligned implantation and annealing of the p-type base region 16 are carried out on the upper part of the polysilicon electrode 15; implanting and annealing an N + source region 18 in a preset region on the upper part of the p-type base region 16, and depositing and growing an isolation medium 17 on the upper part of the N + source region 18; photoetching and etching the source contact hole c, keeping the etching depth in silicon to be 0.3-0.4 um to penetrate through the N + source region 18, and performing injection and annealing of a P + impurity region 19 at the bottom of the source contact hole c in a self-alignment manner; and performing tungsten plug deposition of a source contact hole c, deposition of a source metal aluminum copper alloy layer 10(ALCU), passivation, thinning of the back of the wafer and metallization.
In the trench MOSFET structure manufactured by the process, the N + source region 18, the source contact hole c and the P + impurity region 19 are all on the same cross section, the etching of the contact hole needs to leave a transverse space for N +, the alignment requirement of the contact hole and the trench is very strict, and the performance of the device can be reduced due to slight deviation of the size on the dimension of a submicron unit cell; this structure is therefore greatly limited as the cell size progresses below 0.9 um.
Disclosure of Invention
Aiming at the problem that the cell size is limited by the existing trench MOSFET structure, a high-density trench device structure and a manufacturing method thereof are provided, wherein the high-density trench device structure can effectively improve the cell density.
The invention provides a high-density groove device structure, comprising:
a substrate of a first conductivity type;
an epitaxial layer of a first conductivity type over the substrate;
the groove is formed in the epitaxial layer along the Y-axis direction and is lined with an oxide layer and a grid electrode in sequence;
a body region of a second conductivity type over the epitaxial layer;
further comprising:
an isolation layer is lined in the groove and is positioned above the grid electrode;
a plurality of first conduction type source regions formed along the X-axis direction and located above the substrate region are distributed at intervals in the Y-axis direction;
a second conductive type source region located above the body region and in a spacer region of the first conductive type source region;
the groove penetrates through the base region, the first conduction type source region and the second conduction type source region;
a source region electrode layer over the isolation layer, the first conductive type source region, and the second conductive type source region.
Optionally, the thickness of the isolation layer is 2000A to 7500A.
Optionally, a ratio of a width of the first conductive type source region in the Y axis direction to a width of the second conductive type source region in the Y axis direction is between 3:1 and 10: 1.
Optionally, the thickness of the source region electrode layer is 4 um.
Optionally, the depth of the groove is 1 um-2 um, and the width is 0.2 um-0.7 um.
Optionally, the groove pitch of the groove is larger than the width of the groove.
The invention also provides a manufacturing method of the high-density groove device structure, which comprises the following steps:
forming an epitaxial layer of a first conductivity type over a substrate of the first conductivity type;
etching a groove in the epitaxial layer along the Y-axis direction;
forming an oxide layer on the surface of the groove and above the epitaxial layer;
depositing and back-etching the upper part of the oxide layer in the groove to form a grid in a pit shape;
performing first ion implantation of a second conductive type on the upper part of the epitaxial layer to form a substrate region;
further comprising:
depositing above the grid electrode in the pit shape to form an isolation layer;
a shielding region and an injection region are arranged above the substrate region at preset intervals in the Y-axis direction, and photoetching injection of second ions is carried out on the upper part of the injection region to form a first conductive type source region along the X-axis direction;
photoetching and injecting third ions at the upper part of the shielding region to form a second conductive type source region;
removing the oxide layer over the first conductive type source region and the second conductive type source region;
and performing metal sputtering above the isolation layer, the first conduction type source region and the second conduction type source region to form a source region electrode layer.
Optionally, a ratio of a width of the first conductive type source region in the Y axis direction to a width of the second conductive type source region in the Y axis direction is between 3:1 and 10: 1.
Optionally, the thickness of the isolation layer is 2000A to 7500A.
Optionally, the thickness of the source region electrode layer is 4 um.
Compared with the traditional groove MOSFET structure, the high-density groove device structure has the advantages that the isolation layer is sunk into the groove, the whole groove device structure is used as a source region electrode layer, etching of a source contact hole is not needed, and the whole structure is simplified; the layout mode that the first conduction type source regions and the second conduction type source regions are arranged at intervals along the Y-axis direction breaks through the limitation of the first conduction type source regions and the second conduction type source regions on the cell region size in the transverse direction. The manufacturing method of the high-density groove device structure can be used for manufacturing the ultra-high-density groove MOSFET with the cell density of 0.5um or less, the cell density is improved by more than three times, and the characteristic on-resistance of the device can be integrally reduced by more than 20%.
Drawings
FIG. 1 is a schematic perspective view of one embodiment of a high density trench device structure according to the present invention;
FIG. 2 is a schematic diagram of a prior art trench MOSFET structure;
FIG. 3A is a cross-sectional view of a substrate after trench etching;
FIG. 3B is a cross-sectional view of a structure with an oxide layer formed over the epitaxial layer;
FIG. 3C is a cross-sectional view of a structure for forming a gate;
FIG. 3D is a cross-sectional view of the structure after implantation into a base region;
FIG. 3E is a cross-sectional view of the structure after forming an isolation layer;
fig. 3F is a perspective view of a structure for forming a first conductive type source region;
fig. 3G is a perspective view of a structure for forming a second conductive type source region;
fig. 3H is a cross-sectional view of the structure after forming the source electrode layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
Example one
Referring to fig. 1 and 3A-3H, the present embodiment provides a high-density trench device structure, including: a substrate 21 of a first conductivity type;
an epitaxial layer 22 of the first conductivity type over the substrate 21;
a plurality of first conduction type source regions formed along the X-axis direction and located above the substrate region are distributed at intervals in the Y-axis direction;
a body region 26 of a second conductivity type over the epitaxial layer 22;
further comprising:
the trench 23 is also lined with an isolation layer 27, the isolation layer 27 being located above the gate 25;
a plurality of source regions 28 of the first conductivity type spaced apart along the X-axis over the body region 26;
a second conductivity type source region 29 located above the body region 26 in a spaced-apart region of the first conductivity type source region 28;
the trench 23 penetrates the body region 26, the first conductive type source region 28 and the second conductive type source region 29;
a source electrode layer 20 over the isolation layer 27, the first conductive-type source region 28, and the second conductive-type source region 29.
In the embodiment, the isolation layer 27 is sunk in the trench 23 in the high-density trench device structure, and the whole trench device structure is used as the source electrode layer 20, so that the source contact hole is sputtered in a self-alignment manner without etching, and the problems of hole photoetching alignment and the like are avoided; the layout mode that the first conduction type source regions 28 and the second conduction type source regions 29 are arranged at intervals along the Y-axis direction breaks through the limitation that the first conduction type source regions 28 and the second conduction type source regions 29 are distributed in the transverse direction to reduce the sizes of the cell regions, so that the sizes of the MOSFET cells are increased from 0.9um to 0.5um, and the cell density is increased from 120M/cm2Lifting to 400M/cm2The improvement of the on-resistance due to the increase of the area of the source contact hole is increased by 3.3 times, and the characteristic on-resistance of the device can be correspondingly increased by more than 20%, so that the static power consumption of the power device is reduced by more than 20%.
As an example, if the first conductive type is N-type, the second conductive type is P-type; if the first conductive type is a P type, the second conductive type is an N type.
As an example, the epitaxial layer 22 has a thickness of 1um to 5 um. In practical applications, the thickness of the epitaxial layer 22 can be set according to the device withstand voltage requirement.
As an example, the depth of the groove 23 is 1um to 2m, the width is 0.2um to 0.7um, and the groove interval is larger than the width of the groove 23.
By way of example and not limitation, the trenches 23 have a width of 0.2um, a slot pitch of 0.3um, and a depth of 1.5 um.
By way of example, oxide layer 24 is a gate oxide layer, and oxide layer 24 may be grown in trenches 23 and epitaxial layer 22 by thermal oxidation, where oxide layer 24 typically has a thickness of 150A to 800A (angstroms). In practical applications, the thickness of the oxide layer 24 can be set according to the device withstand voltage and threshold voltage requirements.
As an example, the gate 25 is polysilicon, and the gate 25 is deposited and etched back in the trench 23 lined with the oxide layer 24 to a thickness of 0.2um to 0.5um to form a recess, so as to reserve a space for the subsequent deposition of the isolation layer 27.
Preferably, the thickness of the isolation layer 27 is 0.4 um.
Further, an isolation layer 27 is deposited above the grid 25, and wet etching is carried out to ensure that the residual oxygen content thickness on the surface of the substrate region 26 is within the range of 100A-500A; to act as a shield oxide for the subsequent implantation of the first conductivity type source region 28, a crescent-shaped recess is created on top of the isolation layer 27 due to the isotropy of the wet etch.
By way of example, the ratio of the width of the first conductivity-type source region 28 in the Y-axis direction (longitudinal direction) to the width of the second conductivity-type source region 29 in the Y-axis direction is between 3:1 and 10: 1.
By way of example and not limitation, the ratio of the longitudinal width of first conductivity-type source region 28 to the longitudinal width of second conductivity-type source region 29 is 5: 1.
As an example, the source region electrode layer 20 has a thickness of 4 um.
Example two
Referring to fig. 1 and fig. 3A to fig. 3H, fig. 3A to fig. 3H illustrate a manufacturing method and a manufacturing process of the high-density trench device structure according to the present embodiment. The embodiment provides a manufacturing method of a high-density trench device structure, which comprises the following steps:
s1. forming an epitaxial layer 22 of a first conductivity type over a substrate 21 of the first conductivity type (see fig. 3A);
wherein, the thickness of the epitaxial layer 22 is 1um to 5 um. In practical applications, the thickness of the epitaxial layer 22 can be set according to the device withstand voltage requirement.
S2, etching a groove 23 in the epitaxial layer 22 along the Y-axis direction (see FIG. 3A);
specifically, the trenches 23 are etched on the epitaxial layer 22 along the Y-axis direction, the etching depth of the trenches 23 is 1um to 2um, the width is 0.2um to 0.7um, and the trench pitch is greater than the width of the trenches 23.
S3, forming an oxide layer 24 on the surface of the groove 23 and above the epitaxial layer 22 (see figure 3B);
specifically, an oxide layer 24 is grown on the surfaces of the epitaxial layer 22 and the trench 23 by thermal oxidation, and the thickness of the oxide layer 24 is 150A-800A. In practical applications, the thickness of the oxide layer 24 can be set according to the device withstand voltage and threshold voltage requirements.
S4, depositing and etching back the upper part of the oxide layer 24 in the groove 23 to form a pit-shaped grid 25 (see figure 3C);
specifically, a recessed gate 25 with a thickness of 0.2 um-0.5 um is deposited and etched back in the trench 23 lined with the oxide layer 24 to reserve a space for the subsequent deposition of the isolation layer 27.
S5, performing first ion implantation of a second conductive type on the upper part of the epitaxial layer 22 to form a substrate region 26 (see figure 3D);
by way of example and not limitation, the first ions may employ boron (B) ions. When the second conductivity type is P-type, a boron ion lightly doped implant and anneal is performed above epitaxial layer 22 to form body region 26 at 1100 degrees celsius for 30 minutes.
S6, depositing to form an isolation layer 27 above the grid 25 in a pit shape (see the figure 3E);
further, chemical vapor deposition of the isolation layer 27 is performed above the gate electrode 25, and the deposition degree is 0.4um to 0.8 um. After the deposition is finished, carrying out wet etching on the isolation medium to ensure that the thickness of the residual oxygen on the surface of the substrate area 26 is within the range of 100A-500A; to act as a shield oxide for the subsequent implantation of the first conductivity type source region 28, a crescent-shaped recess is created on top of the isolation layer 27 due to the isotropy of the wet etch.
S7, an isolation region and an implantation region are disposed above the substrate region 26 at a predetermined interval in the Y-axis direction, and a first conductive type source region 28 along the X-axis direction is formed by performing a photolithography implantation of second ions at an upper portion of the implantation region (see fig. 3F);
by way of example and not limitation, the second ions may employ arsenic (As) ions or phosphorus (P) ions. When the first conductivity type is N-type, photolithography of N + heavy doping, arsenic ion heavy doping implantation, and annealing are performed on the upper portion of the body region 26. In fig. 3F, the area indicated by the size a is an implantation area where the photolithography window opens N +, the area indicated by the size B is a shielding area of the photoresist, the shielding area is used for shielding the As ion implantation of N +, and a space is reserved for the subsequent B ion implantation, wherein the ratio of the size a to the size B may be 5: 1.
S8, photoetching and injecting third ions at the upper part of the shielding region to form a second conductive type source region 29 (see the figure 3G);
by way of example and not limitation, the third ion may be a boron ion or boron difluoride (BF)2) Ions. When the second conductivity type is P-type, photolithography of source region P + heavy doping, boron ion heavy doping implantation, and annealing are performed in the shielding region (position indicated by b-dimension in fig. 3G), forming a second conductivity type source region 29.
S9, removing the oxide layer 24 above the first conductive type source region 28 and the second conductive type source region 29;
this step is to perform pre-metal cleaning to ensure that no oxide layer remains at the contact position of the source region electrode layer 20.
S10, performing metal sputtering on the isolation layer 27, the first conductive type source region 28, and the second conductive type source region 29 to form a source electrode layer 20 (see fig. 1 and 3H), and performing subsequent metal photolithography and back-gold processes in the same way as the conventional process, which is omitted.
Wherein, the thickness of source region electrode layer 20 is 4 um.
By way of example and not limitation, metal sputtering of 4um aluminum copper alloy, aluminum silicon copper alloy, or aluminum silicon alloy may be performed to form the source region electrode layer 20.
In this embodiment, the manufacturing method of the high-density trench device structure can be used for manufacturing an ultra-high-density trench MOSFET with a cell density of 0.5um or less, the cell density is increased by more than three times, and the characteristic on-resistance of the device can be reduced by more than 20% as a whole.
As an example, if the first conductive type is N-type, the second conductive type is P-type; if the first conductive type is a P type, the second conductive type is an N type.
In the present embodiment, the method for manufacturing the high-density trench device structure is not required to sink the isolation layer 27 into the trench 23 and use the whole trench device structure as the source electrode layer 20, compared with the conventional trench MOSFET structure methodThe etching of the source contact hole is carried out, so that the overall structure is simplified; the layout mode that the first conduction type source regions 28 and the second conduction type source regions 29 are arranged at intervals along the Y-axis direction breaks through the limitation of the first conduction type source regions 28 and the second conduction type source regions 29 on the cell region size in the transverse direction, so that the MOSFET cell size is increased from 0.9um to 0.5um, and the cell density is increased from 120M/cm2Lifting to 400M/cm2The density of the cellular structure is increased by 3.33 times, namely the channel density is correspondingly increased by 3.33 times, and because the channel resistance accounts for 1/3 of the on resistance of the whole device and the area ratio of the whole source contact hole is enlarged, the characteristic resistance of an ultra-high density cellular product produced by adopting the high-density groove device structure can be reduced by at least more than 20 percent compared with the characteristic resistance of the existing high-density cellular product.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (10)

1. A high density trench device structure, comprising:
a substrate of a first conductivity type;
an epitaxial layer of a first conductivity type over the substrate;
the groove is formed in the epitaxial layer along the Y-axis direction and is lined with an oxide layer and a grid electrode in sequence;
a body region of a second conductivity type over the epitaxial layer;
it is characterized by also comprising:
an isolation layer is lined in the groove and is positioned above the grid electrode;
a plurality of first conduction type source regions formed along the X-axis direction and located above the substrate region are distributed at intervals in the Y-axis direction;
a second conductive type source region located above the body region and in a spacer region of the first conductive type source region;
the groove penetrates through the base region, the first conduction type source region and the second conduction type source region;
a source region electrode layer over the isolation layer, the first conductive type source region, and the second conductive type source region.
2. The high-density trench device structure of claim 1, wherein the thickness of the isolation layer is in the range of 2000A to 7500A.
3. The high-density trench device structure of claim 1 wherein a ratio of a width of the first conductivity type source region in the Y-axis direction to a width of the second conductivity type source region in the Y-axis direction is between 3:1 and 10: 1.
4. The high-density trench device structure of claim 1 wherein the source region electrode layer is 4um thick.
5. The high-density trench device structure of claim 1 wherein the trench has a depth of 1um to 2um and a width of 0.2um to 0.7 um.
6. The high-density trench device structure of claim 1 wherein the trench has a trench pitch greater than a width of the trench.
7. A method of fabricating a high density trench device structure, comprising:
forming an epitaxial layer of a first conductivity type over a substrate of the first conductivity type;
etching a groove in the epitaxial layer along the Y-axis direction;
forming an oxide layer on the surface of the groove and above the epitaxial layer;
depositing and back-etching the upper part of the oxide layer in the groove to form a grid in a pit shape;
performing first ion implantation of a second conductive type on the upper part of the epitaxial layer to form a substrate region;
it is characterized by also comprising:
depositing above the grid electrode in the pit shape to form an isolation layer;
a shielding region and an injection region are arranged above the substrate region at preset intervals in the Y-axis direction, and photoetching injection of second ions is carried out on the upper part of the injection region to form a first conductive type source region along the X-axis direction;
photoetching and injecting third ions at the upper part of the shielding region to form a second conductive type source region;
removing the oxide layer over the first conductive type source region and the second conductive type source region;
and performing metal sputtering above the isolation layer, the first conduction type source region and the second conduction type source region to form a source region electrode layer.
8. The method of claim 7, wherein a ratio of a length of the first conductivity type source region in a Y-axis direction to a length of the second conductivity type source region in the Y-axis direction is between 3:1 and 10: 1.
9. The method of claim 7, wherein the spacer layer has a thickness of 2000A to 7500A.
10. The method of claim 7, wherein the source electrode layer has a thickness of 4 um.
CN202010790604.6A 2020-08-07 2020-08-07 High density trench device structure and method of making same Pending CN111769157A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114420636A (en) * 2021-12-22 2022-04-29 深圳深爱半导体股份有限公司 Semiconductor device structure and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100176446A1 (en) * 2009-01-13 2010-07-15 Force Mos Technology Co. Ltd. MOSFET with source contact in trench and integrated schottky diode
JP2011108713A (en) * 2009-11-13 2011-06-02 Panasonic Corp Semiconductor device and method of manufacturing the same
CN103151310A (en) * 2013-03-11 2013-06-12 中航（重庆）微电子有限公司 Deeply-grooved power MOS (Metal Oxide Semiconductor) device and production method thereof
CN104576743A (en) * 2015-01-28 2015-04-29 无锡新洁能股份有限公司 Deep-groove power MOS (metal oxide semiconductor) device with ultrahigh cellular density and manufacturing method of deep-groove power MOS device
CN212517212U (en) * 2020-08-07 2021-02-09 上海维安半导体有限公司 High density trench device structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100176446A1 (en) * 2009-01-13 2010-07-15 Force Mos Technology Co. Ltd. MOSFET with source contact in trench and integrated schottky diode
JP2011108713A (en) * 2009-11-13 2011-06-02 Panasonic Corp Semiconductor device and method of manufacturing the same
CN103151310A (en) * 2013-03-11 2013-06-12 中航（重庆）微电子有限公司 Deeply-grooved power MOS (Metal Oxide Semiconductor) device and production method thereof
CN104576743A (en) * 2015-01-28 2015-04-29 无锡新洁能股份有限公司 Deep-groove power MOS (metal oxide semiconductor) device with ultrahigh cellular density and manufacturing method of deep-groove power MOS device
CN212517212U (en) * 2020-08-07 2021-02-09 上海维安半导体有限公司 High density trench device structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114420636A (en) * 2021-12-22 2022-04-29 深圳深爱半导体股份有限公司 Semiconductor device structure and preparation method thereof

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