WO2022067618A1 - Semiconductor power device - Google Patents

Semiconductor power device Download PDF

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Publication number
WO2022067618A1
WO2022067618A1 PCT/CN2020/119214 CN2020119214W WO2022067618A1 WO 2022067618 A1 WO2022067618 A1 WO 2022067618A1 CN 2020119214 W CN2020119214 W CN 2020119214W WO 2022067618 A1 WO2022067618 A1 WO 2022067618A1
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trench
type
region
gate
epitaxial layer
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PCT/CN2020/119214
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French (fr)
Chinese (zh)
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龚轶
刘磊
王鑫
刘伟
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苏州东微半导体有限公司
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Priority to PCT/CN2020/119214 priority Critical patent/WO2022067618A1/en
Publication of WO2022067618A1 publication Critical patent/WO2022067618A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application belongs to the technical field of semiconductor devices, such as a semiconductor power device.
  • the key parameters of semiconductor power devices include turn-on voltage (Threshold Voltage, Vth), on-resistance (Rdson), source-drain breakdown voltage (BVdss), gate-source leakage (Igss) and source-drain leakage (Idss), etc.
  • Leakage is a very important parameter to measure the performance of semiconductor power devices. Generally, semiconductor power devices require gate-source leakage to be less than 100nA. If the gate-source leakage is too large, the power consumption will increase, the device life will be shortened, and the gate-source short circuit will occur. , so that the device does not work properly. In the failure project of semiconductor power devices, gate-source leakage is one of the very difficult situations to avoid.
  • the present application provides a semiconductor power device to reduce the risk of failure of the semiconductor power device caused by gate-source leakage in the related art.
  • the present application provides a semiconductor power device, including: a cell area and a gate bus area, the cell area includes a plurality of periodically arranged cells, and the cell includes:
  • the depth of the second trench is smaller than that of the first trench depth; the second trench extends into the gate bus region, and the width of the second trench in the gate bus region is greater than its width in the cell region;
  • a p-type body region located in the n-type epitaxial layer and between the first trench and the second trench; and an n-type emitter region located in the p-type body region.
  • FIG. 1 is a schematic top view structural diagram of an embodiment of a semiconductor power device provided by the present application
  • FIG. 2 is a schematic cross-sectional structure diagram of FIG. 1 along the AA direction.
  • FIG. 1 is a schematic top view structure diagram of an embodiment of the semiconductor power device provided by the present application. It should be noted that, for the convenience of presentation, FIG. 1 only exemplarily shows the top view of a part of the semiconductor power device of the present application. Schematic diagram of the surface structure, FIG. 2 is a schematic diagram of the cross-sectional structure of FIG. 1 along the AA direction. As shown in FIGS. 1 and 2 , the semiconductor power device of the present application includes a cell region 31 and a gate bus region 32 . The cell region 31 includes a plurality of periodically arranged cells 200 , and only one cell 200 is exemplarily shown in the embodiment of the present application (see FIG. 2 ).
  • the cell 200 includes an n-type epitaxial layer 22 , two first trenches 11 in the n-type epitaxial layer 22 and a second trench 12 between the two first trenches 11 , the second trench 12
  • the depth of the first trench 11 is smaller than the depth of the first trench 11 .
  • the depth of the first trench 11 is 0.5 ⁇ m greater than the depth of the second trench 12 .
  • the semiconductor power device has a maximum breakdown voltage.
  • the second trench 12 extends into the gate bus region 32 , and the width of the second trench 12 in the gate bus region 32 is greater than that in the cell region 31 .
  • the first trenches 11 also extend into the gate bus region 32.
  • the first trenches 11 may not extend into the gate bus region 32.
  • the first trench 11 is provided with an insulating layer 23 and a conductive layer 24, and the conductive layer 24 is usually connected to a source voltage and is set to increase the breakdown voltage of the semiconductor power device.
  • the second trench 12 is provided with a gate dielectric layer 25 and a gate electrode 26.
  • the gate electrode 26 is usually connected to a gate voltage and is configured to control the opening and closing of the current channel of the semiconductor power device.
  • the cell 200 further includes a p-type body region 27 located in the n-type epitaxial layer 22 and between the first trench 11 and the second trench 12 , and an n-type emitter region 28 is disposed in the p-type body region 27 .
  • the semiconductor power device of the present application further includes a p-type collector region 21, and the n-type epitaxial layer 22 is located on the p-type collector region 21, so the semiconductor power device of the present application is an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor). Transistor, IGBT) power devices.
  • IGBT Insulated Gate Bipolar Transistor
  • an n-type charge storage layer 29 may also be formed in the n-type epitaxial layer 22, and the n-type charge storage layer 29 is located in the second trench 12 close to the p-type collector region 21.
  • the n-type charge storage layer 29 can improve the carrier distribution in the drift region of the device, so that the device can obtain a shorter turn-off time and reduce turn-off loss.
  • the width of the second trench 12 in the gate bus region 32 is greater than that in the cell 31 region, and the gate dielectric layer 25 and the gate electrode 26 are formed in the second trench 12, which can be Make the gate 26 have a larger width in the gate bus region 32, thereby making the gate 26 easier to be drawn out, increasing the thickness of the interlayer isolation layer between the gate lead and the n-type emitter region 28, reducing the gate source Risk of failure of semiconductor power devices due to leakage current.
  • an n-type field stop region may also be formed between the p-type collector region and the n-type epitaxial layer, and this structure is not shown in the embodiments of the present application.
  • the semiconductor power device of the present application further includes an n-type substrate, and the n-type epitaxial layer may also be formed on the n-type substrate, so the semiconductor power device of the present application is a power metal-oxide semiconductor field effect transistor with a traditional structure (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) device, the n-type substrate is an n-type drain region, and the n-type emitter region is an n-type source region, and this structure is not shown in the embodiments of the present application.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor

Abstract

The present application relates to the technical field of semiconductor power devices. Disclosed is a semiconductor power device, comprising a cellular area and a gate bus area. The cellular area comprises multiple cells arranged periodically; the cells comprise: an n-type epitaxial layer, two first trenches located in the n-type epitaxial layer, and one second trench between the two first trenches; the depth of the second trench is less than the depth of the first trench; the second trench extends to the gate bus area, and the width of the second trench in the gate bus area is greater than the width of the second trench in the cellular area.

Description

半导体功率器件Semiconductor Power Devices 技术领域technical field
本申请属于半导体器件技术领域，例如一种半导体功率器件。The present application belongs to the technical field of semiconductor devices, such as a semiconductor power device.
背景技术Background technique
半导体功率器件的关键参数包括开启电压(Threshold Voltage，Vth)、导通电阻(Rdson)、源漏击穿电压(BVdss)、栅源漏电(Igss)和源漏漏电(Idss)等，其中栅源漏电是衡量半导体功率器件性能的一个非常重要的参数，一般半导体功率器件要求栅源漏电要小于100nA，若栅源漏电偏大，轻则使功耗增大，器件寿命缩短，重则栅源短路，使器件不能正常工作。在半导体功率器件的失效项目中，栅源漏电是非常难避免的情况之一。The key parameters of semiconductor power devices include turn-on voltage (Threshold Voltage, Vth), on-resistance (Rdson), source-drain breakdown voltage (BVdss), gate-source leakage (Igss) and source-drain leakage (Idss), etc. Leakage is a very important parameter to measure the performance of semiconductor power devices. Generally, semiconductor power devices require gate-source leakage to be less than 100nA. If the gate-source leakage is too large, the power consumption will increase, the device life will be shortened, and the gate-source short circuit will occur. , so that the device does not work properly. In the failure project of semiconductor power devices, gate-source leakage is one of the very difficult situations to avoid.
发明内容SUMMARY OF THE INVENTION
本申请提供一种半导体功率器件，以降低相关技术中栅源漏电导致半导体功率器件失效的风险。The present application provides a semiconductor power device to reduce the risk of failure of the semiconductor power device caused by gate-source leakage in the related art.
本申请提供了一种半导体功率器件，包括：元胞区和栅极总线区，所述元胞区包括多个周期性排列的元胞，所述元胞包括：The present application provides a semiconductor power device, including: a cell area and a gate bus area, the cell area includes a plurality of periodically arranged cells, and the cell includes:
n型外延层；n-type epitaxial layer;
位于所述n型外延层内的两个第一沟槽以及介于所述两个第一沟槽之间的一个第二沟槽，所述第二沟槽的深度小于所述第一沟槽的深度；所述第二沟槽延伸至所述栅极总线区内，所述第二沟槽在所述栅极总线区内的宽度大于其在所述元胞区内的宽度；two first trenches in the n-type epitaxial layer and one second trench between the two first trenches, the depth of the second trench is smaller than that of the first trench depth; the second trench extends into the gate bus region, and the width of the second trench in the gate bus region is greater than its width in the cell region;
位于所述第一沟槽内的绝缘层和导电层；an insulating layer and a conductive layer within the first trench;
位于所述第二沟槽内的栅介质层和栅极；a gate dielectric layer and a gate located in the second trench;
位于所述n型外延层内且介于所述第一沟槽与所述第二沟槽之间的p型体区； 位于所述p型体区内设有n型发射极区。a p-type body region located in the n-type epitaxial layer and between the first trench and the second trench; and an n-type emitter region located in the p-type body region.
附图说明Description of drawings
图1是本申请提供的半导体功率器件的一个实施例的俯视面结构示意图；FIG. 1 is a schematic top view structural diagram of an embodiment of a semiconductor power device provided by the present application;
图2是图1沿AA方向的剖面结构示意图。FIG. 2 is a schematic cross-sectional structure diagram of FIG. 1 along the AA direction.
具体实施方式Detailed ways
以下将结合本申请实施例中的附图，通过具体方式，完整地描述本申请的技术方案。显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。应当理解，本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不配出至少一个其它元件或其组合的存在或添加。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。The technical solutions of the present application will be completely described below in specific manners with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, embodiments of the present application. It should be understood that terms such as "having", "comprising", and "including" as used herein do not assign the presence or addition of at least one other element or combination thereof. Meanwhile, in order to clearly illustrate the specific embodiments of the present application, the schematic diagrams listed in the accompanying drawings of the specification have enlarged the thicknesses of the layers and regions described in the present application, and the sizes of the listed figures do not represent actual sizes.
图1是本申请提供的半导体功率器件的一个实施例的俯视面结构示意图，需要说明的是，为了方便展示，图1仅示例性的示出了本申请的半导体功率器件中的一部分区域的俯视面结构示意图，图2是图1沿AA方向的剖面结构示意图。如图1和图2所示，本申请的半导体功率器件包括元胞区31和栅极总线区32。元胞区31包括多个周期性排列的元胞200，本申请实施例中仅示例性的示出了一个元胞200(参见图2)。FIG. 1 is a schematic top view structure diagram of an embodiment of the semiconductor power device provided by the present application. It should be noted that, for the convenience of presentation, FIG. 1 only exemplarily shows the top view of a part of the semiconductor power device of the present application. Schematic diagram of the surface structure, FIG. 2 is a schematic diagram of the cross-sectional structure of FIG. 1 along the AA direction. As shown in FIGS. 1 and 2 , the semiconductor power device of the present application includes a cell region 31 and a gate bus region 32 . The cell region 31 includes a plurality of periodically arranged cells 200 , and only one cell 200 is exemplarily shown in the embodiment of the present application (see FIG. 2 ).
元胞200包括n型外延层22，位于n型外延层22内的两个第一沟槽11以及介于两个第一沟槽11之间的一个第二沟槽12，第二沟槽12的深度小于第一沟槽11的深度，示例性的，第一沟槽11的深度比第二沟槽12的深度大0.5um，此时，半导体功率器件具有最大的击穿电压。The cell 200 includes an n-type epitaxial layer 22 , two first trenches 11 in the n-type epitaxial layer 22 and a second trench 12 between the two first trenches 11 , the second trench 12 The depth of the first trench 11 is smaller than the depth of the first trench 11 . Exemplarily, the depth of the first trench 11 is 0.5 μm greater than the depth of the second trench 12 . At this time, the semiconductor power device has a maximum breakdown voltage.
第二沟槽12延伸至栅极总线区32内，且第二沟槽12在栅极总线区内32的宽度大于其在元胞区31内的宽度。在本申请实施例中，第一沟槽11也延伸 至栅极总线区32内，可选的，第一沟槽11也可以不延伸至栅极总线区32内。The second trench 12 extends into the gate bus region 32 , and the width of the second trench 12 in the gate bus region 32 is greater than that in the cell region 31 . In this embodiment of the present application, the first trenches 11 also extend into the gate bus region 32. Optionally, the first trenches 11 may not extend into the gate bus region 32.
第一沟槽11内设有绝缘层23和导电层24，导电层24通常外接源极电压，设置为提高半导体功率器件的击穿电压。第二沟槽12内设有栅介质层25和栅极26，栅极26通常外接栅极电压，设置为控制半导体功率器件的电流沟道的开启和关断。The first trench 11 is provided with an insulating layer 23 and a conductive layer 24, and the conductive layer 24 is usually connected to a source voltage and is set to increase the breakdown voltage of the semiconductor power device. The second trench 12 is provided with a gate dielectric layer 25 and a gate electrode 26. The gate electrode 26 is usually connected to a gate voltage and is configured to control the opening and closing of the current channel of the semiconductor power device.
元胞200还包括位于n型外延层22内且介于第一沟槽11与第二沟槽12之间的p型体区27，p型体区27内设有n型发射极区28。The cell 200 further includes a p-type body region 27 located in the n-type epitaxial layer 22 and between the first trench 11 and the second trench 12 , and an n-type emitter region 28 is disposed in the p-type body region 27 .
本申请的半导体功率器件，还包括p型集电极区21，n型外延层22位于p型集电极区21之上，由此本申请的半导体功率器件为绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)功率器件。当本申请的半导体功率器件为IGBT功率器件时，还可以在n型外延层22内形成n型电荷存储层29，n型电荷存储层29位于第二沟槽12靠近p型集电极区21的一侧，n型电荷存储层29可以改善器件漂移区的载流子分布，使器件获得更小的关断时间，降低关断损耗。The semiconductor power device of the present application further includes a p-type collector region 21, and the n-type epitaxial layer 22 is located on the p-type collector region 21, so the semiconductor power device of the present application is an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor). Transistor, IGBT) power devices. When the semiconductor power device of the present application is an IGBT power device, an n-type charge storage layer 29 may also be formed in the n-type epitaxial layer 22, and the n-type charge storage layer 29 is located in the second trench 12 close to the p-type collector region 21. On one side, the n-type charge storage layer 29 can improve the carrier distribution in the drift region of the device, so that the device can obtain a shorter turn-off time and reduce turn-off loss.
本申请的半导体功率器件，第二沟槽12在栅极总线区32内的宽度大于其在元胞31区内的宽度，第二沟槽12内形成有栅介质层25和栅极26，可以使栅极26在栅极总线区32内具有更大的宽度，从而使栅极26更容易被引出，增大栅引线与n型发射极区28之间的层间隔离层厚度，降低栅源漏电导致半导体功率器件失效的风险。In the semiconductor power device of the present application, the width of the second trench 12 in the gate bus region 32 is greater than that in the cell 31 region, and the gate dielectric layer 25 and the gate electrode 26 are formed in the second trench 12, which can be Make the gate 26 have a larger width in the gate bus region 32, thereby making the gate 26 easier to be drawn out, increasing the thickness of the interlayer isolation layer between the gate lead and the n-type emitter region 28, reducing the gate source Risk of failure of semiconductor power devices due to leakage current.
本申请的半导体功率器件为IGBT功率器件时，还可以在p型集电极区和n型外延层之间形成n型场截止区，本结构在本申请实施例中不再展示。When the semiconductor power device of the present application is an IGBT power device, an n-type field stop region may also be formed between the p-type collector region and the n-type epitaxial layer, and this structure is not shown in the embodiments of the present application.
本申请的半导体功率器件还包括n型衬底，n型外延层还可以是形成在n型衬底之上，由此本申请的半导体功率器件为传统结构的功率金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET) 器件，n型衬底为n型漏区，n型发射极区作为n型源区，该结构在本申请实施例中不再展示。The semiconductor power device of the present application further includes an n-type substrate, and the n-type epitaxial layer may also be formed on the n-type substrate, so the semiconductor power device of the present application is a power metal-oxide semiconductor field effect transistor with a traditional structure (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) device, the n-type substrate is an n-type drain region, and the n-type emitter region is an n-type source region, and this structure is not shown in the embodiments of the present application.

Claims (5)

  1. 半导体功率器件，包括：元胞区和栅极总线区，所述元胞区包括多个周期性排列的元胞，所述元胞包括：A semiconductor power device includes: a cell area and a gate bus area, the cell area includes a plurality of periodically arranged cells, and the cell includes:
    n型外延层；n-type epitaxial layer;
    位于所述n型外延层内的两个第一沟槽以及介于所述两个第一沟槽之间的一个第二沟槽，所述第二沟槽的深度小于所述第一沟槽的深度；所述第二沟槽延伸至所述栅极总线区内，所述第二沟槽在所述栅极总线区内的宽度大于其在所述元胞区内的宽度；two first trenches in the n-type epitaxial layer and one second trench between the two first trenches, the depth of the second trench is smaller than that of the first trench depth; the second trench extends into the gate bus region, and the width of the second trench in the gate bus region is greater than its width in the cell region;
    位于所述第一沟槽内的绝缘层和导电层；an insulating layer and a conductive layer within the first trench;
    位于所述第二沟槽内的栅介质层和栅极；a gate dielectric layer and a gate located in the second trench;
    位于所述n型外延层内且介于所述第一沟槽与所述第二沟槽之间的p型体区；a p-type body region located within the n-type epitaxial layer and between the first trench and the second trench;
    位于所述p型体区内的n型发射极区。an n-type emitter region within the p-type body region.
  2. 如权利要求1所述的器件，还包括p型集电极区，所述n型外延层位于所述p型集电极区之上。The device of claim 1, further comprising a p-type collector region, the n-type epitaxial layer overlying the p-type collector region.
  3. 如权利要求2所述的器件，还包括位于所述n型外延层内的n型电荷存储层，所述n型电荷存储层位于所述第二沟槽靠近所述p型集电极区的一侧。3. The device of claim 2, further comprising an n-type charge storage layer within the n-type epitaxial layer, the n-type charge storage layer being located in a portion of the second trench adjacent to the p-type collector region side.
  4. 如权利要求1所述的器件，其中，所述导电层外接源极电压，所述栅极外接栅极电压。The device of claim 1, wherein the conductive layer is connected to a source voltage, and the gate is connected to a gate voltage.
  5. 如权利要求1所述的器件，还包括n型衬底，所述n型外延层位于所述n型衬底之上。The device of claim 1, further comprising an n-type substrate, the n-type epitaxial layer overlying the n-type substrate.
PCT/CN2020/119214 2020-09-30 2020-09-30 Semiconductor power device WO2022067618A1 (en)

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CN104241386A (en) * 2014-09-25 2014-12-24 无锡新洁能股份有限公司 Power MOSFT (metal-oxide -semiconductor field effect transistor) device with low specific on-resistance and manufacturing method of power MOSFT device
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CN111211169A (en) * 2020-02-26 2020-05-29 无锡新洁能股份有限公司 Shielded IGBT structure and manufacturing method thereof

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