WO2022067618A1 - Dispositif d'alimentation à semi-conducteur - Google Patents

Dispositif d'alimentation à semi-conducteur Download PDF

Info

Publication number
WO2022067618A1
WO2022067618A1 PCT/CN2020/119214 CN2020119214W WO2022067618A1 WO 2022067618 A1 WO2022067618 A1 WO 2022067618A1 CN 2020119214 W CN2020119214 W CN 2020119214W WO 2022067618 A1 WO2022067618 A1 WO 2022067618A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
type
region
gate
epitaxial layer
Prior art date
Application number
PCT/CN2020/119214
Other languages
English (en)
Chinese (zh)
Inventor
龚轶
刘磊
王鑫
刘伟
Original Assignee
苏州东微半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州东微半导体有限公司 filed Critical 苏州东微半导体有限公司
Priority to PCT/CN2020/119214 priority Critical patent/WO2022067618A1/fr
Publication of WO2022067618A1 publication Critical patent/WO2022067618A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application belongs to the technical field of semiconductor devices, such as a semiconductor power device.
  • the key parameters of semiconductor power devices include turn-on voltage (Threshold Voltage, Vth), on-resistance (Rdson), source-drain breakdown voltage (BVdss), gate-source leakage (Igss) and source-drain leakage (Idss), etc.
  • Leakage is a very important parameter to measure the performance of semiconductor power devices. Generally, semiconductor power devices require gate-source leakage to be less than 100nA. If the gate-source leakage is too large, the power consumption will increase, the device life will be shortened, and the gate-source short circuit will occur. , so that the device does not work properly. In the failure project of semiconductor power devices, gate-source leakage is one of the very difficult situations to avoid.
  • the present application provides a semiconductor power device to reduce the risk of failure of the semiconductor power device caused by gate-source leakage in the related art.
  • the present application provides a semiconductor power device, including: a cell area and a gate bus area, the cell area includes a plurality of periodically arranged cells, and the cell includes:
  • the depth of the second trench is smaller than that of the first trench depth; the second trench extends into the gate bus region, and the width of the second trench in the gate bus region is greater than its width in the cell region;
  • a p-type body region located in the n-type epitaxial layer and between the first trench and the second trench; and an n-type emitter region located in the p-type body region.
  • FIG. 1 is a schematic top view structural diagram of an embodiment of a semiconductor power device provided by the present application
  • FIG. 2 is a schematic cross-sectional structure diagram of FIG. 1 along the AA direction.
  • FIG. 1 is a schematic top view structure diagram of an embodiment of the semiconductor power device provided by the present application. It should be noted that, for the convenience of presentation, FIG. 1 only exemplarily shows the top view of a part of the semiconductor power device of the present application. Schematic diagram of the surface structure, FIG. 2 is a schematic diagram of the cross-sectional structure of FIG. 1 along the AA direction. As shown in FIGS. 1 and 2 , the semiconductor power device of the present application includes a cell region 31 and a gate bus region 32 . The cell region 31 includes a plurality of periodically arranged cells 200 , and only one cell 200 is exemplarily shown in the embodiment of the present application (see FIG. 2 ).
  • the cell 200 includes an n-type epitaxial layer 22 , two first trenches 11 in the n-type epitaxial layer 22 and a second trench 12 between the two first trenches 11 , the second trench 12
  • the depth of the first trench 11 is smaller than the depth of the first trench 11 .
  • the depth of the first trench 11 is 0.5 ⁇ m greater than the depth of the second trench 12 .
  • the semiconductor power device has a maximum breakdown voltage.
  • the second trench 12 extends into the gate bus region 32 , and the width of the second trench 12 in the gate bus region 32 is greater than that in the cell region 31 .
  • the first trenches 11 also extend into the gate bus region 32.
  • the first trenches 11 may not extend into the gate bus region 32.
  • the first trench 11 is provided with an insulating layer 23 and a conductive layer 24, and the conductive layer 24 is usually connected to a source voltage and is set to increase the breakdown voltage of the semiconductor power device.
  • the second trench 12 is provided with a gate dielectric layer 25 and a gate electrode 26.
  • the gate electrode 26 is usually connected to a gate voltage and is configured to control the opening and closing of the current channel of the semiconductor power device.
  • the cell 200 further includes a p-type body region 27 located in the n-type epitaxial layer 22 and between the first trench 11 and the second trench 12 , and an n-type emitter region 28 is disposed in the p-type body region 27 .
  • the semiconductor power device of the present application further includes a p-type collector region 21, and the n-type epitaxial layer 22 is located on the p-type collector region 21, so the semiconductor power device of the present application is an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor). Transistor, IGBT) power devices.
  • IGBT Insulated Gate Bipolar Transistor
  • an n-type charge storage layer 29 may also be formed in the n-type epitaxial layer 22, and the n-type charge storage layer 29 is located in the second trench 12 close to the p-type collector region 21.
  • the n-type charge storage layer 29 can improve the carrier distribution in the drift region of the device, so that the device can obtain a shorter turn-off time and reduce turn-off loss.
  • the width of the second trench 12 in the gate bus region 32 is greater than that in the cell 31 region, and the gate dielectric layer 25 and the gate electrode 26 are formed in the second trench 12, which can be Make the gate 26 have a larger width in the gate bus region 32, thereby making the gate 26 easier to be drawn out, increasing the thickness of the interlayer isolation layer between the gate lead and the n-type emitter region 28, reducing the gate source Risk of failure of semiconductor power devices due to leakage current.
  • an n-type field stop region may also be formed between the p-type collector region and the n-type epitaxial layer, and this structure is not shown in the embodiments of the present application.
  • the semiconductor power device of the present application further includes an n-type substrate, and the n-type epitaxial layer may also be formed on the n-type substrate, so the semiconductor power device of the present application is a power metal-oxide semiconductor field effect transistor with a traditional structure (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) device, the n-type substrate is an n-type drain region, and the n-type emitter region is an n-type source region, and this structure is not shown in the embodiments of the present application.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention se rapporte au domaine technique des dispositifs d'alimentation à semi-conducteur. L'invention concerne un dispositif d'alimentation à semi-conducteur, comprenant une zone cellulaire et une zone de bus de grille. La zone cellulaire comprend de multiples cellules disposées périodiquement ; les cellules comprennent : une couche épitaxiale de type n, deux premières tranchées situées dans la couche épitaxiale de type n, et une seconde tranchée entre les deux premières tranchées ; la profondeur de la seconde tranchée est inférieure à la profondeur de la première tranchée ; la seconde tranchée s'étend jusqu'à la zone de bus de grille, et la largeur de la seconde tranchée dans la zone de bus de grille est supérieure à la largeur de la seconde tranchée dans la zone cellulaire.
PCT/CN2020/119214 2020-09-30 2020-09-30 Dispositif d'alimentation à semi-conducteur WO2022067618A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/119214 WO2022067618A1 (fr) 2020-09-30 2020-09-30 Dispositif d'alimentation à semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/119214 WO2022067618A1 (fr) 2020-09-30 2020-09-30 Dispositif d'alimentation à semi-conducteur

Publications (1)

Publication Number Publication Date
WO2022067618A1 true WO2022067618A1 (fr) 2022-04-07

Family

ID=80951088

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/119214 WO2022067618A1 (fr) 2020-09-30 2020-09-30 Dispositif d'alimentation à semi-conducteur

Country Status (1)

Country Link
WO (1) WO2022067618A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203288599U (zh) * 2013-04-22 2013-11-13 无锡新洁能股份有限公司 一种新型结构的vdmos器件
CN104241386A (zh) * 2014-09-25 2014-12-24 无锡新洁能股份有限公司 具有低特征导通电阻的功率mosfet器件及其制造方法
CN204257658U (zh) * 2013-11-21 2015-04-08 成都芯源系统有限公司 场效应晶体管和边缘结构
CN205177854U (zh) * 2015-10-22 2016-04-20 青岛佳恩半导体有限公司 一种沟槽式mosfet
CN111211169A (zh) * 2020-02-26 2020-05-29 无锡新洁能股份有限公司 屏蔽型igbt结构及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203288599U (zh) * 2013-04-22 2013-11-13 无锡新洁能股份有限公司 一种新型结构的vdmos器件
CN204257658U (zh) * 2013-11-21 2015-04-08 成都芯源系统有限公司 场效应晶体管和边缘结构
CN104241386A (zh) * 2014-09-25 2014-12-24 无锡新洁能股份有限公司 具有低特征导通电阻的功率mosfet器件及其制造方法
CN205177854U (zh) * 2015-10-22 2016-04-20 青岛佳恩半导体有限公司 一种沟槽式mosfet
CN111211169A (zh) * 2020-02-26 2020-05-29 无锡新洁能股份有限公司 屏蔽型igbt结构及其制造方法

Similar Documents

Publication Publication Date Title
US10608106B2 (en) Power semiconductor devices
JP4028333B2 (ja) 半導体装置
US9318547B2 (en) Wide bandgap insulated gate semiconductor device
US8237195B2 (en) Power MOSFET having a strained channel in a semiconductor heterostructure on metal substrate
CN109920854B (zh) Mosfet器件
US9496382B2 (en) Field effect transistor, termination structure and associated method for manufacturing
EP2860762B1 (fr) Transistor à effet de champ à jonction pour haute tension
US11211485B2 (en) Trench power transistor
CN104201206A (zh) 一种横向soi功率ldmos器件
US7898024B2 (en) Semiconductor device and method for manufacturing the same
US8264015B2 (en) Semiconductor device wherein a first insulated gate field effect transistor is connected in series with a second field effect transistor
US11264468B2 (en) Semiconductor device
WO2019157819A1 (fr) Puce igbt comportant une grille composite et une tranchée tridimensionnelle
WO2019085850A1 (fr) Dispositif d'alimentation d'igbt
CN106920844A (zh) 一种具有n型浮空埋层的resurf hemt器件
WO2021042582A1 (fr) Dispositif de puissance à semi-conducteur
CN109755310B (zh) 一种分栅结构的功率晶体管
WO2019085752A1 (fr) Dispositif mosfet de puissance
WO2022067946A1 (fr) Dispositif d'alimentation à semi-conducteur
CN204375754U (zh) 低输入电容功率半导体场效应晶体管
US20140035031A1 (en) Semiconductor device and method of fabricating the same
CN117059667A (zh) 一种双沟道soi-ldmos晶体管
WO2022067618A1 (fr) Dispositif d'alimentation à semi-conducteur
JP2014216573A (ja) 半導体装置
CN210006743U (zh) 超结功率器件和电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20955643

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20955643

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20955643

Country of ref document: EP

Kind code of ref document: A1