CN104241386A - Power MOSFT (metal-oxide -semiconductor field effect transistor) device with low specific on-resistance and manufacturing method of power MOSFT device - Google Patents
Power MOSFT (metal-oxide -semiconductor field effect transistor) device with low specific on-resistance and manufacturing method of power MOSFT device Download PDFInfo
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- CN104241386A CN104241386A CN201410500191.8A CN201410500191A CN104241386A CN 104241386 A CN104241386 A CN 104241386A CN 201410500191 A CN201410500191 A CN 201410500191A CN 104241386 A CN104241386 A CN 104241386A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 116
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
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- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 108
- 239000002184 metal Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims description 137
- 238000000034 method Methods 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000002347 injection Methods 0.000 abstract description 25
- 239000007924 injection Substances 0.000 abstract description 25
- 230000001413 cellular effect Effects 0.000 description 24
- 230000015572 biosynthetic process Effects 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 12
- 238000009413 insulation Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 239000007769 metal material Substances 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 241000826860 Trapezium Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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Abstract
The invention relates to a power MOSFT (metal-oxide -semiconductor field effect transistor) device with low specific on-resistance and a manufacturing method of the power MOSFT device. An element region of the power MOSFT device comprises first trenches and second trenches which are arranged alternatively; depth of each of the second trenches in a first conductive type drift layer is not larger than that of each of the first trenches in the first conductive type drift layer. The first trenches which are covered with insulated oxide layers are filled with first conductive polycrystalline silicon; the second trenches which are covered with insulated gate oxide layers are filled with second conductive polycrystalline silicon. First conductive type injection regions are arranged on two sides of the opening of each of the second trench; the openings of the second trenches are covered with insulated dielectric layers. A first main surface metal layer is electrically simultaneously connected with the first conductive type injection regions and second conductive type well layers under the first main surface. The power MOSFT device has the advantages of low on-resistance, small gate charge (Qg), simple manufacturing process and high reliability.
Description
Technical field
The present invention relates to a kind of power MOSFET and manufacture method thereof, especially a kind of power MOSFET and manufacture method thereof with low specific on-resistance, belongs to the technical field of power semiconductor.
Background technology
Specific on-resistance (Rsp) is one of most important index evaluating MOSFET element current capacity, the product (i.e. Rsp*Qg or Rsp*Qgd) of usual specific on-resistance and gate charges electric charge (Qg) or grid leak electrode charge electric charge (Qgd) is as the quality factor (FOM) of device, quality factor becomes and judges the most direct most important technical indicator of a MOSFET product combination property, FOM is less, and the power loss representing devices function is lower.
For the mesohigh MOSFET element of 500V to 900V, use superjunction technology (Super Junction) effectively can reduce the specific on-resistance of device, its principle is in the drift region of device withstand voltage, be provided with the column region with drift region opposite dopant type, thus define with drift region can the withstand voltage P-N post pair of horizontal depletion, the resistivity that so just greatly can reduce drift region realizes the specific on-resistance reducing device under the condition obtaining identical withstand voltage level.Superjunction power MOSFET device has become the main devices kind of 500V-900V voltage section at present.
For the mesolow MOSFET element within 200V, especially the low pressure MOSFET element of 20V to 100V, the proportion that channel resistance due to device accounts for total conducting resistance has had obvious increase compared to mesohigh MOSFET element, therefore, the method that tradition reduces device specific on-resistance mainly around how to increase, launch by device cellular density (Cell Density), report single cellular pitch minimum is at present had to be of a size of 0.6 μm, but although increase cellular density can reduce specific on-resistance, but also greatly can increase grid source charging charge (Qgs) and the grid leak charging charge (Qgd) of device simultaneously, be unfavorable for the application of product in high frequency field, as synchronous rectification.
In the last few years, a kind of new technology obtains checking and promotes in mesolow MOSFET element field, this technology uses the cellular of groove structure, and in cellular groove, be provided with two parts conductive polycrystalline silicon, the gate metal of two parts conductive polycrystalline silicon difference interface unit and source metal, and between isolated by insulating oxide, the conductive polycrystalline silicon connecting grid is positioned at groove internal upper part, it is insulated gate oxide layer between itself and trenched side-wall, for the formation of the raceway groove of device, the conductive polycrystalline silicon connecting source electrode is positioned at groove bottom, itself and be thicker insulating oxide between trenched side-wall and bottom, when device withstand voltage works, it is for coupling electric charge in drift region, in the electric charge of coupling and drift region, the impurity of opposite types exhausts to support withstand voltage, be similar to super-junction MOSFET device, the resistivity of drift region can reduce by the MOSFET element of this structure greatly, thus under the condition obtaining identical withstand voltage level, reduce the specific on-resistance of device, in groove, the conductive polycrystalline silicon connecting source electrode can be positioned at groove bottom completely, also groove bottom can be partly positioned at, as depicted in figs. 1 and 2.In addition, this structure due to under-filled in groove be the conductive polycrystalline silicon connecting source electrode, Gate Electrode Conductive polysilicon is obviously reduced with the crossover region area be connected between the drift region that drains, and therefore, the Qgd of MOSFET element is also much smaller than the Qgd of conventional trench MOSFET element.
But, although the structure of this low pressure MOSFET element can effectively reduce Rsp and Qgd of device, but still there is following shortcoming:
1, owing to being provided with the conductive polycrystalline silicon connecting grid and source electrode respectively in cellular groove simultaneously, and between by one deck insulating oxide institute interval, therefore, this structure devices in turn introduces this part grid source electric capacity (Cgs), add grid source charging charge (Qgs) of device, be unfavorable for the driving loss and the switching loss that reduce device.
2, because the conductive polycrystalline silicon connecting grid in cellular groove is isolated by one deck insulating oxide with the conductive polycrystalline silicon being connected source electrode, therefore, the reliability of isolation just must be considered, and in the manufacture process of reality, this two parts conductive polycrystalline silicon all needs through polycrystal etching, polysilicon profile after etching is difficult to accomplish smoothly neatly, usually some wedge angles or " V " type shallow slot can all be there is, so, insulating oxide layer growth is also difficult to the thickness realizing uniform ground later, this just brings huge hidden danger for reliability in the future, fact proved, one of this problem principal risk point having become this class formation.
3, due to mutually isolated two parts conductive polycrystalline silicon will be formed in same groove; therefore; process window often can be restricted each other between the processing steps such as the deposit of the growth of etching groove, thick oxide layer and burn into polysilicon and etching; thus considerably increase the complexity of technique; not only reduce the reliability of product, too increase manufacturing cost simultaneously.
4, the conductive polycrystalline silicon owing to connecting source electrode is positioned at the latter half of groove, and need this part conductive polycrystalline silicon to be managed draw to be connected with source electrode, therefore, this structure too increases design difficulty and the window of device, also to a certain degree can increase the chip area of device and manufacture complexity.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of power MOSFET device and the manufacture method thereof with low specific on-resistance are provided, its conducting resistance is low, and gate charges electric charge (Qg) is little, and manufacturing process is simple and device has high reliability.
According to technical scheme provided by the invention, the described power MOSFET device with low specific on-resistance, in the top plan view of described MOSFET element, comprise the element region and terminal protection district that are positioned at semiconductor substrate, described element region is positioned at the center of semiconductor substrate, and terminal protection district is around embracing element district; On the cross section of described MOSFET element, semiconductor substrate has the first interarea and second interarea corresponding with described first interarea, comprise the first conduction type drift layer between the first interarea and the second interarea and be positioned at the first conductivity type substrate layer below described first conduction type drift layer, first conductivity type substrate layer and the first conduction type drift layer adjoin, the surface of the first conduction type drift layer forms the first interarea, and the surface of the first conductivity type substrate forms the second interarea; Top in the first conduction type drift layer arranges the second conduction type well layer; Its innovation is:
On the cross section of described MOSFET element, described element region comprises the first groove and the second groove; First groove is alternately disposed adjacent with the second groove, and the degree of depth of the second groove in the first conduction type drift layer is no more than the degree of depth of the first groove in the first conduction type drift layer;
On the cross section of described MOSFET element, the first groove is extended vertically downward by the first interarea of semiconductor substrate, in the first conduction type drift layer below the degree of depth to the second conduction type well layer; The grown on interior walls of the first groove is coated with insulating oxide, in described the first groove being coated with insulating oxide, be filled with the first conductive polycrystalline silicon;
On the cross section of described MOSFET element, the second groove has the first interarea of semiconductor substrate to extend vertically downward, in the first conduction type drift layer below the degree of depth to the second conduction type well layer; The grown on interior walls of the second groove is coated with insulated gate oxide layer, is filled with the second conductive polycrystalline silicon in the second groove being coated with insulated gate oxide layer; Both sides outside the second groove notch arrange the first conductivity type implanted region, and the first conductivity type implanted region contacts with the outer wall of the second groove; The notch of the second groove is coated with insulating medium layer;
On the cross section of described MOSFET element, first interarea of semiconductor substrate is provided with the first interarea metal level, described first interarea metal level is electrically connected with first conductive polycrystalline silicon of filling in the first groove, the second conductive polycrystalline insulate on Si of the first interarea metal level by filling in insulating medium layer and the second groove, the first interarea metal level is electrically connected with the first conductivity type implanted region below the first interarea and the second conduction type well layer simultaneously.
On the cross section of described MOSFET element, the width of rebate of described first groove is greater than the width of rebate of the second groove; Distance between two adjacent first trenches is not more than the distance between two adjacent second grooves.
The thickness of the insulating oxide in described first groove is greater than the thickness of insulated gate oxide layer in the second groove.
Second interarea of described semiconductor substrate is coated with the second interarea metal level, the second interarea metal level is electrically connected with the first conductivity type substrate layer.
Have a manufacture method for the power MOSFET device of low specific on-resistance, the manufacture method of described power MOSFET device comprises the steps:
A, provide the first conductive type semiconductor substrate with two opposing main faces, described interarea comprises the first interarea and second interarea corresponding with described first interarea, comprises the first conductivity type substrate and be positioned at the first conduction type drift layer above described first conductivity type substrate between the first interarea and the second interarea;
B, the first hard mask layer being set on the first interarea of above-mentioned semiconductor substrate, optionally sheltering and etch described first hard mask layer, to be formed for etching the first hard mask layer window obtaining the first groove above the first interarea of semiconductor substrate;
C, utilize above-mentioned first hard mask layer window, by the first interarea of anisotropic dry etch semiconductor substrate, to obtain the first required groove in semiconductor substrate, described first groove extends vertically downward from the first interarea of semiconductor substrate, and the degree of depth of the first groove is no more than the thickness of the first conduction type drift layer;
D, the first hard mask layer removed on above-mentioned semiconductor substrate, and the first insulating oxide body is set on the first interarea of semiconductor substrate, described first insulating oxide body covers the first interarea of semiconductor substrate, and the first insulating oxide body covers the inwall of the first groove;
E, on the first interarea of above-mentioned semiconductor substrate, arrange the first conductive polycrystalline silicon floor, described first conductive polycrystalline silicon floor to be filled in the first groove and to cover on the first insulating oxide body of the first interarea;
F, the first conductive polycrystalline silicon floor removed on above-mentioned semiconductor substrate first interarea, to obtain the first conductive polycrystalline silicon being positioned at the first groove;
G, the first insulating oxide body removed on above-mentioned semiconductor substrate first interarea, to obtain the insulating oxide being positioned at the first groove;
H, the second hard mask layer being set on the first interarea of above-mentioned semiconductor substrate, optionally sheltering and etch described second hard mask layer, to be formed for etching the second hard mask layer window obtaining the second groove above the first interarea of semiconductor substrate;
I, utilize the second hard mask layer window, by the first interarea of anisotropic dry etch semiconductor substrate, to obtain the second required groove in semiconductor substrate, described second groove extends vertically downward from the first interarea of semiconductor substrate, and the degree of depth of the second groove is no more than the degree of depth of the first groove;
J, the second hard mask layer removed on above-mentioned first interarea, and the second insulating oxide body is set on the first interarea of semiconductor substrate, described insulating oxide body covers the first interarea of semiconductor substrate, and covers the inwall of the second groove;
K, on the first interarea of above-mentioned semiconductor substrate, arrange the second conductive polycrystalline silicon floor, described second conductive polycrystalline silicon floor covers the second insulating oxide body and is filled in the second groove;
L, remove the second conductive polycrystalline silicon floor above above-mentioned semiconductor substrate first interarea, to obtain being positioned at the second conductive polycrystalline silicon;
M, on the first interarea of above-mentioned semiconductor substrate, autoregistration ion implantation second conductive type impurity ion, and the second conduction type well layer being positioned at the first conduction type drift layer top is formed by high temperature knot, described second conduction type well layer is less than the degree of depth of the second groove in the degree of depth of the first conduction type drift layer;
N, on the first interarea of above-mentioned semiconductor substrate, carry out source region photoetching, and inject the first conductive type impurity ion of high concentration, and form the first conductivity type implanted region by high temperature knot, described first conductivity type implanted region is positioned at the outside of the second groove notch, and the first conductivity type implanted region contacts with the outer wall of the second groove;
O, insulating medium layer body is set on the first interarea of above-mentioned semiconductor substrate, and optionally etches described insulating medium layer body, to obtain the insulating medium layer of covering second groove notch; Remove the second insulating oxide body on semiconductor substrate first interarea, obtain the insulated gate oxide layer being positioned at the second groove, described insulated gate oxide layer is positioned between the inwall of the second conductive polycrystalline silicon and the second groove simultaneously;
P, on the first interarea of above-mentioned semiconductor substrate deposit first interarea metal level, described first interarea metal level is electrically connected with the first conductive polycrystalline silicon in the second conduction type well layer, the first conductivity type implanted region and the first groove simultaneously;
Q, on the second interarea of semiconductor substrate deposit second interarea metal level, the second interarea metal level is electrically connected with the first conductivity type substrate layer.
The thickness of described insulating oxide is 1000 à ~ 10000 à.
The thickness of described insulated gate oxide layer is 100 à ~ 150 à.
Described first hard mask layer, the second hard mask layer are LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
Described insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
The width of rebate of described first groove is greater than the width of rebate of the second groove; Distance between two adjacent first trenches is not more than the distance between two adjacent second grooves.
In both described " the first conduction type " and " the second conduction type ", for N-type MOSFET element, the first conduction type refers to N-type, and the second conduction type is P type; For P type MOSFET element, the first conduction type is just in time contrary with N type semiconductor device with the type of the second conduction type indication.
Advantage of the present invention:
1, at element region, comprise the first groove and the second groove, wherein the second groove comprises insulated gate oxide layer and the second conductive polycrystalline silicon being connected gate electrode, the effect of the second groove forms conducting channel when break-over of device works, wherein the first groove comprises thicker insulating oxide and the first conductive polycrystalline silicon being connected source electrode, the effect of the first groove is when device withstand voltage works, and is coupled out the charge carrier contrary with drift layer doping type thus exhausts withstand voltage with drift layer in drift layer.In contrast original structure, two parts conductive polycrystalline silicon is arranged in a groove, by arranging the first groove and the second groove, this avoid the part that in original structure, two parts conductive polycrystalline silicon is overlapping, thus eliminate grid source electric capacity (Cgs) that this part structure formed, significantly reduce the switching loss of device and drive loss.
2, avoid two parts polysilicon in same groove, also solve insulation isolating problem in original structure between two parts polysilicon, considerably increase the withstand voltage quality of grid oxygen of device and the reliability of overall device, making the process window of product when carrying out gate oxide growth technique, polycrystalline silicon deposition process and polycrystalline silicon etching process larger, significantly reducing manufacture difficulty and cost.
3, the second groove notch is only had to be coated with insulating medium layer, therefore when above element region first interarea during deposit covering metal layer, this metal level can directly be electrically connected with the first conductive polycrystalline silicon in the first groove, and do not need to draw the first conductive polycrystalline silicon especially by other approach, difficulty when can reduce design layout like this and the process window increased when manufacturing, be beneficial to the large production of product more.
Accompanying drawing explanation
Fig. 1 is that the one of existing groove type power MOS FET device implements structural representation.
Fig. 2 is that the another kind of existing groove type power MOS FET device implements structural representation.
Fig. 3 is the vertical view of power MOSFET device of the present invention.
Fig. 4 is the profile in power MOSFET components district of the present invention.
Fig. 5 ~ Figure 19 is power MOSFET device of the present invention concrete implementing process step cutaway view, wherein
Fig. 5 is the cutaway view after obtaining the first hard mask layer window.
Fig. 6 is the cutaway view after obtaining the first groove.
Fig. 7 is the cutaway view after obtaining the first insulating oxide body.
Fig. 8 is the cutaway view after obtaining the first polysilicon layer.
Fig. 9 is the cutaway view after obtaining the first polysilicon.
Figure 10 is the cutaway view after obtaining insulating oxide.
Figure 11 is the cutaway view after obtaining the second hard mask layer window.
Figure 12 is the cutaway view after obtaining the second groove.
Figure 13 is the cutaway view after obtaining the second polysilicon layer.
Figure 14 is the cutaway view after obtaining insulated gate oxide layer and the second polysilicon layer.
Figure 15 is the cutaway view after obtaining the second conduction type well region.
Figure 16 is the cutaway view after obtaining the first conductivity type implanted region.
Figure 17 is the cutaway view after obtaining insulating medium layer.
Figure 18 is the cutaway view after obtaining the first interarea metal level.
Figure 19 is the cutaway view after obtaining the second interarea metal level.
Description of reference numerals: 1-element region, 2-terminal protection district, 3-N type drift layer, 4-N+ substrate layer, 5-second interarea metal level, 6-P type well layer, 7-first groove, 8-second groove, 9-insulating oxide, 10-first conductive polycrystalline silicon, 11-insulated gate oxide layer, 12-second conductive polycrystalline silicon, 13-N+ injection region, 14-insulating medium layer, 15-first interarea metal level, 16-first hard mask layer, 17-first hard mask layer window, 18-first insulating oxide body, 19-first polysilicon body, 20-second hard mask layer, 21-second hard mask layer window, 22-second conductive polycrystalline silicon floor, 100-N type drift region, 101-N+ substrate zone, 102-channel insulation oxide layer, 103-trench polisilicon, 104-P type well region, 105-N+ cellular injection region, 106-channel insulation dielectric layer, 107-source metal, 108-source electrode, 109-gate electrode and 110-drain electrode.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in Figure 1: be the existing enforcement structure chart with the groove type power MOS FET device of low specific on-resistance, wherein, on the cross section of power MOSFET device, the element region of power MOSFET device adopts groove structure, cellular groove is positioned at N-type drift region 100, the degree of depth of cellular groove is less than the thickness of N-type drift region 100, and N-type drift region 100 adjoins with N+ substrate zone 101.Top in N-type drift region 100 arranges P type trap zone 104, and described P type trap zone 104 runs through N-type drift region 100.Channel insulation oxide layer 102 and trench polisilicon 103 is provided with in cellular groove, in the arranged outside N+ cellular injection region 105 of cellular groove notch, N+ cellular injection region 105 is positioned at P type trap zone 104, and N+ cellular injection region 105 contacts with the outer wall of cellular groove.The notch of cellular groove arranges channel insulation dielectric layer 106, and insulating medium layer 106 covers the notch of cellular groove and covers on the N+ cellular injection region 105 of cellular groove two side portions.Above N-type drift region 100, arrange source metal 107, described source metal 107 is electrically connected with P type trap zone 104, N+ cellular injection region 105.In cellular groove, the trench polisilicon 103 of a part is by forming source electrode 108 with the electrical connection of source metal 103, and another part trench polisilicon 103 in cellular groove can form gate electrode 109, and N+ substrate zone 101 can form drain electrode 110.Insulated by channel insulation oxide layer between conductive polycrystalline silicon for the formation of source electrode 108 and the conductive polycrystalline silicon for the formation of gate electrode 109 in cellular groove and isolate.
Structure in Fig. 2 and Fig. 1 similar, be only in cellular groove different from the position between the conductive polycrystalline silicon for the formation of gate electrode 109 for the formation of the conductive polycrystalline silicon of source electrode 108.The shortcoming that the power MOSFET that Fig. 1 and Fig. 2 implements structure exists is as described above, repeats no more herein.
As shown in Fig. 3, Fig. 4 and Figure 19, in order to make the conducting resistance of power MOSFET device low, gate charges electric charge (Qg) is little, manufacturing process is simple and device has high reliability, for N-type power MOSFET device, the present invention, in the top plan view of described MOSFET element, comprises the element region 1 and terminal protection district 2 that are positioned at semiconductor substrate, described element region 1 is positioned at the center of semiconductor substrate, and terminal protection district 2 is around embracing element district 1; On the cross section of described MOSFET element, semiconductor substrate has the first interarea and second interarea corresponding with described first interarea, comprise N-type drift layer 3 between the first interarea and the second interarea and be positioned at the N-type substrate layer 4 below described N-type drift layer 3, N-type substrate layer 4 adjoins with N-type drift layer 3, the surface of N-type drift layer 3 forms the first interarea, and the surface of N-type substrate 4 forms the second interarea; Top in N drift layer 3 arranges P type well layer 6;
On the cross section of described MOSFET element, described element region 1 comprises the first groove 7 and the second groove 8; First groove 7 is alternately disposed adjacent with the second groove 8, and the degree of depth of the second groove 8 in N-type drift layer 3 is no more than the degree of depth of the first groove 7 in N-type drift layer 3;
On the cross section of described MOSFET element, the first groove 7 is extended vertically downward by the first interarea of semiconductor substrate, in the N-type drift layer 3 below the degree of depth to P type well layer 6; The grown on interior walls of the first groove 7 is coated with insulating oxide 9, in described the first groove 7 being coated with insulating oxide 9, be filled with the first conductive polycrystalline silicon 10;
On the cross section of described MOSFET element, the second groove 8 has the first interarea of semiconductor substrate to extend vertically downward, in the N-type drift layer 3 below the degree of depth to P type well layer 6; The grown on interior walls of the second groove 8 is coated with insulated gate oxide layer 11, is filled with the second conductive polycrystalline silicon 12 in the second groove 8 being coated with insulated gate oxide layer 11; Both sides outside the second groove 8 notch arrange injection region, N+ type injection region 13, N+ 13 and contact with the outer wall of the second groove 8; The notch of the second groove 8 is coated with insulating medium layer 14;
On the cross section of described MOSFET element, first interarea of semiconductor substrate is provided with the first interarea metal level 15, described first interarea metal level 15 is electrically connected with first conductive polycrystalline silicon 10 of filling in the first groove 7, first interarea metal level 15 is isolated by second conductive polycrystalline silicon 12 of filling in insulating medium layer 14 and the second groove 8, and the first interarea metal level 15 is electrically connected with P type well layer 6 with the N+ injection region 13 below the first interarea simultaneously.
Particularly, terminal protection district can adopt existing conventional structure, as long as can realize effectively protecting.The degree of depth of the second groove 8 in N-type drift layer 3 is no more than the degree of depth of the first groove 7 in N-type drift region 3 and refers to, the degree of depth of the second groove 8 in N-type drift layer 3 is less than or equal to the degree of depth of the first groove 7 in N-type drift region 3.First groove 7, second groove 8 is all positioned at the below of P type well layer 6 through the bottom land of P type well layer 6, first groove 7 and the bottom land of the second groove 8, P type well layer 6 runs through the N-type drift region 3 being positioned at element region 1.
On the cross section of described MOSFET element, the width of rebate of described first groove 7 is greater than the width of rebate of the second groove 8; Distance between two adjacent first trenches 7 is not more than the distance between two adjacent second grooves 8.Distance between two adjacent first trenches 7 is less than or equal to the distance between two adjacent second grooves 8.
The thickness of the insulating oxide 9 in described first groove 7 is greater than the thickness of insulated gate oxide layer 11 in the second groove 8.Second interarea of described semiconductor substrate is coated with the second interarea metal level 5, second interarea metal level 5 to be electrically connected with N-type substrate layer 4.
As shown in Fig. 5 ~ Figure 19, the above-mentioned power MOSFET device with low specific on-resistance can be prepared by following technique, and described manufacture method comprises the steps:
A, provide the N type semiconductor substrate with two opposing main faces, described interarea comprises the first interarea and second interarea corresponding with described first interarea, comprises N-type substrate layer 4 and be positioned at the N-type drift layer 3 above described N-type substrate layer 4 between the first interarea and the second interarea;
The material of semiconductor substrate can adopt silicon, also can be other semi-conducting material.The surface of N-type drift layer 3 is for the formation of the first interarea of semiconductor substrate, and the surface of N-type substrate layer 4 is for the formation of the second interarea of semiconductor substrate, and the first interarea and the second interarea are Relative distribution.
B, the first hard mask layer 16 is set on the first interarea of above-mentioned semiconductor substrate, optionally shelter and etch described first hard mask layer 16, to be formed for etching the first hard mask layer window 17 obtaining the first groove 7 above the first interarea of semiconductor substrate;
As shown in Figure 5, described first hard mask layer 16 is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.Through first hard mask layer 16 of first hard mask layer window 17; the first interarea of semiconductor substrate can be made to expose by the first hard mask layer window 17; the first hard mask layer 16 outside first hard mask layer window 17 covers on the first interarea of semiconductor substrate, can block protection to the first covered interarea.
C, utilize above-mentioned first hard mask layer window 17, by the first interarea of anisotropic dry etch semiconductor substrate, to obtain the first required groove 7 in semiconductor substrate, described first groove 7 extends vertically downward from the first interarea of semiconductor substrate, and the degree of depth of the first groove 7 is no more than the thickness of N-type drift layer 3;
As shown in Figure 6, because first interarea corresponding with the first hard mask layer window 17 is exposed, after utilizing the first interarea of anisotropic dry etch semiconductor substrate, the first groove 7 can be obtained, the width of rebate of the first groove 7 is corresponding with the first hard mask layer window 17, the degree of depth of the first groove 7 can be selected as required, but the degree of depth of the first groove 7 can not exceed N-type drift layer 3, and namely the bottom land of the first groove 7 will be positioned at N-type drift region 3.
D, the first hard mask layer 16 removed on above-mentioned semiconductor substrate, and the first insulating oxide body 18 is set on the first interarea of semiconductor substrate, described first insulating oxide body 18 covers the first interarea of semiconductor substrate, and the first insulating oxide body 18 covers the inwall of the first groove 7;
As shown in Figure 7, existing conventional semiconductor technology is utilized to carry out etching to the first hard mask layer 16 and remove, after removal first hard mask layer 16, first interarea of semiconductor substrate grows the first insulating oxide body 18, first insulating oxide body 18 can be generally silicon dioxide, and the thickness of the first insulating oxide body 18 is 1000 à ~ 10000 à.First insulating oxide body 18 can cover on the inwall of the first interarea and the first groove 7 simultaneously in growth, and the first insulating oxide body 18 be positioned on the first groove 7 inwall can be used in the insulating oxide 9 needed for formation.
E, on the first interarea of above-mentioned semiconductor substrate, arrange the first conductive polycrystalline silicon floor 19, described first conductive polycrystalline silicon floor 19 to be filled in the first groove 7 and to cover on the first insulating oxide body 18 of the first interarea;
As shown in Figure 8, due to the existence of the first insulating oxide body 18, when deposit filled conductive polysilicon, will certainly all obtain the first conductive polycrystalline silicon floor 19 in the first insulating oxide body 18 of the first interarea and the first groove 7, can be used in formation first conductive polycrystalline silicon 10 by the first conductive polycrystalline silicon floor 19.
F, the first conductive polycrystalline silicon floor 19 removed on above-mentioned semiconductor substrate first interarea, to obtain the first conductive polycrystalline silicon 10 being positioned at the first groove 7;
As shown in Figure 9, adopt the first conductive polycrystalline silicon floor 19 on the above-mentioned first insulating oxide body 18 of dry etching removal, retain the conductive polycrystalline silicon being positioned at the first groove 7, obtain the first conductive polycrystalline silicon 10 being positioned at the first groove 7.
G, the first insulating oxide body 18 removed on above-mentioned semiconductor substrate first interarea, to obtain the insulating oxide 9 being positioned at the first groove 7;
As shown in Figure 10, employing wet etching or dry etching remove the first insulating oxide body 18 on the first interarea, retain the first insulating oxide 18 be positioned on the first groove 7 inwall simultaneously, obtain the insulating oxide 9 of covering first groove 7 inwall, the thickness of insulating oxide 9 and the consistency of thickness of the first insulating oxide 18.
H, the second hard mask layer 20 is set on the first interarea of above-mentioned semiconductor substrate, optionally shelter and etch described second hard mask layer 20, to be formed for etching the second hard mask layer window 21 obtaining the second groove 8 above the first interarea of semiconductor substrate;
As shown in figure 11, the Material selec-tion of through second hard mask layer 20, second hard mask layer 20 of the second hard mask layer window 21 can be consistent with the first hard mask layer 16, and the region that the first interarea can be made corresponding by the second hard mask layer window 21 exposes.
I, utilize the second hard mask layer window 21, by the first interarea of anisotropic dry etch semiconductor substrate, to obtain the second required groove 8 in semiconductor substrate, described second groove 8 extends vertically downward from the first interarea of semiconductor substrate, and the degree of depth of the second groove 8 is no more than the degree of depth of the first groove 7;
As shown in figure 12, width and the second hard mask layer window 21 of the second groove 8 notch are corresponding to the same, the degree of depth of the second groove 8 is no more than the first groove 7, namely the bottom land of the second groove 8 is positioned at the top of the first groove 7 bottom land, or the bottom land of the bottom land of the second groove 8 and the first groove 7 is positioned in same level.On cross section, be alternately distributed between the first groove 7 and the second groove 8.
J, the second hard mask layer 20 removed on above-mentioned first interarea, and the second insulating oxide body is set on the first interarea of semiconductor substrate, described second insulating oxide body covers the first interarea of semiconductor substrate, and covers the inwall of the second groove 8;
The method removing the second hard mask layer 20 is consistent with the method removing the first hard mask layer 16, and the second insulating oxide body is also generally carbon dioxide layer, and the second insulating oxide body is mainly used in forming insulated gate oxide layer 11.After formation second insulating oxide body, the second insulating oxide knows from experience the inwall of covering first interarea, the first conductive polycrystalline silicon 10, insulating oxide 9 and the second groove 8.
K, on the first interarea of above-mentioned semiconductor substrate, arrange the second conductive polycrystalline silicon floor 22, described second conductive polycrystalline silicon floor 22 covers the second insulating oxide body and is filled in the second groove 8;
As shown in figure 13, be mainly used in forming the second conductive polycrystalline silicon 12 in the second groove 8 by the second conductive polycrystalline silicon floor 22; After the second conductive polycrystalline silicon floor 22 is filled in the first interarea deposit of semiconductor substrate, the second conductive polycrystalline silicon floor 22 can cover on the second insulating oxide body, and is filled by the second groove 8 full.
L, remove the second conductive polycrystalline silicon floor 22 above above-mentioned semiconductor substrate first interarea, to obtain being positioned at the second conductive polycrystalline silicon 12;
As shown in figure 14, remove the second conductive polycrystalline silicon floor 22 on the second insulating oxide body, retain the conductive polycrystalline silicon being positioned at the second groove 8, thus obtain the second conductive polycrystalline silicon 12 being positioned at the second groove 8.
M, on the first interarea of above-mentioned semiconductor substrate, autoregistration ion implantation p type impurity ion, and formed by high temperature knot and be positioned at the P type well layer 6 on N-type drift layer 3 top, described P type well layer 6 is less than the degree of depth of the second groove 8 in the degree of depth of N-type drift layer 3;
As shown in figure 15, P type well layer 6 is less than the degree of depth of the second groove 8 in the degree of depth of N-type drift layer 3, namely ensures that P type well layer 6 is positioned at the top of the second groove 8 bottom land, also can ensure that P type well layer 6 is positioned at the top of the first groove 7 bottom land.When after formation P type well layer 6, P type well layer 6 runs through N-type drift layer 3, and on cross section, the first groove 7 and the second groove 8 all will pass P type well layer 6.In the embodiment of the present invention, the temperature of high temperature knot is generally 900 DEG C ~ 1200 DEG C.
N, on the first interarea of above-mentioned semiconductor substrate, carry out source region photoetching, and inject the N-type impurity ion of high concentration, and form N+ injection region 13 by high temperature knot, described N+ injection region 13 is positioned at the outside of the second groove 8 notch, and N+ injection region 13 contacts with the outer wall of the second groove 8;
As shown in figure 16, the concentration of N+ injection region 13 is higher than the concentration of N-type drift layer 3, and N+ injection region 13 is positioned at P type well layer 6, N+ injection region 13 and also extends vertically downward from the first interarea, and being less than the thickness of P type well layer 6, N+ injection region 13 only contacts with the outer wall of the second groove 8.In the embodiment of the present invention, ion implantation concentration is generally at 5E14-1E16, and temperature is generally at 800 DEG C-1100 DEG C.
O, insulating medium layer body is set on the first interarea of above-mentioned semiconductor substrate, and optionally etches described insulating medium layer body, to obtain the insulating medium layer 14 of covering second groove 8 notch; Remove the second insulating oxide body on semiconductor substrate first interarea, obtain the insulated gate oxide layer 11 being positioned at the second groove 8, described insulated gate oxide layer 11 is positioned between the inwall of the second conductive polycrystalline silicon 12 and the second groove 8 simultaneously;
As shown in figure 17, particularly, the thickness of described insulated gate oxide layer is 100 à ~ 150 à.Described insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).On the first interarea, deposit insulating medium layer body is mainly used in forming insulating medium layer 14.Insulating medium layer body is entered optionally etch time, retain the insulating medium layer body above the second notch 8 and near notch both sides, can contact hole be formed when removing insulating medium layer body, and the second insulating oxide body covering the first conductive polycrystalline silicon 10 top in the first groove 7 can be removed while etching insulating medium layer body.The N+ injection region 13 of the insulating medium layer 14 meeting cover part formed.In the specific implementation, the second insulating oxide body also can be removed after removal second conductive polycrystalline silicon floor 22, and concrete technology can be selected as required, repeats no more herein.
P, on the first interarea of above-mentioned semiconductor substrate deposit first interarea metal level 15, described first interarea metal level 15 is connected with the first conductive polycrystalline silicon electricity 10 in P type well layer 6, N+ injection region 13 and the first groove 7 simultaneously;
As shown in figure 18, depositing metal material on the first interarea, obtain the first interarea metal level 15, first interarea metal level 15 is filled in above-mentioned contact hole, and cover on insulating medium layer 14, first interarea, thus the first interarea metal level 15 is connected with the first conductive polycrystalline silicon electricity 10 in P type well layer 6, N+ injection region 13 and the first groove 7 simultaneously.First interarea metal level 15 adopts existing conventional metal material.
Q, on the second interarea of semiconductor substrate, deposit second interarea metal level 5, second interarea metal level 5 is electrically connected with N-type substrate layer 4.
As shown in figure 19, by the second interarea depositing metal material, after obtaining the second interarea metal level 5, the second interarea metal level 5 is electrically connected with N-type substrate layer 4, can for the formation of drain electrode.
The working mechanism of MOSFET element of the present invention is: the P type well layer 6 outside insulated gate oxide layer 11, second conductive polycrystalline silicon 12 of the second groove 8 inside and the second groove 8 and N+ injection region 13 form the MOS structure of device jointly, second conductive polycrystalline silicon 12 is at the gate electrode of element region 1 edge leading-out connector part, P type well layer 6 and N+ injection region 13 are connected with the first interarea metal level above it and lead to the source electrode of device, and device second interarea metal level 5 leads to drain electrode.
When devices function is in conducting state, described MOS structure provides the conducting channel that controlled by gate electrode and forms the path of current flowing.Described P type well layer 6 is also connected with the first conductive polycrystalline silicon 10 in the first groove 7 with the first interarea metal level 15 above N+ injection region 13, heavy insulation oxide layer 9 on described first conductive polycrystalline silicon 10 and the first groove 7 inwall and the outer N-type drift layer 3 surveyed of the first groove 7 form a capacitance field plate structure, when devices function is in time ending resistance to pressure condition, the drain electrode of device can apply the voltage of a forward, now, described capacitance field plate structure will be coupled out positive charge in the N-type drift layer 3 around it, described positive charge can form depletion layer with the electronics in N-type drift layer 3, along with the rising of drain voltage, depletion layer is constantly expanded towards periphery, when depletion layer when between adjacent two the first grooves 7 contacts, the Withstand voltage layer that one is born device drain voltage will be set up, thus the drain voltage of supporting device, and before above-mentioned depletion layer contacts, device drain voltage is that the depletion layer formed by P type well layer 6 and N-type drift layer 3 is born.
Due to the capacitance field plate structure introducing the first groove 7 and formed by it, the Withstand voltage layer making device add again Charged Couple on original P trap-N-type epitaxy layer pressure-resistance structure basis in N-type drift layer 3 body to go out, the distribution of electric field in Withstand voltage layer becomes trapezium structure from original triangular structure, the voltage endurance capability of device increases greatly, on the other hand, to the original withstand voltage demand of retainer member, so N-type drift layer 3 resistivity of device just can reduce significantly, thus effectively reduces device on-resistance.
In embodiments of the present invention, first groove 7 and the second groove 8 separate, so there is not in original structure the situation that the second conductive polycrystalline silicon 12 of connecting grid is mutually overlapping with the first conductive polycrystalline silicon 10 being connected source electrode, thus eliminate device gate source electric charge (Qgs) of being introduced by this part structure, the gate charges electric charge (Qg) of device is obviously reduced, improves the switching characteristic of device; Simultaneously, avoid two parts conductive polycrystalline silicon in same groove, also solve insulation isolating problem in original structure between two parts polysilicon, considerably increase the withstand voltage quality of grid oxygen of device and the reliability of overall device, make the process window of product when carrying out gate oxide growth technique, polycrystalline silicon deposition process and polycrystalline silicon etching process larger, significantly reduce device manufacturing cost, improve the reliability of device.
Claims (10)
1. one kind has the power MOSFET device of low specific on-resistance, in the top plan view of described MOSFET element, comprise the element region and terminal protection district that are positioned at semiconductor substrate, described element region is positioned at the center of semiconductor substrate, and terminal protection district is around embracing element district; On the cross section of described MOSFET element, semiconductor substrate has the first interarea and second interarea corresponding with described first interarea, comprise the first conduction type drift layer between the first interarea and the second interarea and be positioned at the first conductivity type substrate layer below described first conduction type drift layer, first conductivity type substrate layer and the first conduction type drift layer adjoin, the surface of the first conduction type drift layer forms the first interarea, and the surface of the first conductivity type substrate forms the second interarea; Top in the first conduction type drift layer arranges the second conduction type well layer; It is characterized in that:
On the cross section of described MOSFET element, described element region comprises the first groove and the second groove; First groove is alternately disposed adjacent with the second groove, and the degree of depth of the second groove in the first conduction type drift layer is no more than the degree of depth of the first groove in the first conduction type drift layer;
On the cross section of described MOSFET element, the first groove is extended vertically downward by the first interarea of semiconductor substrate, in the first conduction type drift layer below the degree of depth to the second conduction type well layer; The grown on interior walls of the first groove is coated with insulating oxide, in described the first groove being coated with insulating oxide, be filled with the first conductive polycrystalline silicon;
On the cross section of described MOSFET element, the second groove has the first interarea of semiconductor substrate to extend vertically downward, in the first conduction type drift layer below the degree of depth to the second conduction type well layer; The grown on interior walls of the second groove is coated with insulated gate oxide layer, is filled with the second conductive polycrystalline silicon in the second groove being coated with insulated gate oxide layer; Both sides outside the second groove notch arrange the first conductivity type implanted region, and the first conductivity type implanted region contacts with the outer wall of the second groove; The notch of the second groove is coated with insulating medium layer;
On the cross section of described MOSFET element, first interarea of semiconductor substrate is provided with the first interarea metal level, described first interarea metal level is electrically connected with first conductive polycrystalline silicon of filling in the first groove, the second conductive polycrystalline insulate on Si of the first interarea metal level by filling in insulating medium layer and the second groove, the first interarea metal level is electrically connected with the first conductivity type implanted region below the first interarea and the second conduction type well layer simultaneously.
2. the power MOSFET device with low specific on-resistance according to claim 1, is characterized in that: on the cross section of described MOSFET element, and the width of rebate of described first groove is greater than the width of rebate of the second groove; Distance between two adjacent first trenches is not more than the distance between two adjacent second grooves.
3. the power MOSFET device with low specific on-resistance according to claim 1, is characterized in that: the thickness of the insulating oxide in described first groove is greater than the thickness of insulated gate oxide layer in the second groove.
4. the power MOSFET device with low specific on-resistance according to claim 1, is characterized in that: the second interarea of described semiconductor substrate is coated with the second interarea metal level, and the second interarea metal level is electrically connected with the first conductivity type substrate layer.
5. have a manufacture method for the power MOSFET device of low specific on-resistance, it is characterized in that, the manufacture method of described power MOSFET device comprises the steps:
(a), the first conductive type semiconductor substrate with two opposing main faces is provided, described interarea comprises the first interarea and second interarea corresponding with described first interarea, comprises the first conductivity type substrate and be positioned at the first conduction type drift layer above described first conductivity type substrate between the first interarea and the second interarea;
(b), on the first interarea of above-mentioned semiconductor substrate, the first hard mask layer is set, optionally shelter and etch described first hard mask layer, to be formed for etching the first hard mask layer window obtaining the first groove above the first interarea of semiconductor substrate;
(c), utilize above-mentioned first hard mask layer window, by the first interarea of anisotropic dry etch semiconductor substrate, to obtain the first required groove in semiconductor substrate, described first groove extends vertically downward from the first interarea of semiconductor substrate, and the degree of depth of the first groove is no more than the thickness of the first conduction type drift layer;
(d), the first hard mask layer removed on above-mentioned semiconductor substrate, and the first insulating oxide body is set on the first interarea of semiconductor substrate, described first insulating oxide body covers the first interarea of semiconductor substrate, and the first insulating oxide body covers the inwall of the first groove;
(e), on the first interarea of above-mentioned semiconductor substrate, the first conductive polycrystalline silicon floor is set, described first conductive polycrystalline silicon floor to be filled in the first groove and to cover on the first insulating oxide body of the first interarea;
F (), the first conductive polycrystalline silicon floor removed on above-mentioned semiconductor substrate first interarea, to obtain the first conductive polycrystalline silicon being positioned at the first groove;
G (), the first insulating oxide body removed on above-mentioned semiconductor substrate first interarea, to obtain the insulating oxide being positioned at the first groove;
(h), on the first interarea of above-mentioned semiconductor substrate, the second hard mask layer is set, optionally shelter and etch described second hard mask layer, to be formed for etching the second hard mask layer window obtaining the second groove above the first interarea of semiconductor substrate;
(i), utilize the second hard mask layer window, by the first interarea of anisotropic dry etch semiconductor substrate, to obtain the second required groove in semiconductor substrate, described second groove extends vertically downward from the first interarea of semiconductor substrate, and the degree of depth of the second groove is no more than the degree of depth of the first groove;
(j), the second hard mask layer removed on above-mentioned first interarea, and the second insulating oxide body is set on the first interarea of semiconductor substrate, described insulating oxide body covers the first interarea of semiconductor substrate, and covers the inwall of the second groove;
(k), on the first interarea of above-mentioned semiconductor substrate, the second conductive polycrystalline silicon floor is set, described second conductive polycrystalline silicon floor covers the second insulating oxide body and is filled in the second groove;
(l), remove the second conductive polycrystalline silicon floor above above-mentioned semiconductor substrate first interarea, to obtain being positioned at the second conductive polycrystalline silicon;
(m), on the first interarea of above-mentioned semiconductor substrate, autoregistration ion implantation second conductive type impurity ion, and the second conduction type well layer being positioned at the first conduction type drift layer top is formed by high temperature knot, described second conduction type well layer is less than the degree of depth of the second groove in the degree of depth of the first conduction type drift layer;
(n), on the first interarea of above-mentioned semiconductor substrate, carry out source region photoetching, and inject the first conductive type impurity ion of high concentration, and form the first conductivity type implanted region by high temperature knot, described first conductivity type implanted region is positioned at the outside of the second groove notch, and the first conductivity type implanted region contacts with the outer wall of the second groove;
(o), on the first interarea of above-mentioned semiconductor substrate, insulating medium layer body is set, and optionally etch described insulating medium layer body, to obtain the insulating medium layer of covering second groove notch; Remove the second insulating oxide body on semiconductor substrate first interarea, obtain the insulated gate oxide layer being positioned at the second groove, described insulated gate oxide layer is positioned between the inwall of the second conductive polycrystalline silicon and the second groove simultaneously;
(p), on the first interarea of above-mentioned semiconductor substrate deposit first interarea metal level, described first interarea metal level is electrically connected with the first conductive polycrystalline silicon in the second conduction type well layer, the first conductivity type implanted region and the first groove simultaneously;
(q), on the second interarea of semiconductor substrate deposit second interarea metal level, the second interarea metal level is electrically connected with the first conductivity type substrate layer.
6. there is the manufacture method of the power MOSFET device of low specific on-resistance according to claim 5, it is characterized in that: the thickness of described insulating oxide is 1000 à ~ 10000 à.
7. there is the manufacture method of the power MOSFET device of low specific on-resistance according to claim 5, it is characterized in that: the thickness of described insulated gate oxide layer is 100 à ~ 150 à.
8. there is the manufacture method of the power MOSFET device of low specific on-resistance according to claim 5, it is characterized in that: described first hard mask layer, the second hard mask layer are LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
9. there is the manufacture method of the power MOSFET device of low specific on-resistance according to claim 5, it is characterized in that: described insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
10. there is the manufacture method of the power MOSFET device of low specific on-resistance according to claim 5, it is characterized in that: the width of rebate of described first groove is greater than the width of rebate of the second groove; Distance between two adjacent first trenches is not more than the distance between two adjacent second grooves.
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| CN114068331A (en) * | 2022-01-12 | 2022-02-18 | 南京华瑞微集成电路有限公司 | SGT terminal structure for improving BV stability and preparation method thereof |
| CN114420761A (en) * | 2022-03-30 | 2022-04-29 | 成都功成半导体有限公司 | High-pressure-resistant silicon carbide device and preparation method thereof |
| CN114420761B (en) * | 2022-03-30 | 2022-06-07 | 成都功成半导体有限公司 | High-pressure-resistant silicon carbide device and preparation method thereof |
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