CN110061047B - IGBT structure and manufacturing method thereof - Google Patents
IGBT structure and manufacturing method thereof Download PDFInfo
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- CN110061047B CN110061047B CN201910439533.2A CN201910439533A CN110061047B CN 110061047 B CN110061047 B CN 110061047B CN 201910439533 A CN201910439533 A CN 201910439533A CN 110061047 B CN110061047 B CN 110061047B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 76
- 229920005591 polysilicon Polymers 0.000 claims abstract description 71
- 238000003860 storage Methods 0.000 claims abstract description 48
- 210000000746 body region Anatomy 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000012535 impurity Substances 0.000 claims description 49
- 238000005530 etching Methods 0.000 claims description 27
- 238000000137 annealing Methods 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 22
- 230000015556 catabolic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 230000004913 activation Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
Abstract
The invention relates to the technical field of semiconductors, and particularly discloses an IGBT structure, which comprises a collector metal, wherein a first conductive type collector region, a second conductive type buffer layer and a second conductive type epitaxial layer are sequentially arranged on the collector metal, grooves are formed in the second conductive type epitaxial layer at intervals, a first conductive type well region is arranged at the bottom of each groove, a second conductive type carrier storage layer is arranged in the second conductive type epitaxial layer between two adjacent grooves, a first conductive type body region is arranged on the surface of the second conductive type carrier storage layer, a second conductive type source region and a first conductive type source region are arranged on the surface of the first conductive type body region, conductive polysilicon is arranged on the side wall of each groove, and insulating medium layers are arranged at the bottoms of the grooves, the surfaces of the conductive polysilicon and the surfaces of the second conductive type epitaxial layer. The invention also discloses a manufacturing method of the IGBT structure. The IGBT structure provided by the invention improves the reliability.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an IGBT structure and a manufacturing method of the IGBT structure.
Background
An insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, abbreviated as IGBT) is used as an insulated gate bipolar device, and the higher the concentration of unbalanced carriers in the body, the more remarkable the effect of conductivity modulation, and the higher the current density. In order to improve the concentration of unbalanced carriers, a carrier storage layer doped with high-concentration N-type impurities is arranged below a P-type body region, so that the conductivity modulation effect of a drift region is enhanced, the forward voltage drop is reduced, the compromise characteristic of the forward voltage drop and the turn-off loss is improved, but the carrier storage layer can increase the electric field peak value near the region, and the breakdown voltage of an IGBT cell is reduced. In order to improve the anode carrier injection effect, the doping concentration of the carrier storage layer must be increased, and the breakdown voltage of the IGBT cell drops sharply with the increase of the doping concentration of the carrier storage layer. When the device is blocked in the forward direction, the high-concentration carrier storage layer can increase the electric field intensity in the gate oxide layer, so that the reliability of the gate oxide layer is reduced.
Therefore, in order to maintain a certain blocking capability of the device in practical application, a technician has to increase the thickness of the drift region of the device, which instead increases the forward voltage drop and deteriorates the trade-off characteristics of the forward voltage drop and the turn-off loss. Therefore, a new IGBT cell structure is needed to avoid the adverse effects of the increased doping concentration of the carrier storage layer on the breakdown voltage, forward blocking performance and reliability of the IGBT cell.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art, and provides an IGBT structure and a manufacturing method thereof, so as to solve the problems in the prior art.
As a first aspect of the present invention, there is provided an IGBT structure, including a collector metal, on which a first conductivity type collector region, a second conductivity type buffer layer, and a second conductivity type epitaxial layer are sequentially disposed, on which trenches are disposed at intervals, wherein a first conductivity type well region is disposed at a bottom of each trench, a second conductivity type carrier storage layer is disposed in the second conductivity type epitaxial layer between two adjacent trenches, a first conductivity type body region is disposed on a surface of the second conductivity type carrier storage layer, a second conductivity type source region and a first conductivity type source region are disposed on a surface of the first conductivity type body region, conductive polysilicon is disposed on a sidewall of the trench, an insulating dielectric layer is disposed on a bottom of the trench, a surface of the conductive polysilicon, and a surface of the second conductivity type epitaxial layer, an emitter metal layer is disposed on a surface of the insulating dielectric layer, and the emitter metal layer is in contact with the second conductivity type source region and the first conductivity type source region through a through-hole on the insulating dielectric layer.
Preferably, two pieces of conductive polysilicon are arranged in each groove, and an insulating medium layer is arranged between the two pieces of conductive polysilicon.
Preferably, both conductive polysilicon within the same trench are connected to the gate potential.
Preferably, one of the two conductive polysilicon within the same trench is connected to the gate potential and the other is connected to the source potential.
Preferably, two pieces of conductive polysilicon in the same trench are connected to the source potential, and two pieces of conductive polysilicon in the trenches adjacent to or spaced from the source potential are connected to the gate potential.
Preferably, a gate oxide layer is disposed between the conductive polysilicon and the sidewall of the trench, and the conductive polysilicon is disposed on the surface of the gate oxide layer.
Preferably, the lower boundary of the second conductive type carrier storage layer is higher than the bottom of the trench.
Preferably, the impurity concentration in the second conductivity type carrier storage layer ranges between 1e14 and 1e 18.
Preferably, the width of the trench ranges between 0.4 μm and 3 μm.
Preferably, the second conductive type epitaxial layer is provided with grooves with uniform intervals, and a plurality of grooves are parallel to each other.
Preferably, the first conductivity type includes a P-type and the second conductivity type includes an N-type.
As a second aspect of the present invention, there is provided a method for manufacturing an IGBT structure, wherein the method for manufacturing an IGBT structure includes:
providing a second conductivity type epitaxial layer;
forming a barrier layer on the surface of the second conductive type epitaxial layer, selectively etching the barrier layer, and etching the second conductive type epitaxial layer to form a groove;
implanting impurities of a second conductivity type into the trench in a direction at an angle a to the horizontal;
removing the barrier layer, and then forming a gate oxide layer on the surface of the second conductive type epitaxial layer;
depositing conductive polysilicon on the gate oxide layer, and forming the conductive polysilicon by etching;
etching the exposed gate oxide layer, including the gate oxide layer on the surface of the epitaxial layer between the two pieces of conductive polysilicon in the trench and the gate oxide layer on the surface of the epitaxial layer between the trenches, and then injecting first conductivity type impurities into the second conductivity type epitaxial layer;
performing a thermal annealing process to form a first conductive type body region, a second conductive type carrier storage layer and a first conductive type well region, injecting second conductive type impurities on the surface of the first conductive type body region, and forming a second conductive type source region after annealing;
depositing an insulating medium layer, selectively etching the deposited insulating medium layer and the second conductive type epitaxial layer on the surface of the first conductive type body region, then injecting first conductive type impurities, and forming a first conductive type source region after annealing;
depositing an emitter metal layer on the surface of the insulating medium layer;
injecting second-conductivity-type impurities and first-conductivity-type impurities into the surface of the second-conductivity-type epitaxial layer, which is away from the second-conductivity-type carrier storage layer, and sequentially forming a first-conductivity-type collector region and a second-conductivity-type buffer region;
and forming a collector metal on the surface of the second conductive type epitaxial layer, which faces away from the second conductive type carrier storage layer.
Preferably, the method for manufacturing the IGBT structure further includes, after the step of etching the exposed gate oxide layer, including the gate oxide layer on the surface of the epitaxial layer between the two pieces of conductive polysilicon in the trench and the gate oxide layer on the surface of the epitaxial layer between the trenches, implanting impurities of the first conductivity type into the epitaxial layer of the second conductivity type:
and selectively implanting impurities of the first conductivity type into the surface of the epitaxial layer of the second conductivity type between the trenches for the second time.
Preferably, the angle a ranges between 1 ° and 89 °.
Preferably, the first conductivity type includes a P-type and the second conductivity type includes an N-type.
According to the IGBT structure provided by the invention, the first conductive type well region is arranged at the bottom of the groove, so that the withstand voltage can be borne, the electric field peak value at the bottom of the groove is reduced, the influence of the increase of the doping concentration of the carrier storage layer on the breakdown voltage and the forward blocking property of an IGBT cell can be avoided, and the reliability of the IGBT structure is further improved.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention. In the drawings:
fig. 1 is a schematic structural diagram of an IGBT structure according to the present invention.
Fig. 2 is another schematic structural diagram of the IGBT structure provided by the invention.
Fig. 3 is a schematic structural diagram of an initial epitaxial layer for forming the IGBT structure shown in fig. 1 according to the present invention.
Fig. 4 is a schematic diagram of a structure of a barrier layer for forming the IGBT structure shown in fig. 1 according to the present invention.
Fig. 5 is a schematic diagram of implanting N-type impurities after forming an etched trench of the IGBT structure shown in fig. 1 according to the present invention.
Fig. 6 is a schematic diagram of a thermally grown gate oxide layer forming the IGBT structure shown in fig. 1 according to the present invention.
Fig. 7 is a schematic diagram of a deposited conductive polysilicon forming the IGBT structure shown in fig. 1 provided by the invention.
Fig. 8 is a schematic diagram of etched conductive polysilicon for forming the IGBT structure shown in fig. 1 according to the present invention.
Fig. 9 is a schematic diagram of an implanted P-type impurity for forming the IGBT structure shown in fig. 1 according to the present invention.
Fig. 10 is a schematic diagram of forming a P-type well region, an N-type carrier storage layer and a P-type body region after thermal annealing to form the IGBT structure shown in fig. 1, and then forming an N-type source region according to the present invention.
Fig. 11 is a schematic diagram of an insulating dielectric layer and a P-type source region for forming the IGBT structure shown in fig. 1 according to the present invention.
Fig. 12 is a schematic diagram of an initial epitaxial layer for forming the IGBT structure shown in fig. 2 according to the present invention.
Fig. 13 is a schematic diagram of a barrier layer for forming the IGBT structure shown in fig. 2 according to the present invention.
Fig. 14 is a schematic diagram of implanting N-type impurities after forming an etched trench of the IGBT structure shown in fig. 2 according to the present invention.
Fig. 15 is a schematic diagram of a thermally grown oxide provided by the present invention that forms the IGBT structure shown in fig. 2.
Fig. 16 is a schematic diagram of a thermally grown gate oxide layer after oxide removal to form the IGBT structure shown in fig. 2 according to the present invention.
Fig. 17 is a schematic diagram of a deposited conductive polysilicon forming the IGBT structure shown in fig. 2 provided by the invention.
Fig. 18 is a schematic diagram of etched conductive polysilicon for forming the IGBT structure shown in fig. 2 according to the present invention.
Fig. 19 is a schematic diagram of an implanted P-type impurity for forming the IGBT structure shown in fig. 2 according to the present invention.
Fig. 20 is a schematic diagram of forming a P-type well region, an N-type carrier storage layer and a P-type body region after thermal annealing to form the IGBT structure shown in fig. 2, and then forming an N-type source region according to the present invention.
Fig. 21 is a schematic diagram of forming an insulating dielectric layer and a P-type source region for forming the IGBT structure shown in fig. 2 according to the present invention.
Fig. 22 is a schematic diagram of a connection mode of the conductive polysilicon according to the present invention.
Fig. 23 is a flowchart of a method for fabricating an IGBT structure according to the present invention.
Reference numerals:
1. a collector metal; 2. a P-type collector region; 3. A P-type well region; 4. an N-type epitaxial layer; 5. a P-type well region; 6. conductive polysilicon; 7. a gate oxide layer; 8. an insulating dielectric layer; 9. an N-type carrier storage layer; 10. a P-type body region; 11. a P-type source region; 12. an N-type source region; 13. an emitter metal; 14. a barrier layer; 15. an oxide; 16. a grounded gate.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
As a first aspect of the present invention, there is provided an IGBT structure, as shown in fig. 1, comprising a collector metal 1, a first conductivity type collector region 2, a second conductivity type buffer layer 3, and a second conductivity type epitaxial layer 4 sequentially provided on the collector metal 1, trenches are provided on the second conductivity type epitaxial layer 4 at intervals, wherein a first conductivity type well region 5 is provided at the bottom of each trench, a second conductivity type carrier storage layer 9 is provided in the second conductivity type epitaxial layer 4 between two adjacent trenches, a first conductivity type body region 10 is provided on the surface of the second conductivity type carrier storage layer 9, a second conductivity type source region 12 and a first conductivity type source region 11 are provided on the surface of the first conductivity type body region 10, a conductive polysilicon 6 is provided on the side wall of each trench, an insulating medium layer 8 is provided on the bottom of each trench, a surface of the conductive polysilicon 6, and a surface of the second conductivity type epitaxial layer 4, a metal emitter layer 13 is provided on the surface of the insulating medium layer 8, and an ohmic contact region 13 is provided on the surface of the second conductivity type carrier storage layer 9 and the second conductivity type emitter layer 11.
According to the IGBT structure provided by the invention, the first conductive type well region is arranged at the bottom of the groove, so that the withstand voltage can be borne, the electric field peak value at the bottom of the groove is reduced, the influence of the increase of the doping concentration of the carrier storage layer on the breakdown voltage and the forward blocking property of an IGBT cell can be avoided, and the reliability of the IGBT structure is further improved.
Preferably, the first conductivity type includes a P-type and the second conductivity type includes an N-type.
It should be understood that the structures shown in the figures each include a P-type conductivity and the second conductivity type includes an N-type conductivity as an example.
The first conductivity type is P-type, and the second conductivity type is N-type, for example, are described below.
Specifically, two pieces of conductive polysilicon 6 are disposed in each trench, and an insulating dielectric layer 8 is disposed between the two pieces of conductive polysilicon 6.
As a first specific embodiment, two conductive polysilicon 6 located in the same trench are both connected to the gate potential.
As a second specific embodiment, as shown in fig. 22, one conductive polysilicon 6 of two conductive polysilicon 6 located in the same trench is connected to a gate potential, and the other conductive polysilicon 6 is connected to a source potential.
As a third specific embodiment, two pieces of conductive polysilicon 6 located in the same trench are both connected to the source potential, and two pieces of conductive polysilicon 6 located in the trenches adjacent to or spaced from the same are both connected to the gate potential.
It should be understood that, specifically, two conductive polysilicon 6 in two adjacent or multiple adjacent trenches are connected to the source potential, while two conductive polysilicon 6 in other trenches are connected to the gate potential, or the trench in which two conductive polysilicon 6 connected to the source potential are located and the trench in which two conductive polysilicon 6 connected to the gate potential are located are arranged at intervals, and the specific arrangement form of the trench is not limited, so long as it is ensured that two conductive polysilicon 6 in some trenches are connected to the source potential, and two conductive polysilicon 6 in some trenches are connected to the gate potential.
Specifically, a gate oxide layer 7 is disposed between the conductive polysilicon 6 and the sidewall of the trench, and the conductive polysilicon 6 is disposed on the surface of the gate oxide layer 7.
Specifically, the lower boundary of the second conductivity type carrier storage layer 9 is higher than the bottom of the trench. It should be understood that by the lower boundary of the second conductivity type carrier storage layer 9 being higher than the bottom of the trench, the withstand voltage can be improved, the electric field peak at the bottom of the trench can be reduced, and the reliability can be improved.
Specifically, the impurity concentration in the second conductivity type carrier storage layer 9 ranges from 1e14 to 1e 18.
Preferably, the concentration of the second conductivity type carrier storage layer 9 may be 5e16.
Specifically, the width of the trench ranges between 0.4 μm and 3 μm.
Preferably, the width of the trench may be 1 μm.
It should be appreciated that the trench of the present invention is wider than that of a conventional IGBT, with the following advantages: firstly, during the high-current conduction of the device, the bottom of the groove can effectively store enough charges, so that the carrier storage effect is enhanced, and the conduction voltage drop of the device is further reduced; secondly, the cell density of the device is smaller than that of the traditional IGBT, so that the saturation current of the device is obviously lower than that of the traditional IGBT, and the short circuit capacity of the device is greatly improved; third, the capacitance of the invention is obviously reduced, so that the EMI characteristic is improved, and compared with the traditional mode that in order to reduce the capacitance of the IGBT, a plurality of grid polycrystalline silicon are connected with source electrode potential, the mode of the invention can reduce the capacitance and simultaneously can not improve the conduction voltage drop.
Specifically, the trenches provided on the second conductivity type epitaxial layer 4 are uniformly spaced, and a plurality of the trenches are parallel to each other.
Preferably, the shape of the conductive polysilicon 6 includes a stripe shape.
Specifically, as shown in fig. 1, 2 and 22, the IGBT structure provided by the invention includes a collector metal 1, a P-type collector region 2 is disposed on the collector metal 1, an N-type buffer layer 3 is disposed on the P-type collector region 2, an N-type epitaxial layer 4 is disposed on the N-type buffer layer 3, trenches with uniform intervals and parallel to each other are disposed on the N-type epitaxial layer 4, and the width of the trenches is preferably 1 μm.
The bottom of the groove is provided with a P-type well region 5, an epitaxial layer between adjacent grooves is internally provided with an N-type carrier storage layer 9, the surface of the N-type carrier storage layer 9 is provided with a P-type body region 10, the surface of the P-type body region 10 is provided with an N-type source region 12 and a P-type source region 11, the side wall of the groove is provided with a gate oxide layer 7, the surface of the gate oxide layer 7 is provided with conductive polysilicon 6, the conductive polysilicon 6 is preferably in a narrow strip shape, two conductive polysilicon 6 exist in the same groove, an insulating medium layer 8 is arranged between the two conductive polysilicon 6, the bottom of the groove, the surfaces of the conductive polysilicon 6 and the epitaxial layer 4 are provided with insulating medium layers 8, the surface of the chip is provided with an emitter metal 13, and the emitter metal 13 is in ohmic contact with the N-type source region 12 and the P-type source region 11 through holes on the insulating medium layer 8.
As shown in fig. 22, one of the two conductive polysilicon 6 in one trench is connected to a gate potential, and the other is connected to a source potential. The lower boundary of the N-type carrier storage layer 9 is higher than the lower portion of the trench, and the concentration of impurities in the N-type carrier storage layer 9 is preferably 5e16.
It should be noted that, as shown in fig. 2, which is another specific embodiment of the IGBT structure, in fig. 2, compared with fig. 1, the width of the N-type carrier storage layer 9 and the width of the P-type body region 10 are both narrower, and one of the conductive polysilicon 16 is configured as a grounded gate, so that the saturation current can be effectively reduced, the cell density is higher, and the switching speed is effectively increased.
As a second aspect of the present invention, there is provided a method for manufacturing an IGBT structure, wherein the method for manufacturing an IGBT structure, as shown in fig. 23, includes:
s110, providing a second conductive type epitaxial layer;
s120, forming a barrier layer on the surface of the second conductive type epitaxial layer, selectively etching the barrier layer, and etching the second conductive type epitaxial layer to form a groove;
s130, implanting second conductivity type impurities into the groove in a direction with an angle a with the horizontal;
s140, removing the barrier layer, and then forming a gate oxide layer on the surface of the second conductive type epitaxial layer;
s150, depositing conductive polysilicon on the gate oxide layer, and forming conductive polysilicon by etching the conductive polysilicon;
s160, etching the exposed gate oxide layer, including the gate oxide layer positioned on the surface of the epitaxial layer between the two pieces of conductive polysilicon in the groove and the gate oxide layer positioned on the surface of the epitaxial layer between the grooves, and then injecting first conductivity type impurities into the second conductivity type epitaxial layer;
s170, performing a thermal annealing process to form a first conductive type body region, a second conductive type carrier storage layer and a first conductive type well region, injecting second conductive type impurities on the surface of the first conductive type body region, and forming a second conductive type source region after annealing;
s180, depositing an insulating medium layer, selectively etching the deposited insulating medium layer and the second conductive type epitaxial layer on the surface of the first conductive type body region, then injecting first conductive type impurities, and forming a first conductive type source region after annealing;
s190, depositing an emitter metal layer on the surface of the insulating medium layer;
s200, injecting second-conductivity-type impurities and first-conductivity-type impurities into the surface, facing away from the second-conductivity-type carrier storage layer, of the second-conductivity-type epitaxial layer, and sequentially forming a first-conductivity-type collector region and a second-conductivity-type buffer region;
and S210, forming collector metal on the surface of the second conductive type epitaxial layer, which faces away from the second conductive type carrier storage layer.
According to the manufacturing method of the IGBT structure, the first conductive type well region is arranged at the bottom of the groove, so that the withstand voltage can be borne, the electric field peak value at the bottom of the groove is reduced, the influence of the increase of the doping concentration of the carrier storage layer on the breakdown voltage and the forward blocking property of the IGBT cell can be avoided, and the reliability of the IGBT structure is further improved. In addition, the manufacturing method of the IGBT structure provided by the invention has the advantages of simple process and easiness in implementation.
Specifically, the method for manufacturing the IGBT structure further includes, after the step of etching the exposed gate oxide layer, including the gate oxide layer on the surface of the epitaxial layer between the two pieces of conductive polysilicon in the trench and the gate oxide layer on the surface of the epitaxial layer between the trenches, and then implanting impurities of the first conductivity type into the epitaxial layer of the second conductivity type:
and selectively implanting impurities of the first conductivity type into the surface of the epitaxial layer of the second conductivity type between the trenches for the second time.
Preferably, the angle a ranges between 1 ° and 89 °.
Preferably, the first conductivity type includes a P-type and the second conductivity type includes an N-type.
The specific implementation process of the manufacturing method of the IGBT structure provided by the invention is described in detail below with the first conductivity type being P-type and the second conductivity type being N-type.
Example 1
The manufacturing method of the embodiment 1 comprises the following steps:
step one, as shown in fig. 3, an N-type epitaxial layer 4 is provided;
step two, as shown in fig. 4, a barrier layer 14 is formed on the surface of the N-type epitaxial layer 4;
step three, as shown in fig. 5, selectively etching the barrier layer 14, then etching the N-type epitaxial layer 4 to form a gate trench, and then implanting N-type impurities in a direction at an angle of 70 degrees to the horizontal;
step four, as shown in fig. 6, removing the barrier layer 14, and forming a gate oxide layer 7 on the upper surface of the epitaxial layer 4;
step five, as shown in fig. 7, depositing conductive polysilicon;
step six, as shown in fig. 8, etching the conductive polysilicon to form conductive polysilicon 6;
step seven, as shown in fig. 9, etching the exposed gate oxide layer 7 to reduce the thickness of the exposed gate oxide layer 7, and then implanting P-type impurities, so that the mesa between the bottom of the trench and the trench is implanted with P-type impurities, and then implanting P-type impurities again on the mesa between the trenches;
step eight, as shown in fig. 10, performing a thermal annealing process to form a P-type body region 10, an N-type carrier storage layer 9 and a P-type well region 5, then injecting N-type impurities on the mesa between the trenches, and forming an N-type source region 12 after annealing;
step nine, as shown in fig. 11, depositing an insulating dielectric layer 8, then selectively etching and depositing the insulating dielectric layer 8 and the epitaxial layer 4 on the table top between the grooves, then injecting second conductivity type impurities, and forming a P-type source region 11 after annealing;
step ten, as shown in fig. 1, an emitter metal 13 is deposited on the surface of the device, then an N-type impurity and a P-type impurity are injected on the back of the device, a P-type collector region 2 and an N-type buffer layer 3 are formed after activation, and finally a collector metal 1 is formed.
Example 2
The manufacturing method of the embodiment 2 comprises the following steps:
step one, as shown in fig. 12, an N-type epitaxial layer 4 is provided;
step two, as shown in fig. 13, a barrier layer 14 is formed on the surface of the N-type epitaxial layer 4;
step three, as shown in fig. 14, selectively etching the barrier layer 14, then etching the N-type epitaxial layer 4 to form a gate trench, and then implanting N-type impurities in a direction at an angle of 70 degrees to the horizontal;
step four, as shown in fig. 15, forming a thicker oxide layer by thermal growth, wherein the step is to further narrow the width of the mesa region between the trenches;
step five, as shown in fig. 16, oxide 15 is removed, and then a gate oxide layer 7 is formed on the upper surface of the epitaxial layer 4;
step six, as shown in fig. 17, depositing conductive polysilicon;
step seven, as shown in fig. 18, etching the conductive polysilicon to form conductive polysilicon 6;
step eight, as shown in fig. 19, etching the exposed gate oxide layer 7 to reduce the thickness of the exposed gate oxide layer 7, and then implanting P-type impurities, so that the mesa between the bottom of the trench and the trench is implanted with P-type impurities, and then implanting P-type impurities again on the mesa between the trenches;
step nine, as shown in fig. 20, performing a thermal annealing process to form a P-type body region 10, an N-type carrier storage layer 9 and a P-type well region 5, then injecting N-type impurities only on the mesa between the trenches, and forming an N-type source region 12 after annealing;
step ten, as shown in fig. 21, an insulating dielectric layer 8 is deposited, then the insulating dielectric layer 8 and the epitaxial layer 4 are selectively etched and deposited on the table top between the grooves, then impurities of a second conductivity type are injected, and a P-type source region 11 is formed after annealing;
step eleven, as shown in fig. 2, an emitter metal 13 is deposited on the surface of the device, then an N-type impurity and a P-type impurity are injected on the back of the device, a P-type collector region 2 and an N-type buffer layer 3 are formed after activation, and finally a collector metal 1 is formed.
The IGBT structure obtained by the manufacturing method of the IGBT structure can improve the breakdown voltage of the device under the condition of the carrier storage layer, can effectively enhance the carrier storage effect, reduces the conduction voltage drop, and can reduce the capacitance and improve the EMI characteristics.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (15)
1. The IGBT structure comprises a collector metal (1), a first conductive type collector region (2), a second conductive type buffer layer (3) and a second conductive type epitaxial layer (4) are sequentially arranged on the collector metal (1), grooves are formed in the second conductive type epitaxial layer (4) at intervals, and the IGBT structure is characterized in that a first conductive type well region (5) is arranged at the bottom of each groove, a second conductive type carrier storage layer (9) is arranged in the second conductive type epitaxial layer (4) between every two adjacent grooves, a first conductive type body region (10) is arranged on the surface of the second conductive type carrier storage layer (9), a second conductive type source region (12) and a first conductive type source region (11) are arranged on the surface of the first conductive type body region (10), conductive polycrystalline silicon (6) is arranged on the side wall of each groove, an insulating medium layer (8) is arranged on the surface of the conductive polycrystalline silicon (6) and the surface of the second conductive type epitaxial layer (4), and an ohmic medium layer (8) is arranged on the surface of the second conductive type epitaxial layer (4), and the medium layer (13) is in contact with the second conductive type emitter region (12).
2. The IGBT structure according to claim 1, characterized in that two conductive polysilicon (6) are provided in each trench, and an insulating dielectric layer (8) is provided between the two conductive polysilicon (6).
3. An IGBT structure according to claim 2, characterized in that both conductive polysilicon (6) located in the same trench are connected to the gate potential.
4. The IGBT structure according to claim 2, characterized in that one conductive polysilicon (6) of the two conductive polysilicon (6) located in the same trench is connected to the gate potential and the other conductive polysilicon (6) is connected to the source potential.
5. The IGBT structure according to claim 2, characterized in that two conductive poly-silicon (6) located in the same trench are both connected to the source potential and that two conductive poly-silicon (6) in the trench adjacent or spaced apart from it are both connected to the gate potential.
6. The IGBT structure according to any one of claims 1 to 5, characterized in that a gate oxide layer (7) is provided between the conductive polysilicon (6) and the side walls of the trench, the conductive polysilicon (6) being provided on the surface of the gate oxide layer (7).
7. IGBT structure according to any one of claims 1 to 5, characterized in that the lower boundary of the second conductivity type carrier storage layer (9) is higher than the bottom of the trench.
8. The IGBT structure according to any one of claims 1 to 5, characterized in that the impurity concentration in the second conductivity type carrier storage layer (9) is in the range of 1e14cm -3 To 1e18cm -3 Between them.
9. The IGBT structure according to any one of claims 1 to 5, wherein the width of the trench ranges between 0.4 μm and 3 μm.
10. The IGBT structure according to any one of claims 1 to 5, characterized in that the trenches provided on the second conductivity type epitaxial layer (4) are spaced uniformly and a plurality of the trenches are parallel to each other.
11. The IGBT structure of any one of claims 1 to 5 wherein the first conductivity type comprises a P-type and the second conductivity type comprises an N-type.
12. The manufacturing method of the IGBT structure is characterized by comprising the following steps of:
providing a second conductivity type epitaxial layer;
forming a barrier layer on the surface of the second conductive type epitaxial layer, selectively etching the barrier layer, and etching the second conductive type epitaxial layer to form a groove;
implanting impurities of a second conductivity type into the trench in a direction at an angle a to the horizontal;
removing the barrier layer, and then forming a gate oxide layer on the surface of the second conductive type epitaxial layer;
depositing conductive polysilicon on the gate oxide layer, and forming the conductive polysilicon by etching;
etching the exposed gate oxide layer, including the gate oxide layer on the surface of the epitaxial layer between the two pieces of conductive polysilicon in the trench and the gate oxide layer on the surface of the epitaxial layer between the trenches, and then injecting first conductivity type impurities into the second conductivity type epitaxial layer;
performing a thermal annealing process to form a first conductive type body region, a second conductive type carrier storage layer and a first conductive type well region, injecting second conductive type impurities on the surface of the first conductive type body region, and forming a second conductive type source region after annealing;
depositing an insulating medium layer, selectively etching the deposited insulating medium layer and the second conductive type epitaxial layer on the surface of the first conductive type body region, then injecting first conductive type impurities, and forming a first conductive type source region after annealing;
depositing an emitter metal layer on the surface of the insulating medium layer;
injecting second-conductivity-type impurities and first-conductivity-type impurities into the surface of the second-conductivity-type epitaxial layer, which is away from the second-conductivity-type carrier storage layer, and sequentially forming a first-conductivity-type collector region and a second-conductivity-type buffer region;
and forming a collector metal on the surface of the second conductive type epitaxial layer, which faces away from the second conductive type carrier storage layer.
13. The method of fabricating an IGBT structure according to claim 12, further comprising, after the etching the exposed gate oxide layer including the gate oxide layer on the surface of the epitaxial layer between the two conductive polysilicon within the trench and the gate oxide layer on the surface of the epitaxial layer between the trenches, then implanting the first conductivity type impurity into the second conductivity type epitaxial layer:
and selectively implanting impurities of the first conductivity type into the surface of the epitaxial layer of the second conductivity type between the trenches for the second time.
14. The method of fabricating an IGBT structure of claim 12 wherein the angle a ranges from 1 ° to 89 °.
15. The method of manufacturing an IGBT structure according to any one of claims 12 to 14, wherein the first conductivity type comprises a P type and the second conductivity type comprises an N type.
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| CN107634095A (en) * | 2017-09-14 | 2018-01-26 | 全球能源互联网研究院 | Trench semiconductor power device and preparation method thereof |
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| CN107634095A (en) * | 2017-09-14 | 2018-01-26 | 全球能源互联网研究院 | Trench semiconductor power device and preparation method thereof |
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