CN106653828A - IGBT front structure and preparation method - Google Patents
IGBT front structure and preparation method Download PDFInfo
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- CN106653828A CN106653828A CN201611240210.3A CN201611240210A CN106653828A CN 106653828 A CN106653828 A CN 106653828A CN 201611240210 A CN201611240210 A CN 201611240210A CN 106653828 A CN106653828 A CN 106653828A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 33
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 238000002347 injection Methods 0.000 claims abstract description 12
- 239000007924 injection Substances 0.000 claims abstract description 12
- 238000002513 implantation Methods 0.000 claims description 19
- 238000000137 annealing Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000004857 zone melting Methods 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims 1
- 239000000725 suspension Substances 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention relates to an IGBT front structure and a preparation method. The IGBT front structure comprises an N base region, an N+ emitter region, a P base region, trench gates, a gate oxidation layer, an isolated oxidation layer, contact holes, a P+ region, a metal Al electrode, N+ suspension layers and P+ suspension rings. The N+ suspension layer is positioned below the P base region, and the depth of the N+ suspension layer does not exceed the bottom of the trench gates; the P+ suspension rings are positioned below the trench gates; and the formation of the N+ suspension layers is controlled by the intervals of the trench gates, the injection energy of the N+ suspension layers, and the temperature and time of gate sacrificial oxidation and gate oxidation. The intervals of the P+ suspension rings are controlled by the intervals of the trench gates, the injection energy of the P+ suspension layers, and the temperature and time of gate sacrificial oxidation and gate oxidation. The invention also provides a preparation method of the IGBT front structure. According to the IGBT front structure and the preparation method thereof, the conduction loss of an IGBT device is reduced, and the reliability of the IGBT device is improved.
Description
Technical field
The present invention relates to a kind of semiconductor components and devices structure, especially a kind of IGBT Facad structures and preparation method.
Background technology
IGBT（Igbt）It is by BJT（Bipolar junction transistor）And MOSFET（Metal-oxide-half
Conductor FET）The compound full-control type voltage driven type power semiconductor of composition.Compared with MOSFET, the advantage of IGBT
It is that with conductivity modulation effect, i.e., in break-over of device, dipole structure can be injected few from back side P+ collecting zones to N bases
Number carrier（Hole）, the electrical conductivity of N bases is modulated, the conducting resistance of N bases is effectively reduced, so as to reduce device
Conduction voltage drop and conduction loss, this be referred to as " conductivity modulation effect ".But the carrier inside N-type base and non-homogeneous point
Cloth, from the back side up, the closer to front（Near grid）, carrier concentration is lower, and conductivity modulation effect weakens, and which has limited device
The further reduction of part conduction voltage drop.In order to solve this problem, a kind of existing way is by N-type ion implanting and annealing
In the positive P bases of a device N+ layer formed below, referred to as " carrier accumulation layer ", it is attached that this extra play can improve grid
Near hole concentration reduces conduction voltage drop so as to improve device conductivity modulation effect, further.The injection of carrier accumulation layer is needed
It is limited in specific region, it is therefore desirable to increase by one layer of mask plate, increased cost；On the other hand, because " carrier is deposited
Reservoir " is located at region more deeper than P base, it is therefore desirable to higher ion implantation energy, higher annealing temperature and longer
Annealing time, increased cost and technology difficulty, also easily affect the reliability of device.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided a kind of IGBT Facad structures and preparation side
Method, it is not necessary to increase mask plate, it is not necessary to which high-energy injects, it is not necessary to extra to increase high temperature and prolonged annealing, so as to reach
To the conductivity modulation effect for improving device, reduce the conduction voltage drop and conduction loss of the device of device and improve device reliability
Purpose.
According to the technical scheme that the present invention is provided, the IGBT Facad structures, including the first conduction type base region, first leads
The front of electric type base arranges the second conduction type base region, and the surface of the second conduction type base region arranges metal electrode, the
Two conduction type base regions arrange groove structure；The upper end of the groove structure is extended in metal electrode, groove structure and metal
Arrange isolating oxide layer between electrode to be isolated, the lower end of groove structure is extended in the first conduction type base region, groove knot
The upper end both sides of structure arrange the first conduction type launch site, and metal electrode and the second conduction type base region are formed between groove structure
Contact hole, contact hole bottom arrange the second conductivity regions；It is characterized in that：Arrange in first conduction type base region
First conduction type superposed layer and the second conduction type suspended ring.
Further, the first conduction type superposed layer is located at more than the bottom of groove structure, and the second conduction type hangs
Floating ring is located at the bottom of groove structure.
Further, spacing is formed between the second conduction type suspended ring.
Further, the groove structure includes being arranged on ditch of the grid oxic horizon of trench wall with filling in the trench
Groove grid.
The preparation method of the IGBT Facad structures, is characterized in that, comprise the following steps：
（1）In the first conduction type base region by ion implanting and annealing formed the second conduction type base region, then by from
Son is infused in the second conduction type base region surface and forms the first conduction type thin layer；
（2）Then in the surface deposition oxide layer of the first conduction type thin layer, groove is formed by photoetching and first time etching, with
Oxide layer carries out the first conductive type ion injection to channel bottom for mask；The oxidation of first time grid sacrifice is carried out after injection,
The thermal process aoxidized by first time grid sacrifice, in channel bottom the first conduction type suspended ring is formed, and then will sacrifice oxygen
Change layer to etch away；
（3）Next with step（2）The oxide layer of middle deposit carries out second etching groove for mask, and the depth of etching is more than
The bottom of one conduction type suspended ring, then again with step（2）The oxide layer of middle deposit（13）Channel bottom is carried out for mask
Second conductive type ion injects；Then the oxidation of second grid sacrifice and gate oxidation are carried out, by this two steps thermal process,
Channel bottom forms the second conduction type suspended ring, while the first conduction type suspended ring connects to form the suspension of the first conduction type
Layer；By step（2）With（3）Middle grid sacrifice oxidation and the thermal process of gate oxidation, the first conduction type thin layer forms first
It is type launch site to lead, and after gate oxidation thermal process grid oxic horizon is formed；Then polysilicon is filled into groove and is carried out many
Crystal silicon is returned and forms trench-gate quarter, then removal step（2）The oxide layer of middle deposit；
（4）One layer of isolating oxide layer is deposited in front, contact hole is formed by photoetching and etching, the depth of contact hole is more than first
The depth of conduction type launch site；Then with isolating oxide layer as mask, the second conductive-type is formed by ion implanting and annealing
Type area, finally carries out positive metallization, forms metal electrode.
Further, the step（1）In the first conduction type base region intermediate ion Implantation Energy be 50keV ~ 200keV, note
Enter dosage for 1e12cm-2~1e14cm-2, annealing temperature is 1000 DEG C ~ 1200 DEG C, and annealing time is 50 minutes ~ 200 minutes；The
Two conduction type base region ion implantation energies are 30keV ~ 100keV, and implantation dosage is 1e14cm-2~1e16cm-2。
Further, the step（2）Middle first time etches the gash depth to be formed for 4 ~ 6um, and channel bottom carries out the
One conductive type ion Implantation Energy is 40keV ~ 100keV, and implantation dosage is 1e11cm-2~1e13cm-2；First time grid is sacrificial
Domestic animal oxidizing temperature is 950 DEG C ~ 1200 DEG C, and the time is 10 minutes ~ 100 minutes.
Further, the step（3）In second etching groove depth be 6 ~ 8um, groove width be 0.5 ~ 2um,
The spacing of groove is 1 ~ 3um；Channel bottom carries out the second conductive type ion Implantation Energy for 30keV ~ 100keV, implantation dosage
For 1e12cm-2~1e14cm-2；It is 950 DEG C ~ 1200 DEG C that second grid sacrifices oxidizing temperature, and the time is 10 minutes ~ 100 minutes；
Gate oxidation temperature is 1000 DEG C ~ 1200 DEG C, and the time is 30 minutes ~ 100 minutes）.
Further, the step（4）The depth of middle contact hole is 0.5 ~ 3um, and the width of contact hole is 0.5 ~ 1.5um；
Ion implantation energy is 20keV ~ 100keV, and implantation dosage is 1e14cm-2~1e16cm-2；Annealing temperature is 800 DEG C ~ 1000 DEG C,
Time is 10 minutes ~ 60 minutes.
Further, first conduction type base region is zone melting single-crystal silicon chip.
The present invention has advantages below：
（1）Using the mask and the depth of etching groove formation twice of etching groove, ion implanting is carried out to channel bottom and is formed,
The ion implanting of extra mask plate and high-energy is not needed, cost is saved；
（2）Using the oxidation of grid sacrifice and the thermal process of gate oxidation, N+ launch sites are form respectively, N+ superposed layers and P+ suspend
Ring, it is not necessary to increase extra thermal process, further saves cost；
（3）The N+ superposed layers formed by the cost effective method can reduce the purpose of break-over of device loss, by institute
Stating the P+ suspended rings of cost effective method formation can reduce the peak electric field of channel bottom, improve the reliability of device.
Description of the drawings
Fig. 1 is to form the schematic diagram of P bases and N+ thin layers in N bases front.
Fig. 2 is the schematic diagram for obtaining groove.
Fig. 3 is the schematic diagram that N+ suspended rings are formed in channel bottom.
Fig. 4 is the schematic diagram for proceeding etching to groove.
Fig. 5 is the schematic diagram for obtaining groove structure.
Fig. 6 is the schematic diagram to form contact hole.
Fig. 7 is the schematic diagram of IGBT Facad structures of the present invention.
Description of reference numerals：N bases 1, N+ launch sites 2, P bases 3, trench-gate 4, grid oxic horizon 5, isolating oxide layer
6th, contact hole 7, P+ areas 8, metal electrode 9, N+ superposed layers 10, P+ suspended rings 11, N+ thin layers 12, oxide layer 13, N+ suspended rings 14.
Specific embodiment
With reference to concrete accompanying drawing, the invention will be further described.
As shown in fig. 7, IGBT Facad structures of the present invention include N bases 1, the front of N bases 1 arranges P bases 3, P bases
The surface in area 3 arranges metal electrode 9, and in P bases 3 groove structure is arranged, and groove structure includes being arranged on the grid of trench wall
Oxide layer 5 and filling trench-gate 4 in the trench；The upper end of the groove structure is extended in metal electrode 9, groove structure
Arrange isolating oxide layer 6 between metal electrode 9 to be isolated, the lower end of groove structure is extended in N bases 1, groove structure
Upper end both sides N+ launch sites 2 are set, the contact hole 7 of metal electrode 9 and P bases 3 is formed between groove structure, in contact hole 7
Bottom arranges P+ areas 8；N+ superposed layers 10 and P+ suspended rings 11 are set in the N bases 1, and N+ superposed layers 10 are located at groove structure
Bottom more than, P+ suspended rings 11 be located at groove structure bottom, form spacing between P+ suspended rings 11, the spacing is tied by groove
The temperature and time of the spacing, the Implantation Energy of P+ suspended rings and the oxidation of grid sacrifice and gate oxidation of structure is controlled；The N+
Spacing, the Implantation Energy of N+ superposed layers 10 and the oxidation of grid sacrifice and the gate oxidation of groove structure is received in the formation of superposed layer 10
Temperature and time control.
The preparation method of IGBT Facad structures of the present invention, it is adaptable to which the back side is break-through（PT）Type, non-break-through（NPT）Type
Or field cut-off（FS）The IGBT device of type.N bases 1 are zone melting single-crystal silicon chip in the present embodiment.Specifically include following steps：
（1）As shown in figure 1, passing through ion implanting on N bases 1（Injection ion is boron, and Implantation Energy 50keV ~ 200keV is noted
Enter dosage 1e12cm-2~1e14cm-2）And annealing（1000 DEG C ~ 1200 DEG C of annealing temperature, annealing time 50 minutes ~ 200 minutes）Shape
Into P bases 3, then by ion implanting（Injection ion is arsenic, and Implantation Energy is 30keV ~ 100keV, implantation dosage 1e14cm-2
~1e16cm-2）Form N+ thin layers 12；
（2）As shown in Fig. 2 then in the surface deposition layer of oxide layer 13 of N+ thin layers 12, by photoetching and first time etching shape
Into groove（Gash depth is 4 ~ 6um）, N+ ion implantings are carried out to channel bottom by mask of oxide layer 13（Injecting ion is
Phosphorus, Implantation Energy is 40keV ~ 100keV, implantation dosage 1e11cm-2~1e13cm-2）；First time grid sacrifice is carried out after injection
Oxidation（950 DEG C ~ 1200 DEG C of temperature, 10 minutes ~ 100 minutes time）, the thermal process aoxidized by first time grid sacrifice, in ditch
Trench bottom forms N+ suspended rings 14, then etches away sacrificial oxide layer, as shown in Figure 3；
（3）Next with step（2）The oxide layer 13 of middle deposit carries out second etching groove for mask（Ditch groove depth after etching
Spend for 6 ~ 8um, groove width is 0.5 ~ 2um, and the spacing of groove is 1 ~ 3um）, the depth of etching requires more than the bottom of N+ suspended rings 14
Portion, then again with step（2）The oxide layer 13 of middle deposit carries out P+ ion implantings for mask to channel bottom（Injecting ion is
Boron, Implantation Energy 30keV ~ 100keV, implantation dosage 1e12cm-2~1e14cm-2）, as shown in Figure 4；Then second grid is carried out
Pole sacrifice oxidation（950 DEG C ~ 1200 DEG C of temperature, 10 minutes ~ 100 minutes time）And gate oxidation（1000 DEG C ~ 1200 DEG C of temperature,
30 minutes ~ 100 minutes time）, by this two steps thermal process, P+ suspended rings 11 are formed in channel bottom, while N+ suspended rings 14
Connection forms N+ superposed layers 10；By step（2）With（3）Middle grid sacrifice oxidation and the thermal process of gate oxidation, N+ thin layers 12
N+ launch sites 2 are formed, grid oxic horizon 5 is formed after gate oxidation thermal process；Then polysilicon is filled into groove and is carried out many
Crystal silicon is returned and forms trench-gate 4 quarter, then removal step（2）The oxide layer 13 of middle deposit, as shown in Figure 5；
（4）One layer of isolating oxide layer 6 is deposited in front, contact hole 7 is formed by photoetching and etching（Contact hole 7 after etching
Depth is 0.5 ~ 3um, and the width of contact hole 7 is 0.5 ~ 1.5um）, the depth of contact hole 7 requires more than the depth of N+ launch sites 2, such as
Shown in Fig. 6；Then with isolating oxide layer 6 as mask, by ion implanting（Injection ion be boron, Implantation Energy 20keV ~
100keV, implantation dosage 1e14cm-2~1e16cm-2）And annealing（800 DEG C ~ 1000 DEG C of temperature, 10 minutes ~ 60 minutes time）Shape
Into P+ areas 8, finally positive metallization is carried out using Al, form metal electrode 9, as shown in Figure 7.
Claims (10)
1. a kind of IGBT Facad structures, including the first conduction type base region, the front of the first conduction type base region arranges second and leads
Electric type base, the surface of the second conduction type base region arranges metal electrode, and in the second conduction type base region groove structure is arranged；
The upper end of the groove structure is extended in metal electrode, between groove structure and metal electrode arrange isolating oxide layer carry out every
From the lower end of groove structure is extended in the first conduction type base region, and the upper end both sides of groove structure arrange the first conduction type
Launch site, forms the contact hole of metal electrode and the second conduction type base region between groove structure, the setting the in contact hole bottom
Two conductivity regions；It is characterized in that：Arrange the first conduction type superposed layer and second in first conduction type base region to lead
Electric type suspended ring.
2. IGBT Facad structures as claimed in claim 1, is characterized in that：The first conduction type superposed layer is tied positioned at groove
More than the bottom of structure, the second conduction type suspended ring is located at the bottom of groove structure.
3. IGBT Facad structures as claimed in claim 1, is characterized in that：Between being formed between the second conduction type suspended ring
Away from.
4. IGBT Facad structures as claimed in claim 1, is characterized in that：The groove structure includes being arranged on trench wall
Grid oxic horizon and filling trench-gate in the trench.
5. a kind of preparation method of IGBT Facad structures, is characterized in that, comprise the following steps：
（1）In the first conduction type base region by ion implanting and annealing formed the second conduction type base region, then by from
Son is infused in the second conduction type base region surface and forms the first conduction type thin layer；
（2）Then in the surface deposition oxide layer of the first conduction type thin layer（13）, ditch is formed by photoetching and first time etching
Groove, with oxide layer（13）The first conductive type ion injection is carried out to channel bottom for mask；First time grid is carried out after injection
Oxidation is sacrificed, the thermal process aoxidized by first time grid sacrifice forms the first conduction type suspended ring, then in channel bottom
Sacrificial oxide layer is etched away；
（3）Next with step（2）The oxide layer of middle deposit（13）Second etching groove is carried out for mask, the depth of etching surpasses
The bottom of the first conduction type suspended ring is crossed, then again with step（2）The oxide layer of middle deposit（13）It is mask to channel bottom
Carry out the second conductive type ion injection；Then second grid sacrifice oxidation and gate oxidation are carried out, by this hot mistake of two steps
Journey, forms the second conduction type suspended ring, while the first conduction type suspended ring connects to form the first conductive-type in channel bottom
Type superposed layer；By step（2）With（3）Middle grid sacrifice oxidation and the thermal process of gate oxidation, the first conduction type thin layer shape
It is type launch site to lead into first, and after gate oxidation thermal process grid oxic horizon is formed；Then polysilicon is filled simultaneously into groove
Carry out polysilicon time and form trench-gate quarter, then removal step（2）The oxide layer of middle deposit（13）；
（4）One layer of isolating oxide layer is deposited in front, contact hole is formed by photoetching and etching, the depth of contact hole is more than first
The depth of conduction type launch site；Then with isolating oxide layer as mask, the second conductive-type is formed by ion implanting and annealing
Type area, finally carries out positive metallization, forms metal electrode.
6. the preparation method of IGBT Facad structures as claimed in claim 5, is characterized in that：The step（1）In it is first conductive
Type base intermediate ion Implantation Energy is 50keV ~ 200keV, and implantation dosage is 1e12cm-2~1e14cm-2, annealing temperature is
1000 DEG C ~ 1200 DEG C, annealing time is 50 minutes ~ 200 minutes；Second conduction type base region ion implantation energy be 30keV ~
100keV, implantation dosage is 1e14cm-2~1e16cm-2。
7. the preparation method of IGBT Facad structures as claimed in claim 5, is characterized in that：The step（2）Middle first time carves
The gash depth that erosion is formed is 4 ~ 6um, and channel bottom carries out the first conductive type ion Implantation Energy for 40keV ~ 100keV, note
Enter dosage for 1e11cm-2~1e13cm-2；First time grid sacrifice oxidizing temperature be 950 DEG C ~ 1200 DEG C, the time be 10 minutes ~
100 minutes.
8. the preparation method of IGBT Facad structures as claimed in claim 5, is characterized in that：The step（3）In second ditch
Groove etched depth is 6 ~ 8um, and groove width is 0.5 ~ 2um, and the spacing of groove is 1 ~ 3um；It is conductive that channel bottom carries out second
Types of ion Implantation Energy is 30keV ~ 100keV, and implantation dosage is 1e12cm-2~1e14cm-2；Second grid sacrifice oxidation
Temperature is 950 DEG C ~ 1200 DEG C, and the time is 10 minutes ~ 100 minutes；Gate oxidation temperature is 1000 DEG C ~ 1200 DEG C, and the time is 30
Minute ~ 100 minutes）.
9. the preparation method of IGBT Facad structures as claimed in claim 5, is characterized in that：The step（4）Middle contact hole
Depth is 0.5 ~ 3um, and the width of contact hole is 0.5 ~ 1.5um；Ion implantation energy is 20keV ~ 100keV, and implantation dosage is
1e14cm-2~1e16cm-2；Annealing temperature is 800 DEG C ~ 1000 DEG C, and the time is 10 minutes ~ 60 minutes.
10. the preparation method of IGBT Facad structures as claimed in claim 5, is characterized in that：First conduction type base region
For zone melting single-crystal silicon chip.
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| CN201611240210.3A CN106653828A (en) | 2016-12-29 | 2016-12-29 | IGBT front structure and preparation method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109443295A (en) * | 2018-10-28 | 2019-03-08 | 北京工业大学 | A kind of test method for automotive grade igbt chip surface A l metalization layer roughness |
| WO2022222610A1 (en) * | 2021-04-20 | 2022-10-27 | 无锡华润上华科技有限公司 | Trench gate igbt device and fabrication method therefor |
| WO2023193370A1 (en) * | 2022-04-08 | 2023-10-12 | 苏州东微半导体股份有限公司 | Igbt device and manufacturing method therefor |
Citations (4)
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| WO2022222610A1 (en) * | 2021-04-20 | 2022-10-27 | 无锡华润上华科技有限公司 | Trench gate igbt device and fabrication method therefor |
| WO2023193370A1 (en) * | 2022-04-08 | 2023-10-12 | 苏州东微半导体股份有限公司 | Igbt device and manufacturing method therefor |
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