WO2023193370A1

WO2023193370A1 - Igbt device and manufacturing method therefor

Info

Publication number: WO2023193370A1
Application number: PCT/CN2022/107317
Authority: WO
Inventors: 范让萱; 缪进征; 王鹏飞; 刘磊; 龚轶
Original assignee: 苏州东微半导体股份有限公司
Priority date: 2022-04-08
Filing date: 2022-07-22
Publication date: 2023-10-12
Also published as: CN116936626A

Abstract

Provided in the the embodiments of the present application is an IGBT device, which comprises an n-type semiconductor layer, wherein the following are formed in the n-type semiconductor layer: a p-type collector region; an n-type field cut-off region located on the p-type collector region; an n-type drift region located on the n-type field cut-off region; a plurality of trenches extending into the n-type drift region, each trench comprising a first trench at an upper portion and a second trench at a lower portion, and the width of the first trenches being greater than the width of the second trenches; p-type columns located in the second trenches; insulating dielectric layers located in the first trenches and located above the p-type columns; gate oxide layers and gate electrodes which are located in the first trenches and close to the side wall positions of the first trenches; p-type body regions located between the adjacent first trenches; n-type emitter regions located in the p-type body regions; and n-type charge storage regions located below the p-type body regions and between the adjacent trenches.

Description

IGBT device and manufacturing method

This application claims priority to the Chinese patent application with application number 202210366889.X filed with the China Patent Office on April 8, 2022. The entire content of this application is incorporated into this application by reference.

Technical field

This application belongs to the technical field of IGBT devices, and relates to, for example, an IGBT device and a manufacturing method thereof.

Background technique

The Insulated Gate Bipolar Transistor (IGBT) device is a device composed of a MOS transistor and a bipolar transistor. Its input is a MOS transistor and its output is a PNP transistor. It combines these two devices. It has the characteristics of low driving power and fast switching speed of MOS transistors, as well as the characteristics of bipolar transistors with low saturation voltage and large capacity. It has been increasingly widely used in modern power electronics technology, especially occupying the It has achieved a dominant position in the application of large and medium power tubes at higher frequencies. Related art field-stop IGBT (FS-IGBT) devices use a single deep trench MOS structure as the main structure of the active region, and reduce device saturation voltage drop and turn-off loss by increasing the doping concentration of the n-type charge storage region. However, in the reverse bias state, the higher the doping concentration at the n-type charge storage region, the smaller the breakdown voltage of the device. The influence of the doping concentration of the n-type charge storage region on the breakdown voltage limits the optimization of the saturation voltage drop and turn-off loss of the FS-IGBT device by adjusting the doping concentration of the n-type charge storage region.

Contents of the invention

This application provides an IGBT device and a manufacturing method thereof to optimize the saturation voltage drop and turn-off loss of the IGBT device.

An IGBT device provided by an embodiment of the present application includes an n-type semiconductor layer formed within the n-type semiconductor layer:

p-type collector region;

an n-type field stop region located above the p-type collector region;

an n-type drift region located above the n-type field cutoff region;

Several trenches extending into the n-type drift region, each trench including an upper first trench and a lower second trench, the width of the first trench being greater than the width of the second trench width;

A p-type pillar located in the second trench;

an insulating dielectric layer located within the first trench and above the p-type pillar;

a gate oxide layer and a gate electrode located within the first trench and close to the sidewalls of the first trench;

A p-type body region located between adjacent first trenches, and an n-type emitter region located within the p-type body region;

An n-type charge storage region is located below the p-type body region and between adjacent trenches.

A method of manufacturing an IGBT device according to an embodiment of the present application includes:

Form a hard mask layer on the provided n-type semiconductor layer, define the position of the trench through a photolithography process, and etch the hard mask layer to expose the n-type semiconductor layer;

Using the hard mask layer as a mask, perform anisotropic etching and isotropic etching on the n-type semiconductor layer to form a first trench in the n-type semiconductor layer;

Using the hard mask layer as a mask, perform n-type ion implantation and annealing on the n-type semiconductor layer through the first trench, and form a layer located at the bottom of the first trench in the n-type semiconductor layer. n-type charge storage area;

forming a gate oxide layer on the surface of the first trench;

Forming a gate polysilicon layer and etching back the gate polysilicon layer using the hard mask layer as a mask to form a gate electrode at the sidewall position of the first trench;

Form a protective oxide layer on the surface of the gate electrode;

Use the hard mask layer as a mask to etch away the gate oxide layer at the bottom of the first trench, and continue to etch the n-type semiconductor layer to form a second trench below the first trench. groove;

Performing epitaxial growth of p-type polysilicon and etching back the p-type polysilicon using the hard mask layer as a mask to form p-type pillars in the second trench;

Depositing an insulating layer and etching back the insulating layer using the hard mask layer as a mask to form an insulating dielectric layer located above the p-type pillar in the first trench;

The hard mask layer is etched away, a p-type body region is formed in the n-type semiconductor layer, and an n-type emitter region is formed in the p-type body region.

Description of the drawings

Figure 1 is a schematic cross-sectional structural diagram of an embodiment of the IGBT device of the present application;

2 to 9 are schematic cross-sectional structural diagrams of main process nodes of an embodiment of the manufacturing method of an IGBT device of the present application.

Detailed ways

The technical solution of the present application will be completely described in a specific manner in conjunction with the accompanying drawings in the embodiments of the present application.

Figure 1 is a schematic cross-sectional structural diagram of an embodiment of an IGBT device provided by the present application. As shown in Figure 1, the IGBT device of the present application includes an n-type semiconductor layer 20, and a p-type collector formed in the n-type semiconductor layer 20. Region 41, an n-type field stop region 42 located above the p-type collector region 41, and an n-type drift region 43 located above the n-type field stop region 42.

There are several trenches extending into the n-type drift region 43. For convenience of illustration, only two trench structures are shown in the embodiment of the present application as an example. The groove includes an upper first groove and a lower second groove, and the width of the first groove is greater than the width of the second groove. The p-type pillar 25 is located in the second trench. The p-type pillar 25 can be located only in the second trench (as shown in FIG. 1 ), or the p-type pillar 25 can extend upward from the second trench to inside the first trench (not shown in the figure). The insulating dielectric layer 26 located in the first trench and above the p-type pillar 25 , the gate oxide layer 22 and the gate electrode 23 located in the first trench and close to the sidewall of the first trench. In the cross-sectional structure shown in FIG. 1 , the gate electrode 23 is located on both sides of the insulating dielectric layer 26 . Alternatively, the gate electrode 23 can surround the insulating dielectric layer 26 in the first trench. It should be noted that the IGBT device provided by the embodiment of the present application may also include a protective oxide layer (not shown in the figure) between the gate electrode 23 and the insulating dielectric layer 26. The protective oxide layer is used to etch the gate oxide layer. 22 to protect the gate 23. Alternatively, it can also be understood that the insulating dielectric layer 26 includes insulating layers of multiple different materials. The insulating dielectric layer on the side close to the gate 23 can be used as a protective oxide layer to protect the gate during the process of etching the gate oxide layer 22 . twenty three.

The p-type body region 27 located between adjacent first trenches, the n-type emitter region 28 located within the p-type body region 27, and the n-type body region 28 located below the p-type body region 27 and between adjacent trenches. type charge storage area 21.

In the IGBT device of the present application, a p-type pillar is arranged in the second trench, and a superjunction structure is formed between the p-type pillar and the n-type drift region, which can enhance the conductance modulation effect of the drift region and improve the withstand voltage of the IGBT device, thereby enabling By increasing the doping concentration of the n-type charge storage region, the saturation voltage drop and turn-off loss of the IGBT device can be optimized.

2 to 9 are schematic cross-sectional structural diagrams of main process nodes of an embodiment of the manufacturing method of an IGBT device of the present application. As shown in Figures 2 to 9, a manufacturing method of an IGBT device in this application includes:

First, as shown in Figure 2, a hard mask layer 30 is formed on the provided n-type semiconductor layer 20, and the position of the trench is defined through a photolithography process. The process includes: forming a layer of photolithography on the hard mask layer 30. Then, the hard mask layer 30 is etched to expose the n-type semiconductor layer 20, and then the photoresist is removed.

Next, as shown in FIG. 3 , using the hard mask layer 30 as a mask, anisotropic etching and isotropic etching are performed on the n-type semiconductor layer 20 . The anisotropic etching is used to etch n downward. For the n-type semiconductor layer 20, isotropic etching is used to etch the n-type semiconductor layer 20 in various directions to form the first trench 31 in the n-type semiconductor layer 20. The first trench 31 can be formed through isotropic etching. The width is greater than the opening width in the hard mask layer 30 .

Next, as shown in FIG. 4 , using the hard mask layer 30 as a mask, n-type ions are implanted and annealed into the n-type semiconductor layer 20 through the first trench 31 , and a first layer is formed in the n-type semiconductor layer 20 . In the n-type charge storage area 21 at the bottom of the trench 31, by controlling the temperature and time of annealing, n-type ions can be diffused to a preset position, that is, the formation area of the n-type charge storage area 21 is controlled.

Next, as shown in FIG. 5 , a gate oxide layer 22 is formed on the surface of the first trench, and then a gate polysilicon layer is formed and the formed gate polysilicon layer is processed using the hard mask layer 30 as a mask. At this moment, the gate electrode 23 is formed at the sidewall position of the first trench 31.

Next, as shown in FIG. 6 , a protective oxide layer 24 is formed on the surface of the gate electrode 23 . The protective oxide layer 24 is used to protect the gate electrode 23 from etching during the etching of the gate oxide layer 22 , and then is formed with a hard mask. The film layer 30 serves as a mask to etch away the gate oxide layer 22 at the bottom of the first trench, and continues to etch the n-type semiconductor layer 20 to form a second trench 32 below the first trench.

Next, as shown in FIG. 7 , p-type polysilicon is epitaxially grown and the formed p-type polysilicon is etched back using the hard mask layer 30 as a mask to form p-type pillars 25 in the second trench. By controlling this etching process, the p-type pillar 25 can be positioned only in the second trench, or the p-type pillar 25 can be positioned in the second trench and extend upward into the first trench.

Next, as shown in FIG. 8 , an insulating layer is deposited and etched back using the hard mask layer as a mask to form an insulating dielectric layer 26 above the p-type pillar 25 in the first trench. , and then etch away the hard mask layer. Since the gate electrode 23 and the insulating dielectric layer 26 are both formed through a self-alignment process, the gate electrode 23 surrounds the insulating dielectric layer 26 in the first trench.

Next, as shown in FIG. 9 , a p-type body region 27 is formed in the n-type semiconductor layer 20 , and an n-type emitter region 28 is formed in the p-type body region 27 . It should be noted that an annealing process is required when forming the p-type body region 27 and the n-type emitter region 28. At this time, the n-type ions in the n-type charge storage region 21 will further diffuse and be located in two adjacent p-type regions. The n-type charge storage areas 22 between the type pillars 25 can be connected to form a whole after diffusion (as shown in FIG. 9). Alternatively, they can also be not connected after diffusion (this structure is listed in the embodiment of the present application). not shown).

Finally, the manufacturing method of the IGBT device according to the embodiment of the present application also includes: forming an interlayer insulating layer on the surface of the n-type semiconductor layer, and forming source metal and gate metal; forming an n-type field at the bottom of the n-type semiconductor layer The cutoff region and the p-type collector region; and the collector metal is formed on the bottom surface of the n-type semiconductor layer. The above processes are all common processes in the industry and will not be shown or explained in the embodiments of this application.

Claims

An insulated gate bipolar transistor IGBT device, including an n-type semiconductor layer formed within the n-type semiconductor layer:

p-type collector region;

an n-type field stop region located above the p-type collector region;

an n-type drift region located above the n-type field cutoff region;

Several trenches extending into the n-type drift region, each trench including an upper first trench and a lower second trench, the width of the first trench being greater than the width of the second trench width;

A p-type pillar located in the second trench;

an insulating dielectric layer located within the first trench and above the p-type pillar;

a gate oxide layer and a gate electrode located within the first trench and close to the sidewalls of the first trench;

A p-type body region located between adjacent first trenches, and an n-type emitter region located within the p-type body region;

An n-type charge storage region is located below the p-type body region and between adjacent trenches.
The IGBT device of claim 1, wherein the p-type pillar extends upward from the second trench to the first trench.
The IGBT device of claim 1, wherein the gate surrounds the insulating dielectric layer in the first trench.
A method for manufacturing an insulated gate bipolar transistor IGBT device, including:

Form a hard mask layer on the provided n-type semiconductor layer, define the position of the trench through a photolithography process, and etch the hard mask layer to expose the n-type semiconductor layer;

Using the hard mask layer as a mask, perform anisotropic etching and isotropic etching on the n-type semiconductor layer to form a first trench in the n-type semiconductor layer;

Using the hard mask layer as a mask, perform n-type ion implantation and annealing on the n-type semiconductor layer through the first trench, and form a layer located at the bottom of the first trench in the n-type semiconductor layer. n-type charge storage area;

forming a gate oxide layer on the surface of the first trench;

Forming a gate polysilicon layer and etching back the gate polysilicon layer using the hard mask layer as a mask to form a gate electrode at the sidewall position of the first trench;

Form a protective oxide layer on the surface of the gate electrode;

Use the hard mask layer as a mask to etch away the gate oxide layer at the bottom of the first trench, and continue to etch the n-type semiconductor layer to form a second trench below the first trench. groove;

Performing epitaxial growth of p-type polysilicon and etching back the p-type polysilicon using the hard mask layer as a mask to form p-type pillars in the second trench;

Depositing an insulating layer and etching back the insulating layer using the hard mask layer as a mask to form an insulating dielectric layer located above the p-type pillar in the first trench;

The hard mask layer is etched away, a p-type body region is formed in the n-type semiconductor layer, and an n-type emitter region is formed in the p-type body region.
The method of manufacturing an IGBT device according to claim 4, further comprising: forming an interlayer insulating layer, source metal and gate metal on the surface of the n-type semiconductor layer.
The method of manufacturing an IGBT device according to claim 5, further comprising: forming an n-type field stop region and a p-type collector region at the bottom of the n-type semiconductor layer.
The method of manufacturing an IGBT device according to claim 6, further comprising: forming a collector metal on a bottom surface of the n-type semiconductor layer.