CN117832273A

CN117832273A - Low-tunneling leakage current power device and manufacturing method thereof

Info

Publication number: CN117832273A
Application number: CN202311748601.6A
Authority: CN
Inventors: 孙伟锋; 曹钧厚; 付浩; 魏家行; 刘斯扬; 时龙兴
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2023-12-19
Filing date: 2023-12-19
Publication date: 2024-04-05

Abstract

The invention discloses a power device with low tunneling leakage current and a manufacturing method thereof. The device includes a substrate and a first conductivity type drift region thereon; the trench is arranged above the drift region, the drift region and the upper side of the trench are provided with trenches, heterogeneous material regions are arranged on two sides of the trench, a second conductive type voltage-withstanding region is arranged below the heterogeneous material regions, the voltage-withstanding region is separated from the trench by the drift region, gate electrodes are arranged in the trench, symmetrically distributed buried layer electrodes are arranged below the gate electrodes, the trench, the gate electrodes and the buried layer electrodes are respectively separated by dielectric layers, and a source electrode is arranged above the heterogeneous material regions and separated from the gate electrodes in the trench by the dielectric layers; a drain electrode is arranged below the substrate. The invention has the advantages that the device is conducted by the tunneling principle, the on-resistance is effectively reduced, and the latch-up effect caused by the parasitic triode is avoided. The electric field intensity of a tunneling point during reverse blocking is reduced by the introduction of the buried electrode, so that reverse leakage current is reduced. Meanwhile, the switching speed of the device is also improved.

Description

Low-tunneling leakage current power device and manufacturing method thereof

Technical Field

The invention belongs to the technical field of semiconductor power devices, and particularly relates to a power device with low tunneling leakage current and a manufacturing method thereof.

Background

The power semiconductor device plays a role in the power electronics industry, has wide application in automobiles, household appliances, high-speed rails and power grids, and has larger and larger requirements for the power device, however, the traditional power device has a plurality of defects, such as: the on-resistance is large, the threshold voltage is high, the subthreshold swing is large, the manufacturing process is complex, the doping process is easy to generate damage to form traps, the device performance is influenced, and the like.

A metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) is a semiconductor device that uses a gate electrode to regulate the carrier concentration of the underlying semiconductor surface and to control the switching of the device. However, the MOSFET device has unavoidable problems such as device burnout caused by high voltage drop of the body diode and parasitic triode conduction after breakdown due to the existing material band structure and device structure. A conventional MOSFET has a P-type region disposed around an n+ source region, the P-type region having a width of about half the width of a cell due to a limitation of a channel length; the body diode of the conventional MOSFET device is a PN junction, the conduction voltage drop is limited by materials, and the loss in the reverse freewheeling period of the device can not be reduced. The conventional MOSFET has an N-type source region due to the complex structure, and a parasitic NPN triode formed by the N-type source region, a P-type body region and an N-type drift region is arranged in the device structure, so that when the current is large, the voltage drop on the body region resistance is large, and the parasitic triode is conducted to cause secondary breakdown or latch-up effect.

Disclosure of Invention

The invention aims to: the invention aims to provide a power device with low tunneling leakage current and a manufacturing method thereof. Compared with the traditional MOSFET, the device has a brand new conduction mechanism, namely, the device is controlled to be turned on and off by adjusting the energy band bending of the heterojunction contact interface. Compared with the traditional MOSFET, the structure has smaller subthreshold swing due to the change of a conduction mechanism and structural design, effectively avoids the reliability problem of a parasitic triode, and reduces the conduction voltage drop of a body diode by means of the conduction of a heterojunction diode. According to the invention, the buried layer electrode below the trench gate is introduced, so that the concentration of an electric field at a tunneling point is effectively relieved, and the advanced breakdown at the tunneling point is avoided. In addition, the introduction of the buried layer electrode effectively reduces the capacitance opposite to the gate-drain electrode on the premise of controlling the gate-source capacitance as much as possible, and reduces the switching time of the device.

The technical scheme is as follows: the invention relates to a low-tunneling leakage current power device, which comprises a first conductive type semiconductor substrate, wherein a drain electrode is arranged on the lower surface of the first conductive type semiconductor substrate, and a drift region is arranged on the upper surface of the first conductive type semiconductor substrate; a groove is arranged above the drift region, a grid electrode and a buried layer electrode are arranged in the groove, and the grid electrode is positioned above the buried layer electrode and is separated by a third dielectric region; a second dielectric region is filled between the buried layer electrode and the side wall of the groove; the gate electrode and the side wall of the groove and the outward extending parts of the two sides above the gate electrode and the groove are filled with gate dielectric areas; heterogeneous material areas are respectively arranged above the drift areas on two sides of the groove; the upper part of the heterogeneous material region is respectively in contact connection with a source electrode and a gate dielectric region, and the source electrode (5) is positioned at the top of the whole power device; a fourth medium region is filled between the grid electrode and the source electrode; the lower part of the heterogeneous material region is in contact connection with a pressure-resistant region, and the pressure-resistant region is separated from the groove by a drift region.

Further, the number of the buried layer electrodes is two, the two buried layer electrodes are symmetrically distributed on two sides of the bottom of the groove by the center line of the groove, and the two buried layer electrodes are separated by the first dielectric region.

Further, the buried layer electrode has a shape including an L-shape, a square shape, a rectangle shape, a circular arc shape and a fan shape.

Further, the potential of the buried layer electrode comprises floating, and is shared with the source electrode through a layout design or an external circuit mode or is independently provided through electrode extraction.

Further, the voltage-resistant region is subjected to voltage resistance in the device blocking state, and the doping concentration is typically 1×10 ¹⁴ -1×10 ²⁰ cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The depth occupied by the pressure-resistant region in the drift region is not smaller than the groove; the material selected for the voltage-resistant region is the same material of the second conductivity type as the drift region or various materials which are different from the drift region but can form a space charge region near a metallurgical junction in contact with the drift region, and specifically comprises: polycrystalline silicon, monocrystalline silicon, graphene, molybdenum disulfide, silicon carbide, diamond, gallium oxide, or gallium nitride. When a certain potential difference exists between the source electrode and the drain electrode, the width of the space charge region changes, the current path is limited, and the electric field intensity at the bottom of the groove is reduced.

Further, the bottom surface of the groove is lower than the contact surface of the heterogeneous material region and the drift region, and the bottom surface of the grid electrode in the groove is also lower than the contact surface of the heterogeneous material region and the drift region.

Further, the heterogeneous material region may specifically include: polycrystalline silicon, single crystal silicon, nickel, titanium, aluminum, copper, silver, gold, molybdenum, silicon oxide, silicon nitride, aluminum oxide, graphene, molybdenum disulfide, silicon carbide, diamond, gallium oxide, or gallium nitride; which is capable of band bending after contact with the drift region and creates a potential barrier, the barrier height being capable of being varied by varying the voltage applied by the control gate and thereby adjusting the magnitude of the current flowing through the source and drain electrodes.

Further, the thickness of the second dielectric region and the thickness of the gate dielectric region are adjustable, and the thickness of the second dielectric region and the thickness of the gate dielectric region may be equal or unequal, i.e., the thickness of the second dielectric region may be greater than, less than or equal to the thickness of the gate dielectric region.

Further, the first conductivity type drift region material is made of silicon carbide, gallium oxide, gallium nitride, silicon or diamond by a process of growth, thermal diffusion and ion implantation to form doping, wherein the typical impurity concentration value is 1×10 ¹³ ～1×10 ¹⁹ cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The material of the substrate is silicon carbide, gallium nitride, gallium oxide, silicon or diamond, and the substrateCan be selected as the first to point type or the second conductivity type, i.e. the substrate can be selected as N-type doped or P-type doped and has a doping concentration in the range of 1×10 ¹⁸ ～1×10 ²² cm ^-3 。

Further, the source electrode, the gate electrode, the buried layer electrode and the drain electrode are made of conductive materials, including polysilicon, nickel, titanium, aluminum, copper, silver and gold; the fourth dielectric region, the gate dielectric region, the second dielectric region, the third dielectric region and the first dielectric region are made of various nitrogen-containing oxygen-containing compounds of silicon, aluminum oxide, molybdenum dioxide, zirconium oxide and nickel oxide, the first conductive type semiconductor substrate is N-type doped, and the voltage-resistant region is P-type doped; or the first conductive type semiconductor substrate is doped with P type, and the voltage-resistant area is doped with N type.

The invention also discloses a manufacturing method of the low-tunneling leakage current power device, which comprises the following steps:

step 1, taking a first conductive type substrate, forming an epitaxial drift layer with the same conductive type on one surface of the substrate, and implanting a voltage-withstanding region with a second conductive type into the N-type epitaxial layer by using an ion implantation process;

step 2, depositing a layer of heterogeneous material source region on the surface of the epitaxial drift layer by using a CVD process;

step 3, etching and forming a groove above the heterogeneous material source region and the epitaxial drift layer by using an ion etching process;

step 4, depositing a second dielectric layer in the groove by using a thermal growth or deposition process;

step 5, depositing a buried layer electrode in the groove by using a deposition and sputtering process, and controlling the upper surface position of the electrode by one-time etching;

step 6, thinning the thickness of the middle part of the buried layer electrode through secondary etching;

step 7, forming two separated buried layer electrodes through three times of etching;

step 8, filling a dielectric layer in the groove again by using a deposition or growth mode to form a first dielectric region isolated between the two buried layers;

step 9, removing the heterogeneous material surface and the medium layer at the upper part of the inner part of the groove through medium layer etching to form a third medium layer for isolating the buried layer electrode from the grid electrode;

step 10, redeposit dielectric material on the inner wall of the groove and the surface of the heterogeneous material to form a gate dielectric region;

step 11, filling conductive materials of metal or polysilicon in the grooves by using deposition and sputtering modes, and forming a grid electrode;

step 12, depositing a dielectric layer on the surface, and forming a fourth dielectric region and a contact hole exposing the heterogeneous material region by etching the dielectric layer above the heterogeneous material region;

step 13, forming a metal area on the surface plane in a deposition, sputtering and evaporation mode, and forming a second electrode area by filling an opening part of a fourth medium area on the surface, and contacting with the heterogeneous material area below; a metal region is also formed on the back substrate and serves as a first electrode region.

The beneficial effects are that: compared with the prior art, the invention has the following remarkable advantages:

1. compared with a common metal-semiconductor field effect transistor (MOSFET), the power device with low tunneling leakage current has the advantages that a tunneling conduction mode is adopted without depending on inversion of a channel region, so that lower subthreshold swing can be realized, leakage current under low voltage is reduced, and loss of the device in a conduction process is reduced. As shown in fig. 20, the sub-threshold swing is significantly reduced during turn-on compared to conventional MOSFET structures.

2. When the device is turned off, the second conductive type voltage-withstanding region below the heterogeneous material region and the first conductive type drift region form a space charge layer as shown in fig. 4, wherein the boundary of the formed space charge region layer is shown as a broken line 15 in fig. 4, and the space charge region expands and reduces the concentration of carriers in the space charge region in a drain-source high-voltage state, so that the reverse leakage current of the device is effectively reduced, and the blocking characteristic of the device is improved. As shown in fig. 21, the structure of the present invention has significantly reduced drain current in a withstand voltage state and improved device blocking performance compared to the conventional MOSFET structure.

3. The heterojunction contact is formed between the heterogeneous material region and the drift layer in the device structure. The structure improves the third quadrant characteristic of the device, has lower starting voltage compared with the conventional MOSFET body diode freewheeling, reduces reverse recovery current of the device in the switching process, reduces dynamic power consumption of the device, and has better switching characteristic.

4. Compared with a conventional MOSFET, the cell width of the power device can be remarkably reduced. A conventional MOSFET has a P-type region disposed around an n+ source region, the P-type region having a width of about half the width of a cell due to a limitation of a channel length; the device is not limited by a channel due to different conductive principles, so that narrower cell size can be realized under the condition of the same JFET region width, thereby having lower on-resistance and reducing the static power consumption of the device. And secondly, the channel of the device is a triple contact surface of the first source region, the N-type epitaxial layer and the gate oxide layer, a conventional MOSFET channel is not needed, the manufacturing process of the device is simplified, the cost of the device is reduced, and the number of cells is greatly increased in a unit area.

5. Compared with the MOSFET, the invention can effectively avoid secondary breakdown and latch-up effect. The device has simple structure, does not have an N-type source region, does not have a parasitic triode determined by the structure, further does not generate secondary breakdown and latch-up effect, effectively avoids failure possibility caused by the parasitic structure, and improves the reliability of the device.

6. The buried electrode structure below the grid electrode is adopted, and the buried electrode can float, short-circuit with the source electrode or independently provide potential, so that the electric field lines can be contracted at the position when in reverse voltage resistance, the electric field line density degree at the tunneling point is reduced, the electric field intensity at the tunneling point is effectively reduced, the tunneling point is protected, and breakdown of the tunneling point when in reverse voltage resistance is avoided.

7. According to the device structure, the buried electrode structure is additionally arranged below the grid electrode, the buried electrode is connected with the source electrode through an external circuit or a layout structure, the facing area of the grid electrode and the drain electrode is reduced, the miller capacitance Cgd of the MOSFET is effectively reduced, the capacitance charging time of the device in the conducting process is reduced, and the switching speed of the device is increased. Helping to reduce switching losses of the device in switching power supply applications.

8. According to the invention, the buried layer electrodes are separated and made into symmetrical L shapes, so that the opposite areas of the grid electrode and the buried layer electrodes are reduced, the thickness of a medium between the grid electrode and the buried layer electrodes is increased, the increase of the grid source capacitance Cgs introduced by the buried layer electrodes is effectively inhibited, the switching time of the device is reduced, and the device has obvious effect on reducing the loss in the switching process of the device.

In conclusion, the third quadrant characteristic of the device is improved, and the dynamic power consumption of the device is reduced; the cell width of the power device is obviously reduced, the on-resistance is lower, and the static power consumption of the device is reduced; the electric field intensity at the tunneling point is effectively reduced by the introduction of the buried electrode, the breakdown of the tunneling point is avoided, and the tunneling leakage current is effectively reduced. In addition, the gate drain and gate source capacitance of the device are reduced, the built-in resistor-capacitor buffer is introduced, the switching loss is further reduced, and the switching peak and oscillation are suppressed.

Drawings

Fig. 1 is a cell structure diagram of a low tunneling leakage current power device according to an embodiment of the present invention.

Fig. 2 is a diagram of another low tunneling leakage power device cell structure according to an embodiment of the present invention.

Fig. 3 is a cell structure diagram of a power device with a low tunneling leakage current according to another embodiment of the present invention.

Fig. 4 is a schematic diagram of the space charge region of the P-type region of the present invention when the device is turned off.

Fig. 5 is a schematic diagram of a conventional vertical channel trench gate tunneling silicon carbide power semiconductor device in which electric field lines are concentrated at a tunneling point when reverse withstand voltage is applied.

Fig. 6 is a schematic diagram of the present invention for reducing the electric field strength at the tunneling point by adding buried electrodes.

Fig. 7 is a schematic diagram of a process step of forming a p+ region on an upper surface of an epitaxial layer using an ion implantation process according to the manufacturing method of the present invention.

Fig. 8 is a schematic diagram of the process steps for depositing regions of heterogeneous material on the upper surface of an epitaxial layer in accordance with the fabrication method of the present invention.

Fig. 9 is a schematic diagram of a process step of etching a hetero-material region and forming a trench in a drift region according to the manufacturing method of the present invention.

Fig. 10 is a schematic diagram of a process step of depositing a second dielectric layer inside a trench in the manufacturing method of the present invention.

Figure 11 is a schematic illustration of the process steps of the fabrication method of the present invention for depositing and etching a buried layer within a trench.

Fig. 12 is a schematic diagram of a process step of secondary etching of a buried electrode in the manufacturing method of the present invention.

Fig. 13 is a schematic diagram of the process steps of three etching the buried electrode and forming an L-shaped buried electrode according to the manufacturing method of the present invention.

Fig. 14 is a schematic diagram of a process step of filling the trench with a dielectric material and forming a first dielectric layer isolation between buried electrodes in the manufacturing method of the present invention.

FIG. 15 is a schematic diagram of the process steps for etching back the top dielectric material in the trench on the surface of the hetero-material by the fabrication method of the present invention.

Fig. 16 is a schematic diagram of a process step of redeposition a dielectric material to form a gate dielectric layer in the manufacturing method of the present invention.

Fig. 17 is a schematic diagram of a process step of redeposition of conductive material and etching to form a gate electrode in the fabrication method of the present invention.

Fig. 18 is a schematic view of a process step of the fabrication method of the present invention for depositing a dielectric layer over the gate and forming a fourth dielectric region for gate-source isolation.

Fig. 19 is a schematic view of the process steps for fabricating source and drain contact electrodes on the surface and back side of the fabrication method of the present invention.

Fig. 20 is a subthreshold swing comparison of the inventive structure during turn-on with a conventional MOSFET structure.

Fig. 21 is a graph showing the comparison of reverse leakage current in the voltage withstanding state of the inventive structure and the conventional MOSFET structure.

The figure indicates: 1. a first conductivity type semiconductor substrate; 2. a drift region; 3. a voltage-resistant region; 4. a heterogeneous material region; 5. a source electrode; 6. a fourth dielectric region; 7. a gate; 8. a groove; 9. buried layer electrodes; 10. a drain electrode; 11. a gate dielectric region; 12. a second dielectric region; 13. a third dielectric region; 14. a first dielectric region.

Detailed Description

The technical scheme of the invention is further described below with reference to the accompanying drawings.

Example 1

A low tunneling leakage current power device, comprising: a first conductivity type semiconductor substrate provided with a drain electrode 10 on one surface of the substrate 1 and a drift region 2 on the other surface of the first conductivity type substrate 1; a trench 8 is provided above the drift region 2. A grid electrode 7 and two other buried layer electrodes 9 are arranged in the groove 8, the two buried layer electrodes 9 are separated by a first dielectric region 14, and a second dielectric region 12 is arranged between the electrode 9 and the groove 8; the gate 7 is located above the electrode 9 and is separated by a third dielectric region 13; a gate dielectric region 11 is arranged between the gate 7 and the trench 8; the gate electrode 7 is separated from the source electrode 5 by a fourth dielectric region 6. And a heterogeneous material region 4 is arranged above the drift regions 2 at two sides of the groove 8, and the heterogeneous material region 4 is connected with a source electrode 5. A second conductivity type withstand voltage region 3 is provided below the hetero material region 4, the withstand voltage region 3 being separated from the trench 8 by a first conductivity type drift region 2.

Example 2

In another power device with low tunneling leakage current, as shown in fig. 3, the shape of the buried layer electrode 9 below the gate electrode 7 in the trench 8 may be selected to be square or circular, unlike embodiment 1, the buried layer electrode may be prepared by a simpler process, and the device performance uniformity is good and the process requirements are simpler.

Example 3

In another power device with low tunneling leakage current, as shown in fig. 4, the top trench 8 of the drift region 2 is in a circular arc shape, and correspondingly, the bottom buried electrode 9 of the trench is also in a semicircular arc shape. Further alternatively, the buried trench electrode may be a single structure filling the bottom of the trench or a split structure as in embodiment 1. According to the embodiment, the introduction of the bottom angle of the groove is avoided in the groove manufacturing process, so that the peak electric field intensity at the second dielectric layer nearby when the electric field is concentrated near the buried layer electrode at the bottom of the groove is further reduced, and the risk of breakdown of the bottom angle of the groove is further reduced.

Manufacturing method of low-tunneling leakage current power device

Step 1, as shown in fig. 7, taking a first conductive type substrate, forming an epitaxial drift layer with the same conductive type on one surface of the substrate, and implanting a second conductive type region in the N-type epitaxial layer by using an ion implantation process;

step 2, as shown in fig. 8, a layer of heterogeneous material source region is deposited on the surface of the epitaxial layer by using a CVD process, and optionally, the heterogeneous material is polysilicon, metal, graphene, molybdenum disulfide, silicon carbide, and other materials capable of forming an energy band barrier with the drift region.

Step 3, as shown in fig. 9, an ion etching process is used to etch and form a trench above the source region and the drift region, and optionally, the bottom of the trench is square, arc-shaped or other smooth shape.

Step 4, as shown in fig. 10, a second dielectric layer is deposited in the trench by using a thermal growth or deposition process.

And 5, as shown in fig. 11, depositing a buried layer electrode in the trench by using deposition, sputtering and other processes, and controlling the upper surface position of the electrode by one-time etching.

And 6, as shown in fig. 12, thinning the thickness of the middle part of the buried layer electrode through secondary etching.

And 7, forming two separated buried layer electrodes through three times of etching as shown in fig. 13.

And 8, as shown in fig. 14, filling a dielectric layer in the trench again by using a deposition or growth mode to form a first dielectric region isolated between the two buried layers.

And 9, as shown in fig. 15, removing the heterogeneous material surface and the upper part of the dielectric layer in the groove by etching the dielectric layer to form a third dielectric layer for isolating the buried electrode from the grid electrode.

Step 10, as shown in fig. 16, dielectric material is deposited again on the inner wall of the trench and the surface of the heterogeneous material to form a gate dielectric region.

Step 11, as shown in fig. 17, a conductive material such as metal or polysilicon is filled in the trench by deposition, sputtering, or the like, and a gate electrode is formed.

Step 12, as shown in fig. 18, a dielectric layer is deposited on the surface, and a fourth dielectric region and a contact hole exposing the heterogeneous material region are formed by etching the dielectric layer over the heterogeneous material region.

Step 13, as shown in fig. 19, forming a metal region on the surface plane by deposition, sputtering, evaporation and other methods, and forming a second electrode region by filling the opening part of the fourth dielectric region of the surface, contacting with the lower heterogeneous material region; a metal region is also formed on the back substrate and serves as a first electrode region.

It will be understood that the invention has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. The power device with low tunneling leakage current is characterized by comprising a first conductive type semiconductor substrate (1), wherein a drain electrode (10) is arranged on the lower surface of the first conductive type semiconductor substrate (1), and a drift region (2) is arranged on the upper surface of the first conductive type semiconductor substrate (1); a groove (8) is formed above the drift region (2), a grid electrode (7) and a buried layer electrode (9) are arranged in the groove (8), and the grid electrode (7) is positioned above the buried layer electrode (9) and is separated by a third dielectric region (13); a second dielectric region (12) is filled between the buried layer electrode (9) and the side wall of the groove (8); the gate dielectric regions (11) are filled at the outward extending parts of the side walls of the gate electrode (7) and the groove (8) and the two sides above the gate electrode; heterogeneous material areas (4) are respectively arranged above the drift areas (2) on the two sides of the groove (8); the upper part of the heterogeneous material region (4) is respectively in contact connection with a source electrode (5) and a gate dielectric region (11), and the source electrode (5) is positioned at the top of the whole power device; a fourth medium region (6) is filled between the grid electrode (7) and the source electrode (5); the lower part of the heterogeneous material region (4) is in contact connection with the pressure-resistant region (3), and the pressure-resistant region (3) is separated from the groove (8) by the drift region (2).

2. A low tunneling leakage current power device according to claim 1, characterized in that the number of buried electrodes (9) is two, the two buried electrodes (9) are symmetrically distributed on both sides of the bottom of the trench (8) with the centerline of the trench (8), and the two buried electrodes (9) are separated by the first dielectric region (14).

3. A low tunneling leakage current power device according to claim 1 or 2, characterized in that the shape of the buried electrode (9) comprises L-shape, square shape, rectangular shape, circular arc shape and fan shape.

4. A low tunneling leakage current power device according to claim 1 or 2, characterized in that the potential setting means of the buried electrode (9) comprises floating, sharing potential with the source electrode (5) through a layout design or an external circuit, or separately providing potential through electrode extraction.

5. A low tunneling leakage current power device according to claim 1, characterized in that said withstand voltage region (3) is withstand voltage in a device blocking state, with a doping concentration typically of 1 x 10 ¹⁴ -1×10 ²⁰ cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The depth occupied by the pressure-resistant region (3) in the drift region (2) is not less than the depth occupied by the groove (8); the pressure-resistant region (3) is made of a material of a second conductivity type which is the same as that of the drift region (2) or is different from the drift region (2) but can form a space charge region near a metallurgical junction contacted with the drift region (2), when a certain potential difference exists between the source electrode (5) and the drain electrode (10), the width of the space charge region changes, the current path is limited, and the electric field intensity at the bottom of the groove (8) is reduced;

the pressure-resistant area (3) is made of materials specifically including: polycrystalline silicon, single crystal silicon, nickel, titanium, aluminum, copper, silver, gold, molybdenum, silicon oxide, silicon nitride, aluminum oxide, graphene, molybdenum disulfide, silicon carbide, diamond, gallium oxide, and gallium nitride.

6. A low tunneling leakage current power device according to claim 1, characterized in that the bottom surface of the trench (8) is lower than the contact surface of the hetero material region (4) with the drift region (2), and the bottom surface of the gate (7) in the trench (8) is also lower than the contact surface of the hetero material region (4) with the drift region (2).

7. The low tunneling leakage current power device of claim 1, wherein said hetero-material region (4) is selected from the group consisting of polysilicon, single crystal silicon, graphene, molybdenum disulfide, silicon carbide, diamond, gallium oxide, and gallium nitride; which is capable of band bending after contact with the drift region (2) and creates a potential barrier, the barrier height being capable of being varied by varying the voltage applied by the control gate (7) and thereby adjusting the magnitude of the current flowing through the source (5) and drain (10) electrodes.

8. The low tunneling leakage current power device of claim 1, wherein said first conductivity type drift region (2) material is selected from silicon carbide, gallium oxide, gallium nitride, silicon or diamond; by a process of forming doping by growth, thermal diffusion, ion implantation, wherein the impurity concentration is typically 1X 10 ¹³ ～1×10 ¹⁹ cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The substrate (1) is made of silicon carbide, gallium nitride, gallium oxide, silicon or diamond, the substrate (1) can be of a first to point type or a second conductivity type, i.e. the substrate (1) can be doped with N type or P type and has a doping concentration range of 1×10 ¹⁸ ～1×10 ²² cm ^-3 。

9. The low tunneling leakage current power device according to claim 1, wherein said source electrode (5), gate electrode (7), buried layer electrode (9), drain electrode (10) are selected from conductive materials including polysilicon, nickel, titanium, aluminum, copper, silver and gold; the fourth dielectric region (6), the gate dielectric region (11), the second dielectric region (12), the third dielectric region (13) and the first dielectric region (14) are made of various nitrogen-containing and oxygen-containing compounds of silicon, aluminum oxide, molybdenum dioxide, zirconium oxide and nickel oxide, the first conductive type semiconductor substrate (1) is N-type doped, and the pressure-resistant region (3) is P-type doped; or the first conductive type semiconductor substrate (1) is doped with P type, and the voltage-resistant region (3) is doped with N type.

10. A method of manufacturing a low tunneling leakage current power device according to claim 1, comprising the steps of: