WO2023193339A1

WO2023193339A1 - Method for manufacturing igbt device

Info

Publication number: WO2023193339A1
Application number: PCT/CN2022/098586
Authority: WO
Inventors: 刘伟; 王鹏飞; 刘磊; 龚轶
Original assignee: 苏州东微半导体股份有限公司
Priority date: 2022-04-08
Filing date: 2022-06-14
Publication date: 2023-10-12
Also published as: CN116936357A

Abstract

A method for manufacturing an IGBT device. An n-type charge storage region (22) is formed after a first trench (31) is formed, and the depth of the n-type charge storage region (22) is controlled by controlling the depth of the first trench (31); a floating p-type column (23) is first formed, and then a gate (25) is formed; and the n-type charge storage region (22), the p-type column (23), and the gate (25) are formed by means of a self-alignment process.

Description

Manufacturing method of IGBT device

This application claims priority to the Chinese patent application with application number 202210367143.0, which was submitted to the China Patent Office on April 8, 2022. The entire content of this application is incorporated into this application by reference.

Technical field

The present application belongs to the technical field of IGBT devices, and for example, relates to a manufacturing method of IGBT devices.

Background technique

The Insulated Gate Bipolar Transistor (IGBT) power device is a device composed of a Metal-Oxide-Semiconductor (MOS) structure transistor and a bipolar transistor. Its input is extremely MOS transistor, the output is extremely PNP transistor. It combines the advantages of these two devices. It not only has the advantages of small driving power and fast switching speed of MOS transistor, but also has the advantages of low saturation voltage and large capacity of bipolar transistor. In modern times, It has been increasingly widely used in power electronics technology, especially occupying a dominant position in the application of large and medium power tubes with higher frequencies. In the manufacturing method of IGBT in the related art, the n-type charge storage region is formed through a high-temperature annealing process after phosphorus implantation, and then the p-type body region is formed. The n-type charge storage region will extend to the range of the p-type body region, thus affecting the In order to maintain the doping of the p-type body region unaffected, the doping concentration of the n-type charge storage region is much lower than that of the p-type body region, which limits n-type charge storage. The optimization of parameters such as saturation voltage drop, turn-off loss and current density prevents the performance of IGBT devices from being further improved.

Contents of the invention

In view of this, this application provides a manufacturing method of an IGBT device to further improve the performance of the IGBT device.

An embodiment of the present application provides a method for manufacturing an IGBT device, including:

Form a hard mask layer on the provided n-type semiconductor layer, define the position of the first trench through a photolithography process, and etch the hard mask layer to expose the n-type semiconductor layer;

Using the hard mask layer as a mask, perform anisotropic etching on the n-type semiconductor layer to form a first trench in the n-type semiconductor layer;

Using the hard mask layer as a mask, perform n-type ion implantation and annealing on the n-type semiconductor layer through the first trench, and form a layer located at the bottom of the first trench in the n-type semiconductor layer. n-type charge storage area;

Using the hard mask layer as a mask, perform anisotropic etching on the n-type semiconductor layer to form a second trench below the first trench, and the second trench penetrates the n-type semiconductor layer. charge storage area;

A p-type polysilicon layer is formed, the p-type polysilicon layer is etched back using the hard mask layer as a mask, and a p-type pillar is formed in the second trench, and the p-type pillar extends upward to the The remaining space within the first trench and the first trench forms a third trench;

Using the hard mask layer as a mask, perform isotropic etching on the n-type semiconductor layer to increase the width and depth of the third trench. The depth of the third trench is smaller than the first trench. depth of trench;

Form a gate oxide layer on the surface of the third trench;

Forming a gate polysilicon layer, etching back the gate polysilicon layer using the hard mask layer as a mask, and forming a gate electrode at the sidewall position of the third trench;

An insulating layer is formed, and the insulating layer is etched back to form an insulating dielectric layer located above the p-type pillar in the third trench.

Description of the drawings

The following is a brief introduction to the drawings needed to describe the embodiments.

FIG. 1 is a schematic cross-sectional structural diagram after forming a hard mask layer according to the manufacturing method of an IGBT device provided by an embodiment of the present application.

FIG. 2 is a schematic cross-sectional structural diagram after the first trench is formed according to the manufacturing method of the IGBT device provided by the embodiment of the present application.

FIG. 3 is a schematic cross-sectional structural diagram after forming an n-type charge storage region according to the manufacturing method of an IGBT device provided by an embodiment of the present application.

FIG. 4 is a schematic cross-sectional structural diagram after the second trench is formed according to the manufacturing method of the IGBT device provided by the embodiment of the present application.

FIG. 5 is a schematic cross-sectional structural diagram after forming the third trench and the p-type pillar according to the manufacturing method of the IGBT device provided by the embodiment of the present application.

FIG. 6 is a schematic cross-sectional structural diagram after increasing the width and depth of the third trench according to the manufacturing method of the IGBT device provided by the embodiment of the present application.

FIG. 7 is a schematic cross-sectional structural diagram after the gate oxide layer and gate electrode are formed according to the manufacturing method of the IGBT device provided by the embodiment of the present application.

FIG. 8 is a schematic cross-sectional structural diagram after forming an insulating dielectric layer according to the manufacturing method of an IGBT device provided by an embodiment of the present application.

FIG. 9 is a schematic cross-sectional structural diagram after forming a p-type body region according to the manufacturing method of an IGBT device provided by an embodiment of the present application.

Detailed ways

The technical solution of the present application will be completely described in a specific manner in conjunction with the accompanying drawings in the embodiments of the present application.

1 to 9 are schematic cross-sectional structural diagrams of main process nodes of an embodiment of the manufacturing method of an IGBT device of the present application. As shown in Figures 1 to 9, a manufacturing method of an IGBT device in this application includes:

As shown in FIG. 1 , a hard mask layer 21 is formed on the provided n-type semiconductor layer 20 , and then the position of the first trench is defined through a photolithography process. The photolithography process includes: forming a hard mask layer 21 on the hard mask layer 21 . A layer of photoresist 30 is then exposed and developed to form a pattern; and then the hard mask layer 21 is etched to expose the n-type semiconductor layer 20 . The material of the n-type semiconductor layer 20 is preferably silicon.

As shown in FIG. 2 , the photoresist is removed, and the n-type semiconductor layer 20 is anisotropically etched using the hard mask layer 21 as a mask to form a first trench 31 in the n-type semiconductor layer 20 . The number of a trench 31 is determined according to the specific specifications of the IGBT device. In the embodiment of the present application, only two first trench 31 structures are shown as an example.

As shown in FIG. 3 , using the hard mask layer 21 as a mask, vertical n-type ions are implanted into the n-type semiconductor layer 20 through the first trench 31 and annealed to form a layer located in the first trench in the n-type semiconductor layer 20 . The width of the n-type charge storage area 22 at the bottom of the trench 31 should be greater than the width of the first trench 31. The steps for forming the n-type charge storage area 22 include: performing vertical n-type ion implantation in the n-type semiconductor. An n-type charge storage region 22 is formed in the layer 20, and then the n-type ions in the n-type charge storage region 22 are diffused to a predetermined range through an annealing process. This application can control the depth of the n-type charge storage region 22 formed through the depth of the first trench 31, and adjust the diffusion range of the n-type charge storage region 22 through the annealing temperature and time.

As shown in FIG. 4 , using the hard mask layer 21 as a mask, the n-type semiconductor layer 20 is continuously etched anisotropically to form a second trench 32 below the first trench. At this time, the second trench 32 through n-type charge storage region 22. Forming the second trench 32 below the first trench is equivalent to increasing the depth of the first trench.

As shown in FIG. 5 , a p-type polysilicon layer is formed, and then the hard mask layer 21 is used as a mask to etch back the formed p-type polysilicon layer to form p-type pillars 23 in the second trench. should extend upward into the first trench, that is, the upper surface of the p-type pillar 23 is located above the upper surface of the n-type charge storage region 22, and at the same time, the remaining space of the first trench forms the third trench 33. The depth of groove 33 is smaller than the depth of the first groove. A superjunction structure is formed between the p-type pillar 23 and the adjacent n-type semiconductor layer 20, which can improve the withstand voltage of the IGBT device.

As shown in FIG. 6 , using the hard mask layer 21 as a mask, the n-type semiconductor layer 20 is isotropically etched to increase the width and depth of the third trench 33 . In this step of etching process, the p-type pillar 23 will also be partially etched away, so the depth of the third trench 33 will also increase. After this step of etching, preferably, the depth of the third trench 33 can be increased. is still less than the depth of the first trench, that is, the bottom surface of the third trench 33 is located above the n-type charge storage area 22 or the bottom surface of the third trench 33 is flush with the upper surface of the n-type charge storage area 22, that is to say The bottom surface of the third trench 33 is not embedded in the n-type charge storage region 22, so that the n-type charge storage region 22 is located far away from the subsequently formed p-type body region and does not affect the doping of the p-type body region. In other words, in order to maintain the doping of the p-type body region unaffected, the doping concentration of the n-type charge storage region 22 is not set to be much lower than the doping concentration of the p-type body region, thereby increasing the doping concentration of the n-type charge storage region 22 . The doping concentration reduces the saturation voltage drop and turn-off loss of the IGBT device without affecting the p-type body region.

As shown in FIG. 7 , thermal oxidation is performed to form a gate oxide layer 24 on the surface of the third trench; then a gate polysilicon layer is deposited and the formed gate polysilicon layer is processed using the hard mask layer 21 as a mask. Engraving back, the gate 25 is formed at the sidewall position of the third trench 33 . Forming the gate electrode 25 after forming the p-type pillar 23 can avoid damage to the gate electrode when forming the gate electrode first and then forming the p-type pillar; at the same time, the gate electrode 25 is only located at the side wall of the third trench 33 , the area of the gate 25 can be reduced, the gate charge can be reduced, and the switching speed of the IGBT device can be increased.

As shown in FIG. 8 , an insulating layer is formed and the formed insulating layer is etched back to form an insulating dielectric layer 26 above the p-type pillar 23 in the third trench, and then the hard mask layer is removed.

As shown in FIG. 9 , a p-type body region 27 is formed in the n-type semiconductor layer 20 , an n-type emitter region 28 is formed in the p-type body region 27 , and the p-type body region 27 is located between adjacent third trenches. . It should be noted that an annealing process is required when forming the p-type body region 27 and the n-type emitter region 28. At this time, the n-type charge storage region 22 will further diffuse and be located between two adjacent p-type pillars 23. The n-type charge storage regions 22 between them may be connected to form a whole after diffusion (as shown in FIG. 9), or may not be connected after diffusion (this structure is not shown in the embodiments of this application).

The manufacturing method of the IGBT device according to the embodiment of the present application also includes: forming an interlayer insulating layer on the surface of the n-type semiconductor layer, and forming source metal and gate metal; forming an n-type field stop region at the bottom of the n-type semiconductor layer and a p-type collector region; a collector metal is formed on the bottom surface of the n-type semiconductor layer. The above processes are all common processes in the industry, and will not be shown or described in detail in the embodiments of this application.

In the manufacturing method of the IGBT device of the present application, the n-type charge storage area, the p-type pillar and the gate are all formed through a self-alignment process, which greatly simplifies the manufacturing process of the IGBT device.

In the manufacturing method of the IGBT device according to the embodiment of the present application, an n-type charge storage area is formed after forming the first trench, and the depth of the n-type charge storage area is controlled by controlling the depth of the first trench to avoid the n-type charge storage area's negative impact on subsequent operations. The formed p-type body region has an impact; the floating p-type pillar is formed first, and then the gate is formed to avoid damage to the gate when forming the p-type pillar; the n-type charge storage area, p-type pillar and gate are all Formed through a self-alignment process, the manufacturing process of IGBT devices is simplified.

Claims

A method for manufacturing an IGBT device, including:

Form a hard mask layer on the provided n-type semiconductor layer, define the position of the first trench through a photolithography process, and etch the hard mask layer to expose the n-type semiconductor layer;

Using the hard mask layer as a mask, perform anisotropic etching on the n-type semiconductor layer to form the first trench in the n-type semiconductor layer;

Using the hard mask layer as a mask, perform n-type ion implantation and annealing on the n-type semiconductor layer through the first trench, and form a layer located at the bottom of the first trench in the n-type semiconductor layer. n-type charge storage area;

Using the hard mask layer as a mask, perform anisotropic etching on the n-type semiconductor layer to form a second trench below the first trench, and the second trench penetrates the n-type semiconductor layer. charge storage area;

A p-type polysilicon layer is formed, the p-type polysilicon layer is etched back using the hard mask layer as a mask, and a p-type pillar is formed in the second trench, and the p-type pillar extends upward to the A third trench is formed in the first trench and the remaining space of the first trench, and the depth of the third trench is smaller than the depth of the first trench;

Using the hard mask layer as a mask, perform isotropic etching on the n-type semiconductor layer to increase the width and depth of the third trench;

Form a gate oxide layer on the surface of the third trench;

Forming a gate polysilicon layer, etching back the gate polysilicon layer using the hard mask layer as a mask, and forming a gate electrode at the sidewall position of the third trench;

An insulating layer is formed, and the insulating layer is etched back to form an insulating dielectric layer located above the p-type pillar in the third trench.
The manufacturing method of an IGBT device according to claim 1, further comprising: etching away the hard mask layer, forming a p-type body region in the n-type semiconductor layer, and forming an n-type body region in the p-type body region. type emitter region, wherein the p-type body region is located between the adjacent third trenches.
The method of manufacturing an IGBT device according to claim 2, further comprising: forming an interlayer insulating layer on the surface of the n-type semiconductor layer, and forming a source metal and a gate metal.
The method of manufacturing an IGBT device according to claim 3, further comprising: forming an n-type field stop region and a p-type collector region at the bottom of the n-type semiconductor layer.
The method of manufacturing an IGBT device according to claim 4, further comprising: forming a collector metal on a bottom surface of the n-type semiconductor layer.
The method of manufacturing an IGBT device according to claim 1, wherein the n-type semiconductor layer is made of silicon.