CN116936357A - IGBT device manufacturing method - Google Patents
IGBT device manufacturing method Download PDFInfo
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- CN116936357A CN116936357A CN202210367143.0A CN202210367143A CN116936357A CN 116936357 A CN116936357 A CN 116936357A CN 202210367143 A CN202210367143 A CN 202210367143A CN 116936357 A CN116936357 A CN 116936357A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000003860 storage Methods 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 94
- 239000004065 semiconductor Substances 0.000 claims description 41
- 210000000746 body region Anatomy 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Abstract
According to the manufacturing method of the IGBT device, firstly, after the first groove is formed, an n-type charge storage area is formed, the depth of the n-type charge storage area is controlled by controlling the depth of the first groove, and the influence of the n-type charge storage area on a p-type body area formed subsequently is avoided; secondly, firstly forming a floating p-type column and then forming a grid electrode, so that the damage to the grid electrode when the p-type column is formed is avoided; again, the n-type charge storage region, the p-type pillar and the gate are all formed by a self-aligned process, simplifying the fabrication process of the IGBT device.
Description
Technical Field
The invention belongs to the technical field of IGBT devices, and particularly relates to a manufacturing method of an IGBT device.
Background
The insulated gate field effect transistor (Insulated Gate Bipolar Transistor, IGBT) power device is a device formed by compounding a MOS transistor and a bipolar transistor, the input of the device is a MOS transistor, the output of the device is a PNP transistor, the device combines the advantages of the two devices, has the advantages of small driving power and high switching speed of the MOS transistor, has the advantages of reduced saturation voltage and large capacity of the bipolar transistor, and is widely applied in the modern power electronic technology, and particularly occupies the dominant position of the application of high-frequency large and medium-power transistors. In the manufacturing method of the IGBT in the prior art, the n-type charge storage region is formed through a high-temperature annealing process after phosphorus injection, and then the p-type body region is formed, so that the n-type charge storage region can extend to the range of the p-type body region, the doping of the p-type body region is influenced, the doping concentration of the n-type charge storage region is far lower than that of the p-type body region in order to keep the doping of the p-type body region unaffected, and the optimization of parameters such as saturation voltage drop, turn-off loss and current density of the n-type charge storage region is limited, so that the performance of the IGBT device cannot be further improved.
Disclosure of Invention
In view of the above, the present invention is to provide a method for manufacturing an IGBT device to further improve the performance of the IGBT device.
The manufacturing method of the IGBT device provided by the embodiment of the invention comprises the following steps:
forming a hard mask layer on the provided n-type semiconductor layer, defining the position of a first groove through a photoetching process, and etching the hard mask layer to expose the n-type semiconductor layer;
using the hard mask layer as a mask, carrying out anisotropic etching on the n-type semiconductor layer, and forming a first groove in the n-type semiconductor layer;
using the hard mask layer as a mask, performing n-type ion implantation and annealing on the n-type semiconductor layer through the first groove, and forming an n-type charge storage region at the bottom of the first groove in the n-type semiconductor layer;
continuing to anisotropically etch the n-type semiconductor layer by taking the hard mask layer as a mask, and forming a second trench below the first trench, wherein the second trench penetrates through the n-type charge storage region;
forming a p-type polycrystalline silicon layer, carrying out back etching on the p-type polycrystalline silicon layer by taking the hard mask layer as a mask, forming a p-type column in the second groove, wherein the p-type column extends upwards into the first groove, and the residual space of the first groove forms a third groove;
isotropically etching the n-type semiconductor layer by taking the hard mask layer as a mask, and increasing the width and depth of the third groove, wherein the depth of the third groove is smaller than that of the first groove;
forming a gate oxide layer on the surface of the third groove;
forming a gate polysilicon layer, carrying out back etching on the gate polysilicon layer by taking the hard mask layer as a mask, and forming a gate at the side wall position of the third groove;
and forming an insulating layer, and carrying out back etching on the insulating layer to form an insulating medium layer positioned above the p-type column in the third groove.
Optionally, the method further comprises: and etching the hard mask layer, forming a p-type body region in the n-type semiconductor layer, and forming an n-type emitter region in the p-type body region, wherein the p-type body region is positioned between the adjacent third grooves.
Optionally, the method further comprises: an interlayer insulating layer is formed on the surface of the n-type semiconductor layer, and a source metal and a gate metal are formed.
Optionally, the method further comprises: an n-type field stop region and a p-type collector region are formed at the bottom of the n-type semiconductor layer.
Optionally, the method further comprises: and forming a collector metal on the bottom surface of the n-type semiconductor layer.
Optionally, the material of the n-type semiconductor layer is silicon.
According to the manufacturing method of the IGBT device, firstly, after the first groove is formed, an n-type charge storage area is formed, the depth of the n-type charge storage area is controlled by controlling the depth of the first groove, and the influence of the n-type charge storage area on a p-type body area formed subsequently is avoided; secondly, firstly forming a floating p-type column and then forming a grid electrode, so that the damage to the grid electrode when the p-type column is formed is avoided; again, the n-type charge storage region, the p-type pillar and the gate are all formed by a self-aligned process, simplifying the fabrication process of the IGBT device.
Drawings
In order to more clearly illustrate the technical solution of the exemplary embodiments of the present invention, a brief description is given below of the drawings required for describing the embodiments.
Fig. 1 to 9 are schematic cross-sectional structures of main process nodes of an embodiment of a method of manufacturing an IGBT device of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be fully described below by way of specific modes with reference to the accompanying drawings in the embodiments of the present invention.
Fig. 1 to 9 are schematic cross-sectional structures of main process nodes of an embodiment of a method of manufacturing an IGBT device of the invention. As shown in fig. 1 to 9, a method of manufacturing an IGBT device of the invention includes:
first, as shown in fig. 1, a hard mask layer 21 is formed on a provided n-type semiconductor layer 20, and then the position of a first trench is defined by a photolithography process including: forming a photoresist 30 on the hard mask layer 21, and then exposing and developing to form a pattern; the hard mask layer 21 is then etched to expose the n-type semiconductor layer 20. The material of the n-type semiconductor layer 20 is preferably silicon.
Next, as shown in fig. 2, the photoresist is removed, the hard mask layer 21 is used as a mask, the n-type semiconductor layer 20 is anisotropically etched, and the first trenches 31 are formed in the n-type semiconductor layer 20, the number of the first trenches 31 is determined according to the specific specifications of the set IGBT device, and only two first trench 31 structures are exemplarily shown in the embodiment of the present invention.
Next, as shown in fig. 3, with the hard mask layer 21 as a mask, the n-type semiconductor layer 20 is subjected to vertical n-type ion implantation and annealing through the first trench 31, and an n-type charge storage region 22 is formed in the n-type semiconductor layer 20 at the bottom of the first trench 31, wherein the width of the n-type charge storage region 22 is larger than that of the first trench 31, and the specific steps of forming the n-type charge storage region 22 include: a vertical n-type ion implantation is performed to form an n-type charge storage region 22 in the n-type semiconductor layer 20, and then n-type ions of the n-type charge storage region 22 are diffused to a predetermined range by an annealing process. The present invention can control the depth of the formed n-type charge storage region 22 by the depth of the first trench 31 and adjust the diffusion range of the n-type charge storage region 22 by the annealing temperature and time.
Next, as shown in fig. 4, the n-type semiconductor layer 20 is anisotropically etched using the hard mask layer 21 as a mask, and a second trench 32 is formed under the first trench, and the second trench 32 penetrates the n-type charge storage region 22. Forming the second trench 32 below the first trench corresponds to increasing the depth of the first trench.
Next, as shown in fig. 5, a p-type polysilicon layer is formed, and then the formed p-type polysilicon layer is etched back using the hard mask layer 21 as a mask, and a p-type pillar 23 is formed in the second trench, wherein the p-type pillar 23 should extend upward into the first trench, i.e., the upper surface of the p-type pillar 23 is located above the upper surface of the n-type charge storage region 22, while the remaining space of the first trench forms a third trench 33, and the depth of the third trench 33 is smaller than the depth of the first trench. The super junction structure is formed between the p-type pillar 23 and the adjacent n-type semiconductor layer 20, so that the withstand voltage of the IGBT device can be improved.
Next, as shown in fig. 6, the n-type semiconductor layer 20 is isotropically etched with the hard mask layer 21 as a mask, increasing the width and depth of the third trench 33. In this etching process, the p-type pillar 23 is also partially etched away, so that the depth of the third trench 33 is increased, and after the etching process, preferably, the depth of the third trench 33 is still smaller than the depth of the first trench, that is, the bottom surface of the third trench 33 is located above the n-type charge storage region 22 or the bottom surface of the third trench 33 is flush with the upper surface of the n-type charge storage region 22, that is, the bottom surface of the third trench 33 is not embedded into the n-type charge storage region 22, so that the n-type charge storage region 22 is far away from the position of the subsequently formed p-type body region, the doping of the p-type body region is not affected, or in order to maintain the doping of the p-type body region unaffected, the doping concentration of the n-type charge storage region 22 is not set to be far lower than that of the p-type body region, so that the doping concentration of the n-type charge storage region 22 can be increased, the saturation voltage drop and the turn-off loss of the IGBT device are reduced, and the p-type body region is not affected.
Next, as shown in fig. 7, thermal oxidation is performed to form a gate oxide layer 24 on the surface of the third trench; thereafter, a gate polysilicon layer is deposited and etched back using the hard mask layer 21 as a mask, and a gate electrode 25 is formed at a sidewall position of the third trench 33. After the p-type column 23 is formed, the grid electrode 25 is formed, so that the damage to the grid electrode when the grid electrode is formed firstly and then the p-type column is formed can be avoided; meanwhile, the gate electrode 25 is only located at the side wall position of the third trench 33, so that the area of the gate electrode 25 can be reduced, gate charge can be reduced, and the switching speed of the IGBT device can be improved.
Next, as shown in fig. 8, an insulating layer is formed and etched back, an insulating dielectric layer 26 is formed in the third trench over the p-type pillars 23, and then the hard mask layer is removed.
Next, as shown in fig. 9, a p-type body region 27 is formed in the n-type semiconductor layer 20, an n-type emitter region 28 is formed in the p-type body region 27, and the p-type body region 27 is located between adjacent third trenches. It should be noted that an annealing process is required to form the p-type body region 27 and the n-type emitter region 28, and the n-type charge storage region 22 is further diffused, so that the n-type charge storage regions 22 located between two adjacent p-type pillars 23 may be connected as a whole after diffusion (as shown in fig. 9), or may not be connected after diffusion (this structure is not shown in the embodiment of the present invention).
Finally, the method for manufacturing the IGBT device according to the embodiment of the invention further comprises the following steps: forming an interlayer insulating layer on the surface of the n-type semiconductor layer, and forming a source metal and a gate metal; forming an n-type field stop region and a p-type collector region at the bottom of the n-type semiconductor layer; the collector metal is formed on the bottom surface of the n-type semiconductor layer, which is a conventional process in the industry, and is not specifically shown or described in the embodiments of the present invention.
In the manufacturing method of the IGBT device, the n-type charge storage region, the p-type column and the grid electrode are all formed through the self-alignment process, so that the manufacturing process of the IGBT device is greatly simplified.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (6)
1. A method of manufacturing an IGBT device, comprising:
forming a hard mask layer on the provided n-type semiconductor layer, defining the position of a first groove through a photoetching process, and etching the hard mask layer to expose the n-type semiconductor layer;
using the hard mask layer as a mask, carrying out anisotropic etching on the n-type semiconductor layer, and forming a first groove in the n-type semiconductor layer;
using the hard mask layer as a mask, performing n-type ion implantation and annealing on the n-type semiconductor layer through the first groove, and forming an n-type charge storage region at the bottom of the first groove in the n-type semiconductor layer;
continuing to anisotropically etch the n-type semiconductor layer by taking the hard mask layer as a mask, and forming a second trench below the first trench, wherein the second trench penetrates through the n-type charge storage region;
forming a p-type polycrystalline silicon layer, carrying out back etching on the p-type polycrystalline silicon layer by taking the hard mask layer as a mask, forming a p-type column in the second groove, wherein the p-type column extends upwards into the first groove, a third groove is formed in the residual space of the first groove, and the depth of the third groove is smaller than that of the first groove;
isotropically etching the n-type semiconductor layer by taking the hard mask layer as a mask, and increasing the width and depth of the third groove;
forming a gate oxide layer on the surface of the third groove;
forming a gate polysilicon layer, carrying out back etching on the gate polysilicon layer by taking the hard mask layer as a mask, and forming a gate at the side wall position of the third groove;
and forming an insulating layer, and carrying out back etching on the insulating layer to form an insulating medium layer positioned above the p-type column in the third groove.
2. The method of manufacturing an IGBT device of claim 1, further comprising: and etching the hard mask layer, forming a p-type body region in the n-type semiconductor layer, and forming an n-type emitter region in the p-type body region, wherein the p-type body region is positioned between the adjacent third grooves.
3. The method of manufacturing an IGBT device of claim 2, further comprising: an interlayer insulating layer is formed on the surface of the n-type semiconductor layer, and a source metal and a gate metal are formed.
4. The method of manufacturing an IGBT device of claim 3, further comprising: an n-type field stop region and a p-type collector region are formed at the bottom of the n-type semiconductor layer.
5. The method of manufacturing an IGBT device of claim 4, further comprising: and forming a collector metal on the bottom surface of the n-type semiconductor layer.
6. The method of manufacturing an IGBT device of claim 1 wherein the material of the n type semiconductor layer is silicon.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210367143.0A CN116936357A (en) | 2022-04-08 | 2022-04-08 | IGBT device manufacturing method |
| PCT/CN2022/098586 WO2023193339A1 (en) | 2022-04-08 | 2022-06-14 | Method for manufacturing igbt device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210367143.0A CN116936357A (en) | 2022-04-08 | 2022-04-08 | IGBT device manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116936357A true CN116936357A (en) | 2023-10-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210367143.0A Pending CN116936357A (en) | 2022-04-08 | 2022-04-08 | IGBT device manufacturing method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN116936357A (en) |
| WO (1) | WO2023193339A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6056623B2 (en) * | 2013-04-12 | 2017-01-11 | 三菱電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN105551964B (en) * | 2015-12-25 | 2018-10-26 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of groove separation side gate MOSFET with shield grid |
| CN110137249A (en) * | 2018-02-09 | 2019-08-16 | 苏州东微半导体有限公司 | IGBT power device and its manufacturing method |
| CN113643968A (en) * | 2020-04-27 | 2021-11-12 | 上海贝岭股份有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN113838920B (en) * | 2021-09-23 | 2023-04-28 | 电子科技大学 | Separation gate CSTBT with self-bias PMOS and manufacturing method thereof |
-
2022
- 2022-04-08 CN CN202210367143.0A patent/CN116936357A/en active Pending
- 2022-06-14 WO PCT/CN2022/098586 patent/WO2023193339A1/en unknown
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| WO2023193339A1 (en) | 2023-10-12 |
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