JP2006080551A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device capable of simplifying a gate control circuit and having an excellent on-property and a characteristic of reducing stationary loss. <P>SOLUTION: A semiconductor device having pnpn diode is formed by sequentially laminating p<SP>+</SP>collector region 1, n-type buffer region 3, n<SP>-</SP>region 5, p-type base region 41, and n<SP>+</SP>cathode region 7. Trenches 9 penetrating the n<SP>+</SP>cathode region 7 from the surface of the n<SP>+</SP>cathode region 7 and reaching the n<SP>-</SP>region 5 are formed so as to have a part of running in parallel to each other. The n<SP>+</SP>cathode region 7 is formed on the whole surface between the parallel trenches 9. Gate electrode layers 13 are formed inside the trenches 9. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a vertical power semiconductor device having a self-extinguishing function and a method for manufacturing the same.

First, a conventional semiconductor device will be described.
FIG. 97 is a cross sectional view schematically showing a configuration of the semiconductor device in the first conventional example. Referring to FIG. 97, the first conventional example shows an example having SITh (Static Induction Thyristor). This SITh has a pin diode portion, a p-type gate region 307, a gate electrode layer 309, a cathode electrode 311 and an anode electrode 313.

The pin diode portion has a stacked structure of a p ⁺ anode region 301, an n ⁻ region 303, and a cathode region (n ⁺ emitter region) 305. The p-type gate region 307 is formed in the n ⁻ region 303. The gate electrode 309 is electrically connected to the p-type gate region 307. The cathode electrode 311 is electrically connected to the cathode region 305, and the anode electrode 313 is electrically connected to the p ⁺ anode region 301.

The above SITh can realize the main current conduction state by making the gate voltage applied to the gate electrode 309 positive. At this time, current flows from the p ⁺ anode region 301 to the cathode region 305 side through the pin diode.

FIG. 98 is a cross sectional view schematically showing a configuration of a semiconductor device in the second conventional example. Referring to FIG. 98, the second conventional example shows an example of a GTO (Gate Turn-Off) thyristor. This GTO thyristor includes a p ⁺ anode region 351, an n ⁻ region 353, a p base region 355, a cathode region 357, a gate electrode 359, a cathode electrode 361, and an anode electrode 363.

The p ⁺ anode region 351, the n ⁻ region 353, the p base region 355, and the cathode region 357 are sequentially stacked. A gate electrode 359 is electrically connected to the p-type base region 355. The cathode electrode 361 is electrically connected to the cathode region 357, and the anode electrode 363 is electrically connected to the p ⁺ anode region 351.

Even in this GTO thyristor, the main current conduction state can be realized by making the gate voltage positive. When the gate voltage is positive, current flows from the p ⁺ collector region 351 to the cathode region 357 side through the pnpn diode.

  In both the first and second conventional examples described above, the main current cutoff state can be realized by applying a negative voltage to the gate electrode. When a negative voltage is applied to the gate electrodes 309 and 359, minority carriers (holes) remaining in the element are extracted from the gate electrodes 309 and 359. As a result, the main current is cut off.

FIG. 99 is a cross sectional view schematically showing a configuration of a semiconductor device in the third conventional example. Referring to FIG. 99, the third conventional example shows an example of a trench IGBT (Insulated Gate Bipolar Transistor). The trench IGBT includes a p ⁺ collector region 101, an n ⁺ buffer region 103, an n ⁻ region 105, a p-type base region 107, an n ⁺ emitter region 109, a p ⁺ contact region 111, and a gate oxide film 115. A gate electrode layer 117, a cathode electrode (emitter) 121, and an anode electrode (collector) 123.

An n ⁻ region 105 is formed on p ⁺ collector region 101 with n ⁺ buffer region 103 interposed. On n ⁻ region 105, n ⁺ emitter region 109 and p ⁺ contact region 111 are formed adjacent to each other with p-type base region 107 interposed. A groove 413 is provided on the surface where the n ⁺ emitter region 109 is formed.

The groove 413 penetrates through the n ⁺ emitter region 109 and the p-type base region 107 and reaches the n ⁻ region 105. The depth T _P from the surface of the groove 413 is 3 to 5 μm.

A gate oxide film 115 is formed along the inner wall surface of the groove 413. A gate electrode layer 117 is formed so as to fill the groove 413 and to protrude from the inside of the groove 413. Gate electrode layer 117 is opposed to n ⁺ emitter region 109, p-type base region 107 and n ⁻ region 105 with gate oxide film 115 interposed therebetween.

An interlayer insulating layer 119 is formed so as to cover the upper end of the gate electrode layer 117. The interlayer insulating layer is provided with an opening that exposes the surfaces of the n ⁺ emitter region 109 and the p ⁺ contact region 111. A cathode electrode (emitter) 121 is formed so as to be electrically connected to n ⁺ emitter region 109 and p ⁺ contact region 111 through this opening. An anode electrode (collector) 123 is formed so as to be electrically connected to the p ⁺ collector region 101.

  Hereinafter, the surface of the semiconductor substrate on which the cathode electrode 121 is formed is referred to as a cathode surface or a first main surface, and the surface on which the anode electrode 123 is formed is referred to as an anode surface or a second main surface.

  The trench MOS gate structure in which the gate electrode layer 117 is formed in the groove 413 with the gate oxide film 115 interposed is formed by the following manufacturing method.

  First, a relatively deep groove 413 of about 3 to 5 μm is formed on a semiconductor substrate by a normal anisotropic dry etching technique. Sacrificial oxidation or a cleaning process is performed on the inner wall of the groove 413. Thereafter, a silicon thermal oxide film (hereinafter referred to as a gate oxide film) 115 is formed at a temperature of about 900 to 1000 ° C., for example, in a water vapor atmosphere. The trench 413 is filled with a polycrystalline silicon film doped with phosphorus which is an n-type impurity or a polycrystalline silicon film doped with boron which is a p-type impurity. The doped polysilicon film is patterned so as to fill in the groove 413 and to be drawn out from at least a part of the groove 413 to the surface on the cathode side. The patterned doped polysilicon film is electrically connected to a gate surface wiring formed of a metal such as aluminum that is stretched over the entire semiconductor device while being insulated from the cathode electrode 121.

  Next, a method for controlling the main current conduction state and the main current cutoff state in the third conventional example will be described.

  The main current conduction state (ON state) is a forward bias between the cathode electrode 121 and the anode electrode 123, that is, a gate with a positive (+) voltage applied to the anode electrode 123 and a negative (-) voltage applied to the cathode electrode 121. This is realized by applying a positive (+) voltage to the electrode layer 117.

  First, a turn-on process in which the element shifts from an off state to an on state will be described below.

When a positive (+) voltage is applied to the gate electrode layer 117, an n-type inverted n-channel (inverted n region) that is n-type inverted is generated in the p-type base region 107 in the vicinity of the gate oxide film 115. Electrons which are one of current carriers (hereinafter referred to as carriers) are injected into the n ⁻ region 105 from the n ⁺ emitter region 109 through the n channel and applied to the p ⁺ collector region 101 to which a positive (+) voltage is applied. It flows toward you. When these electrons reach the p ⁺ collector region 101, holes from the p ⁺ collector region 101 is another current carrier, n ^- is injected into the region 105, the negative (-) voltage is applied to n ⁺ It flows toward the emitter region 109 and reaches the point where the aforementioned n channel is in contact with the n ⁻ region 105. This process is called the accumulation (storage) process, and this time is called the storage time (t _storage ) or turn-on feed time (td ( _on )). The power loss during this storage time is small compared to the steady loss described later. Almost negligible.

Thereafter, from anode electrode 123 and cathode electrode 121. In response to potential difference applied between the electrodes, sufficient current carriers the n ^- semiconductor substrate concentrations in the area ^{105 (1 × 10 12 ~1 ×} 10 15 cm ^-3 ) 2 to 3 digits more than that. Thereby, a low resistance state called conductivity modulation appears due to the electron-hole pair, and the turn-on is completed. This process is called a rise process, and this time is called a rise time (t _rise ), and the power loss during this time is more than the same as the steady loss described later, and the total loss is divided into four.

  The steady state after completion of this turn-on is called the on-state, and the power loss represented by the product of the forward voltage drop (effectively the potential difference between the two electrodes) generated by the on-resistance in this state and the conduction current is the on-loss. Or it is called steady loss.

When a positive voltage is applied to the gate electrode layer 117, an n ⁺ accumulation region 425a having a high electron density is formed along the sidewall of the trench 113 as shown in FIG.

  The main current cutoff state (off state) is realized by applying a negative (−) voltage to the gate electrode layer 117 even when a forward bias is applied between the anode electrode 123 and the cathode electrode 121.

  Next, a turn-off process in which the element shifts from the on state to the off state will be described below.

When a negative (−) voltage is applied to the gate electrode layer 117, the n channel (inversion n region) formed on the side surface of the gate electrode layer 117 disappears, and electrons from the n ⁺ emitter region 109 to the n ⁻ region 105 disappear. Supply stops. The process so far is called an accumulation (storage) process, and the time required for this process is called an accumulation (storage) time (ts) or a turn-off delay time (td ( _off )). Also, the power loss during this time is small compared to the previous turn-on loss and steady loss, and can be almost ignored.

Further, as the electron density decreases, the electron concentration injected into the n ⁻ region 105 starts to gradually decrease from the vicinity of the n ⁺ emitter region 109. In order to maintain the charge neutral condition, the holes injected into the n ⁻ region 105 also start to decrease, and the p-type base region 107 and the n ⁻ region 105 are reverse-biased. For this reason, a depletion layer starts to spread at the interface between the p-type base region 107 and the n ⁻ region 105, and reaches a thickness corresponding to the applied voltage in the off state between both electrodes. The process so far is called the fall process, and the time required for this is called the fall time (tf). In addition, the power loss during this time is larger than the previous turn-on loss and steady loss, and the total loss is divided into four.

Further, holes in the electrically neutral region where both carriers remain outside the depletion region (from the p ⁺ collector region 101) pass through the depletion region and pass through the p ⁺ contact region 111. Passing through to the emitter electrode 121, all carriers disappear, and turn-off is completed. This process is called the tail process, this time is called the tail time (t _tail ), the power loss during this tail time is called the tail loss, and is equal to or greater than the previous turn-on loss, loss during the fall time, and steady loss. The total loss is divided into four.

The steady state after this turn-off is completed is called the off state, and the power loss caused by the product of the leakage current and the voltage between both electrodes in this state is called the off loss, but it is usually negligible compared to other power losses. .
JP-A-5-243561

  The first and second conventional examples are current control type elements that draw minority carriers from the gate electrodes 309 and 359 in order to set the main current cut-off state. For this reason, at the time of turn-off, it is necessary to draw several tens of percent of the main current from the gate electrode. When a relatively large current is drawn, the surge voltage generated by the wiring inductance or the like becomes large, and at the same time, heat generation due to the current must be considered. Therefore, it is necessary to provide a protection circuit against surge voltage and overcurrent in the circuit that controls the gate voltage. Therefore, there is a problem that the gate control circuit becomes complicated. In addition, since the control circuit may be thermally destroyed or run away due to heat generation, a cooling mechanism must be provided, resulting in a problem that the apparatus becomes large.

  A semiconductor device that solves these problems is disclosed in JP-A-5-243561. The semiconductor device disclosed in this publication will be described below as a fourth conventional example.

  FIG. 101 is a plan view schematically showing the configuration of the semiconductor device in the fourth conventional example. FIGS. 102 and 103 are respectively taken along lines P-P 'and Q-Q' in FIG. It is sectional drawing.

  101 to 103, the fourth conventional example shows an example of an electrostatic induction thyristor. A p-type emitter layer 503 is formed on one surface of the high-resistance n-type base layer 501 with an n-type buffer layer 502 interposed therebetween. A plurality of grooves 505 are formed on the other surface of the n-type base layer 501 with minute intervals. A gate electrode 507 is embedded in these trenches 505 with a gate oxide film 506 interposed therebetween. An n-type turn-off channel layer 508 is formed in every other region between the trenches 505, and a p-type drain layer 509 is formed on the surface of the turn-off channel layer 508. Further, an n-type source layer 510 is formed on the surface portion sandwiched between the p-type drain layers 509.

  A cathode electrode 511 is formed so as to be electrically connected to the p-type drain layer 509 and the n-type source layer 510. An anode electrode 512 is formed so as to be electrically connected to the p-type emitter layer 503.

  In the fourth conventional example, when a positive voltage is applied to the gate electrode 507 to increase the potential of the n-type base layer 501 sandwiched between the grooves 505, electrons are injected from the n-type source layer 510, and the element Turns on. On the other hand, when a negative voltage is applied to the gate electrode layer 507, a p-type channel is formed on the side surface of the groove of the n-type turn-off channel layer 508, and the carrier of the n-type base layer 501 passes through the p-type drain layer 509 to the cathode electrode. 511 is discharged and the device is turned off.

  In the fourth conventional example, the gate electrode 507 has an insulated gate structure. Therefore, the fourth conventional example is not a current control type in which the gate electrode 507 directly draws a current from the substrate, but a so-called voltage control type in which control is performed by a voltage (gate voltage) applied to the gate electrode.

  In the fourth conventional example, since voltage control is performed in this way, it is not necessary to draw a large current from the gate electrode layer 507 during the turn-off operation. For this reason, it is not necessary to provide a protection circuit or a cooling mechanism in consideration of surge voltage and heat generation at the time of drawing a large current. Therefore, the fourth conventional example has an advantage that the gate control circuit can be simplified.

  However, in the fourth conventional example, as shown in FIG. 101, the p-type drain layer 509 and the n-type source layer 510 are adjacent to each other in the surface region sandwiched between the grooves 507 running side by side. Since the p-type drain layer 509 has a potential barrier against electrons, the electron current entering from the cathode electrode 511 flows only through the n-type source layer 510 portion. Therefore, there is a problem that the on-characteristics are deteriorated due to an inhibiting factor such as a partial increase in current density.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a power semiconductor device that can simplify a gate control circuit and has a feature of reducing good on-state characteristics and steady loss.

  Further, the third conventional example shown in FIG. 99 has a problem that the power consumption of the semiconductor device increases because the forward voltage drop Vf cannot be improved. This will be described in detail below.

One of the methods for improving the ON voltage (diode forward voltage drop Vf), which is a basic characteristic of the IGBT, is to improve the electron injection efficiency on the cathode side. In order to improve the electron injection efficiency, it is necessary to increase the impurity concentration on the cathode side or increase the effective cathode area. The effective cathode area referred to here is a portion where the n ⁺ region (effective cathode region) composed of the n ⁺ emitter region 109 and the storage region 425a in FIG. 100 is in contact with the p-type base region 107 and the n ⁻ region 105 (the bold line in the figure). Area).

  In the third conventional example, the depth of the groove 413 was 3 to 5 μm as described above. For this reason, when the positive voltage is applied to the gate electrode layer, the spread of the accumulation layer generated around the trench 113 is restricted. Therefore, since a large effective cathode area cannot be secured, the electron injection efficiency on the cathode side cannot be improved, and the ON voltage of the IGBT cannot be reduced.

  Therefore, another object of the present invention is to provide a power semiconductor device that can simplify the gate control circuit and has a low forward voltage drop Vf and a low steady-state loss.

  A semiconductor device according to one aspect of the present invention is a semiconductor device including a diode structure in which a main current flows between both main surfaces across a genuine or first conductivity type semiconductor substrate, and the first conductivity type first. An impurity region, a second conductivity type second impurity region, a control electrode layer, a first electrode layer, and a second electrode layer are provided. The first impurity region of the first conductivity type is formed on the first main surface of the semiconductor substrate and has an impurity concentration higher than that of the semiconductor substrate. The second impurity region of the second conductivity type is formed on the second main surface of the semiconductor substrate and sandwiches the low impurity concentration region of the semiconductor substrate with the first impurity region. The semiconductor substrate has a plurality of parallel grooves on the first main surface, and each of the grooves penetrates the first impurity region from the first main surface to reach the low impurity concentration region of the semiconductor substrate. Yes. The plurality of grooves have first and second grooves. The first impurity region is formed on the entire first main surface of the semiconductor substrate sandwiched between the first groove and the second groove. The control electrode layer is formed in the trench so as to face the first impurity region and the low impurity concentration region of the semiconductor substrate with an insulating film interposed therebetween. The first electrode layer is formed on the first main surface of the semiconductor substrate and is electrically connected to the first impurity region. The second electrode layer is formed on the second main surface of the semiconductor substrate and is electrically connected to the second impurity region.

  In the semiconductor device according to one aspect of the present invention, the control electrode layer is opposed to the first impurity region and the low impurity concentration region of the semiconductor substrate with an insulating film interposed therebetween. That is, the gate control method is a voltage control type. For this reason, it is not necessary to draw a large current from the control electrode during the turn-off operation. Therefore, it is not necessary to provide a protection circuit or a cooling mechanism in the gate control circuit in consideration of a surge voltage and heat generated when a large current flows. Therefore, the gate control circuit can be simplified as compared with the first and second conventional examples.

  This element is a bipolar device. In this bipolar device, both holes and electrons contribute to the operation. For this reason, even if the thickness of the substrate increases corresponding to the increase in breakdown voltage and the current path in the ON state becomes longer, the conductivity is modulated by holes and electrons, so that the resistance is kept low. Therefore, power loss can be reduced and the amount of heat generated can be reduced.

  The control electrode layer faces the first impurity region and the low impurity concentration region of the semiconductor substrate. Therefore, by applying a voltage to the control electrode layer, the low impurity concentration region of the semiconductor substrate in the vicinity of the trench in which the control electrode layer is buried is made a channel having a high electron density state comparable to that of the first impurity region Can do. As a result, the channel region near the trench can be regarded as the first impurity region, and the first impurity region is expanded. When the first impurity region is enlarged, the contact area between the low impurity concentration region of the semiconductor substrate and the enlarged first impurity region, so-called effective cathode area, increases. Thereby, the electron injection efficiency on the cathode side is improved, and the forward voltage drop Vf of the diode can be reduced.

  Only the first impurity region is formed on the first main surface of the semiconductor substrate sandwiched between the grooves. Therefore, compared to the case where impurity regions of different conductivity types coexist on the first main surface between the grooves, the electron current entering from the cathode side is evenly applied to the first main surface of the semiconductor substrate sandwiched between the grooves. Flowing. Therefore, there are no obstruction factors such as a partial increase in current density, and good on-characteristics can be obtained.

  Preferably, in the above aspect, the plurality of grooves have first, second, and third grooves that run parallel to each other. A third impurity region of the second conductivity type is formed on the first main surface of the semiconductor substrate sandwiched between the second and third grooves. The third impurity region is formed shallower than the groove, and is electrically connected to the first electrode layer.

  A third impurity region is provided on the first main surface of the semiconductor substrate so as to be adjacent to the first impurity region with a groove interposed therebetween. The third impurity region has a conductivity type different from that of the first impurity region. For this reason, when the element is turned off, holes are extracted from the third impurity region. Therefore, the turn-off speed of the element can be improved and the turn-off loss can be reduced.

  The third impurity region is provided adjacent to the first impurity region with a groove interposed in the first main surface of the semiconductor substrate. Therefore, a desired turn-off speed and forward voltage drop Vf can be selected by adjusting the ratio of the presence of the third impurity region and the first impurity region.

  A semiconductor device according to another aspect of the present invention is a semiconductor device including a pnpn structure in which a main current flows between both main surfaces with a genuine or first conductivity type semiconductor substrate interposed therebetween. An impurity region, a second conductivity type second impurity region, a second conductivity type third impurity region, a control electrode layer, a first electrode layer, and a second electrode layer are provided. The first impurity region of the first conductivity type is formed on the first main surface of the semiconductor substrate. The second impurity region of the second conductivity type is formed on the second main surface of the semiconductor substrate. The third impurity region of the second conductivity type is formed below the first impurity region so as to sandwich the region of the semiconductor substrate with the second impurity region. The semiconductor substrate has a plurality of grooves running in parallel on the first main surface, and each of the grooves penetrates the first and third impurity regions from the first main surface and reaches the region of the semiconductor substrate. Yes. The plurality of grooves have first and second grooves. The first impurity region is formed on the entire first main surface of the semiconductor substrate sandwiched between the first groove and the second groove. The control electrode layer is formed so as to face the first and third impurity regions and the semiconductor substrate region with an insulating film interposed in the trench. The first electrode layer is formed on the first main surface of the semiconductor substrate and is electrically connected to the first impurity region. The second electrode layer is formed on the second main surface of the semiconductor substrate and is electrically connected to the second impurity region.

  In the semiconductor device according to another aspect of the present invention, the control electrode layer is opposed to the first and third impurity regions and the region of the semiconductor substrate with an insulating film interposed therebetween. That is, the gate control method is a voltage control type. For this reason, it is not necessary to draw a large current from the control electrode layer during the turn-off operation. Therefore, it is not necessary to provide a protection circuit or a cooling mechanism in the gate control circuit in consideration of a surge voltage or heat generated when a large current flows. Therefore, the gate control circuit can be simplified as compared with the first and second conventional examples.

  This element is a bipolar device. In this bipolar device, both holes and electrons contribute to the operation. For this reason, even if the thickness of the substrate increases corresponding to the increase in breakdown voltage, and the on-state current path becomes longer, the conductivity is modulated by holes and electrons. Therefore, the on-resistance is kept low. Therefore, an increase in steady loss can be suppressed and the amount of generated heat can be reduced.

  Only the first impurity region is formed on the first main surface of the semiconductor substrate sandwiched between the grooves. For this reason, compared to the case where impurity regions of different conductivity types coexist on the first main surface, the electron current entering from the cathode side flows evenly on the first main surface of the semiconductor substrate sandwiched between the grooves. Therefore, there are no obstruction factors such as a partial increase in current density, and good on-characteristics can be obtained.

  Preferably, in the above aspect, the plurality of grooves have first, second, and third grooves that run parallel to each other. A second impurity region of the second conductivity type is formed on the first main surface of the semiconductor substrate sandwiched between the second and third grooves. The fourth impurity region is formed shallower than the trench, and is electrically connected to the first electrode layer.

  A fourth impurity region is provided on the first main surface of the semiconductor substrate so as to be adjacent to the first impurity region with a groove interposed. The fourth impurity region has a conductivity type different from that of the first impurity region. For this reason, when the element is turned off, holes are extracted from the fourth impurity region. Therefore, the turn-off speed of this element can be improved and the turn-off loss can be reduced.

  The fourth impurity region is provided on the first main surface of the semiconductor substrate so as to be adjacent to the first impurity region via a groove. Therefore, a desired turn-off speed and forward voltage drop Vf can be selected by adjusting the ratio of the presence of the fourth impurity region and the first impurity region.

  A semiconductor device according to still another aspect of the present invention is a semiconductor device including a diode structure in which a main current flows between both main surfaces with a genuine or first conductivity type semiconductor substrate interposed therebetween, and the first conductivity type first semiconductor device. A first impurity region, a second impurity region of a second conductivity type, a third impurity region of a second conductivity type, a fourth impurity region of a first conductivity type, a control electrode layer, a first electrode layer, 2 electrode layers. The first impurity region of the first conductivity type is formed on the first main surface of the semiconductor substrate and has an impurity concentration higher than that of the semiconductor substrate. The second impurity region of the second conductivity type is formed on the second main surface of the semiconductor substrate. The semiconductor substrate has a parallel groove formed so as to sandwich the first impurity region. The third impurity region of the second conductivity type is formed on the first main surface, which is the sidewall of the groove. The fourth impurity region of the first conductivity type is provided immediately below the third impurity region so as to be in contact with the side wall of the trench and the region of the semiconductor substrate, and has a lower concentration than the first impurity region. The control electrode layer is formed so as to face the third and fourth impurity regions and the semiconductor substrate region with an insulating film interposed in the trench. The first electrode layer is formed on the first main surface of the semiconductor substrate and is electrically connected to the first and third impurity regions. The second electrode layer is formed on the second main surface of the semiconductor substrate and is electrically connected to the second impurity region.

  In the semiconductor device according to still another aspect of the present invention, the control electrode layer faces the third and fourth impurity regions and the region of the semiconductor substrate with an insulating film interposed therebetween. That is, the gate control method is a voltage control type. For this reason, it is not necessary to draw a large current from the control electrode layer during the turn-off operation. Therefore, it is not necessary to provide a protection circuit or a cooling mechanism in the gate control circuit in consideration of a surge voltage and heat generated when a large current flows. Therefore, the gate control circuit can be simplified as compared with the first and second conventional examples.

  This element is a bipolar device. In this bipolar device, both holes and electrons contribute to the operation. For this reason, even if the thickness of the substrate increases corresponding to the increase in the withstand voltage, and the current path in the on state becomes longer, the conductivity is modulated by holes and electrons. Therefore, the resistance is kept low. Therefore, the calorific value can be reduced and an increase in steady loss can be suppressed.

  The control electrode layer faces the third and fourth impurity regions and the semiconductor substrate region. For this reason, by applying a positive voltage to the control electrode layer, it is possible to make the entire region near the groove in which the control electrode layer is buried have a high electron density comparable to that of the first impurity region. As a result, all the regions in the vicinity of the trench can be regarded as the first impurity region, and the first impurity region is expanded. When the first impurity region is enlarged, the contact area between the semiconductor substrate region and the enlarged first impurity region, so-called effective cathode area, increases. Thereby, the electron injection efficiency on the cathode side is improved, and the forward voltage drop Vf of the diode can be reduced.

  Further, by applying a voltage to the control electrode layer, the region of the opposite conductivity type in the vicinity of the groove can have a high electron density comparable to that of the first impurity region. For this reason, a region of the opposite conductivity type such as the third impurity region is regarded as the first impurity region together with the fourth impurity region. As described above, since the third impurity region becomes the first impurity region in addition to the fourth impurity region, the effective cathode area is further increased. Therefore, the electron injection efficiency on the cathode side can be further improved, and the forward voltage drop Vf of the diode can be further reduced.

  Preferably, in the above aspect, an isolation impurity region formed on the first main surface of the semiconductor substrate is further provided. Among the plurality of grooves arranged so as to be parallel to each other, the other groove is located on one side of the grooves arranged in the outermost row, and the isolation impurity region is arranged in the outermost row on the other side. It is in contact with the groove and formed deeper than the groove.

  Since the isolation impurity region is provided so as to surround the formation region of the diode structure or the thyristor structure, the effect of electrical isolation from other elements can be enhanced and the device breakdown voltage can be improved and stabilized.

  In the above aspect, the depth of the groove from the first main surface is preferably 5 μm or more and 15 μm or less.

  Since the depth of the groove is 5 μm or more, a high electron density accumulation region generated along the side wall of the groove when the main current is conducted can be widely generated. Therefore, the effective cathode area can be secured widely compared with the third conventional example. Therefore, the electron injection efficiency on the cathode side is further improved, and the forward voltage drop Vf can be reduced. Further, since it is difficult to form a groove having a fine width (0.6 μm or less) and deeper than 15 μm with the current apparatus, the depth of the groove is 15 μm or less.

  A semiconductor device according to still another aspect of the present invention is a semiconductor device in which a main current flows between both main surfaces of a genuine or first conductive type semiconductor substrate, the second conductive type first impurity region, A second conductivity type second impurity region, a first conductivity type third impurity region, a control electrode layer, and first and second electrode layers are provided. The first impurity region is formed on the first main surface side of the semiconductor substrate. The second impurity region is formed on the second main surface of the semiconductor substrate and sandwiches the low concentration region of the semiconductor substrate with the first impurity region. The semiconductor substrate has a groove reaching the region of the semiconductor substrate from the first main surface through the first impurity region. The third impurity region is formed on the first impurity region and in contact with the sidewall of the groove on the first main surface of the semiconductor substrate. The control electrode layer is formed in the trench so as to face the first and third impurity regions and the region of the semiconductor substrate with the first insulating film interposed therebetween, and the first and second main surfaces are applied by the applied control voltage. The current flowing between them is controlled. The first electrode layer is formed on the first main surface of the semiconductor substrate and is electrically connected to the first and third impurity regions. The second electrode layer is formed on the second main surface of the semiconductor substrate and is electrically connected to the second impurity region. When the first and second main surfaces of the semiconductor substrate are in a conductive state, a first conductivity type accumulation region is formed around the groove so as to be in contact with the third impurity region. The ratio Rn = (n / n + p) between the area n where the effective cathode region including the third impurity region and the accumulation region is in contact with the first impurity region and the region of the semiconductor substrate and the area p on the first main surface side of the first impurity region ) Becomes 0.4 or more and 1.0 or less in the conductive state.

  Since the ratio Rn is 0.4 or more and 1.0 or less, which is higher than that of the third conventional example, the electron injection efficiency on the cathode side is improved as compared with the conventional example, and the forward voltage drop Vf can be reduced.

  In the above aspect, the depth of the groove from the first main surface is preferably 5 μm or more and 15 μm or less.

  Since the depth of the groove is 5 μm or more, a high electron density accumulation region generated along the side wall of the groove when the main current is conducted can be widely generated. Therefore, the effective cathode area can be secured widely compared with the third conventional example. Therefore, the electron injection efficiency on the cathode side is further improved, and the forward voltage drop Vf can be reduced. Further, since it is difficult to form a groove having a fine width (0.6 μm or less) and deeper than 15 μm with the current apparatus, the depth of the groove is 15 μm or less.

  Preferably, in the above aspect, a plurality of grooves are formed so as to have first, second and third grooves. First and third impurity regions are formed in the semiconductor substrate sandwiched between the first and second grooves. Only the region of the semiconductor substrate is located on the first main surface of the semiconductor substrate sandwiched between the second and third grooves. A conductive layer is formed on the semiconductor substrate sandwiched between the second and third grooves with a second insulating layer interposed. The conductive layer is electrically connected to each of the control electrode layers embedded in the second and third grooves.

  Since the conductive layer is electrically connected to the control electrode layer, when a positive voltage is applied to the control electrode layer when the main current is conducted, for example, a positive voltage is also applied to the conductive layer. This conductive layer is opposed to the region of the semiconductor substrate between the second and third grooves with a second insulating layer interposed. For this reason, when a positive voltage is applied to the conductive layer, the surface region sandwiched between the second and third grooves can be in a high electron density state comparable to that of the third impurity region. Therefore, the third impurity region is enlarged by the surface region of the substrate sandwiched between the second and third grooves. Therefore, the effective cathode area is increased, the electron injection efficiency on the cathode side is further improved, and the forward voltage drop Vf of the diode can be further reduced.

  Preferably, in the above aspect, a plurality of grooves are formed so as to have first, second and third grooves. First and third impurity regions are formed in the semiconductor substrate sandwiched between the first and second grooves. A fourth impurity region of a second conductivity type having a lower concentration than the second impurity region is formed on the first main surface of the semiconductor substrate sandwiched between the second and third grooves. On the semiconductor substrate sandwiched between the second and third grooves, a conductive layer is formed with a second insulating layer interposed. This conductive layer is electrically connected to each of the control electrode layers embedded in the second and third grooves.

  Since the conductive layer is electrically connected to the control electrode layer, when a positive voltage is applied to the control electrode layer when the main current is conducted, for example, a positive voltage is also applied to the conductive layer. The conductive layer is opposed to the fourth impurity region between the second and third grooves with the second insulating layer interposed. Since the fourth impurity region has a lower concentration than the second impurity region, when a positive voltage is applied to the conductive layer, the surface region sandwiched between the second and third grooves is the same as the third impurity region. It becomes a high electron density state. Therefore, the third impurity region is enlarged by the surface region of the substrate sandwiched between the second and third grooves. Therefore, the effective cathode area is increased, the electron injection efficiency on the cathode side is further improved, and the forward voltage drop Vf of the diode can be further reduced.

  Further, since the fourth impurity region is set at a lower concentration than the second impurity region, a thyristor operation occurs during the operation. As a result, there is an advantage that the ON voltage is lowered when the rated current is applied.

  When the element is turned off, for example, a negative voltage is applied to the control electrode layer. In this case, since a negative voltage is also applied to the conductive layer, a region having a higher hole density than the fourth impurity region is generated on the surface of the fourth impurity region below the conductive layer. By forming the region having a high hole density, holes are easily extracted at the time of turn-off, the turn-off speed of the device can be improved, and the turn-on loss can be reduced.

  Preferably, in the above aspect, the first impurity region is formed so as to be in contact with the sidewall of the groove below the first impurity region and sandwich the region of the semiconductor substrate with the second impurity region, and has a lower concentration than the first impurity region. A fourth impurity region of the second conductivity type is further provided.

  Since the fourth impurity region has a lower concentration than the first impurity region, if a negative voltage is applied to the control electrode layer when the main current is cut off, the first impurity region is formed in the fourth impurity region along the sidewall of the trench. A region with a higher hole density than the concentration of s. Since this region having a high hole density is formed, holes that are carriers can be drawn smoothly when the device is turned off, and the switching characteristics can be improved.

  A semiconductor device according to still another aspect of the present invention is a semiconductor device in which a current flows between both main surfaces of a genuine or first conductive type semiconductor substrate, the second impurity type first impurity region, A second impurity region of conductivity type, a third impurity region of first conductivity type, a fourth impurity region of second conductivity type, a control electrode layer, and first and second electrode layers are provided. The first impurity region is formed on the first main surface side of the semiconductor substrate. The second impurity region is formed on the second main surface of the semiconductor substrate and sandwiches the low concentration region of the semiconductor substrate with the first impurity region. The semiconductor substrate has a groove reaching the region of the semiconductor substrate from the first main surface through the first impurity region. The third impurity region is formed on the first impurity region and in contact with the sidewall of the groove on the first main surface of the semiconductor substrate. The fourth impurity region is formed on the first impurity region and adjacent to the third impurity region on the first main surface of the semiconductor substrate, and has a higher concentration than the first impurity region. The control electrode layer is formed in the trench so as to oppose the first and third impurity regions and the low concentration region of the semiconductor substrate with the first insulating film interposed therebetween, and the first and second control electrodes are applied with a given control voltage. The current flowing between the main surfaces is controlled. The first electrode layer is formed on the first main surface of the semiconductor substrate and is electrically connected to the third and fourth impurity regions. The second electrode layer is formed on the second main surface of the semiconductor substrate and is electrically connected to the second impurity region. The depth from the first main surface of the groove is Dt, the width of the groove is Wt, the depth of the third impurity region from the first main surface is De, and from one groove of the third impurity region to the other When the width in the direction toward the groove is We and the pitch between adjacent grooves is Pt,

It becomes.
The ratio Rn = (n / n + p) can be approximated by the above equation depending on the size of each part. Thus, the dimensions of the respective parts are set so that the ratio Rn is 0.4 or more. Therefore, the electron injection efficiency on the cathode side is improved as compared with the third conventional example, and the vertical voltage drop Vf can be reduced.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a main current flows between both main surfaces of a genuine or first conductivity type semiconductor substrate, and includes the following steps.

  First, the first impurity region of the second conductivity type is formed by selectively implanting ions into the first main surface of the semiconductor substrate. A second impurity region of the second conductivity type is formed on the second main surface of the semiconductor substrate. By selectively implanting ions, a third impurity region of the first conductivity type is formed on the first main surface in the first impurity region. Then, by performing anisotropic etching on the first main surface, a plurality of grooves having first, second and third grooves are formed in the semiconductor substrate. The first main surface sandwiched between the first and second grooves has first and third impurity regions formed along the side walls of the groove, and the first main surface sandwiched between the second and third grooves. Only the low concentration region of the semiconductor substrate is located on one main surface. A control electrode layer is formed in the trench so as to face the low concentration region of the semiconductor substrate and the first and third impurity regions sandwiched between the first and second impurity regions with the first insulating film interposed therebetween. The By selectively implanting ions, a fourth impurity region of the second conductivity type having a higher impurity concentration than the first impurity region is formed on the first main surface in the first impurity region so as to be adjacent to the third impurity region. It is formed. A first electrode layer is formed on the first main surface so as to be electrically connected to the third and fourth impurity regions. A second electrode layer is formed on the second main surface so as to be electrically connected to the second impurity region.

  According to the method of manufacturing a semiconductor device of the present invention, only the low concentration region of the semiconductor substrate is located on the first main surface sandwiched between the second and third grooves. For this reason, the first impurity region is not positioned on the first main surface sandwiched between the second and third grooves. Therefore, by increasing the ratio Rn, the purpose of improving the element characteristics can be achieved and the main breakdown voltage can be maintained.

  In the semiconductor device according to one aspect of the present invention, since the control electrode layer is a voltage-controlled element disposed opposite to the first impurity region and the low impurity concentration region of the semiconductor substrate with an insulating film interposed therebetween, The gate control circuit can be simplified as compared with the current control type element.

  Further, since the element including the diode structure according to the present invention is a bipolar device, a low steady loss can be obtained.

In addition, since the gate electrode layer forms an n ⁺ accumulation layer by applying a positive bias and the effective cathode area can be increased, the forward voltage drop Vf of the diode can be reduced.

  Further, since only the first impurity region is formed on the first main surface of the semiconductor substrate sandwiched between the grooves, good on-characteristics can be obtained.

  Preferably, in the above aspect, a third impurity region having a conductivity type different from that of the first impurity region is provided on the first main surface of the semiconductor device with a groove adjacent to the first impurity region. For this reason, turn-off speed can be improved, turn-off loss can be reduced, and switching tolerance and short-circuit tolerance can be improved.

  Further, by adjusting the existence ratio of the first impurity region and the third impurity region, a desired turn-off speed and forward voltage drop Vf can be selected.

  In the semiconductor device according to another aspect of the present invention, as described in the above aspect 1, the gate control system is a voltage control type. For this reason, the gate control circuit can be simplified.

Moreover, since this element is a bipolar device, a low steady loss can be obtained.
Further, as described in the above aspect 1, the control electrode layer forms an n ⁺ inversion layer in the p-type region and an n ⁺ storage layer in the n ⁻ region by applying a positive bias, thereby increasing the effective cathode area. Therefore, the forward voltage drop Vf of the diode can be reduced.

  Further, a fourth impurity region having a conductivity type different from that of the first impurity region is provided on the first main surface of the semiconductor substrate with a groove adjacent to the first impurity region. For this reason, turn-off speed can be improved and turn-off loss can be reduced.

  Further, by adjusting the existence ratio of the first impurity region and the fourth impurity region, a desired turn-off speed and forward voltage drop Vf can be selected.

  In the semiconductor device according to still another aspect of the present invention, the gate control method is a voltage control type. For this reason, the gate control circuit can be simplified.

Moreover, since this element is a bipolar device, a low steady loss can be obtained.
Similarly to the effect of the above aspect, the effective cathode area due to the gate potential can be increased, and the forward voltage drop Vf of the diode can be reduced.

  The third impurity region is also regarded as an effective cathode region together with the first impurity region. For this reason, the cathode area in the main current conduction state is further increased, and the forward voltage drop Vf of the diode can be further reduced.

  In the above aspect, since the isolation impurity region is preferably provided so as to surround the formation region of the diode or thyristor, the ability to electrically isolate the diode or thyristor from other regions is improved, and the device breakdown voltage and stability are improved. Can be enhanced.

  In the above aspect, since the depth of the groove from the first main surface is preferably 5 μm or more and 15 μm or less, the forward voltage drop Vf can be further reduced, and the groove can be easily formed even with the current apparatus.

  In the semiconductor device according to still another aspect of the present invention, since the ratio Rn is as high as 0.4 or more and 1.0 or less, the electron injection efficiency on the cathode side is improved as compared with the conventional example, and the forward voltage drop Vf can be reduced. .

  In the above aspect, since the depth of the groove is preferably 5 μm or more and 15 μm or less, the forward voltage drop Vf can be further reduced, and the groove can be easily formed even with the current apparatus.

  In the above aspect, preferably, the conductive layer is electrically connected to the control electrode layer, and this control electrode layer faces the region of the semiconductor substrate surface between the second and third grooves, so that the effective cathode area Can be further increased, and the forward voltage drop Vf of the diode can be further reduced.

  Preferably, in the above aspect, since the low concentration second ion impurity region is formed in the region of the semiconductor substrate surface sandwiched between the second and third grooves, a thyristor operation occurs during operation, and as a result, when a rated current is passed There is an advantage that the ON voltage is lowered.

Preferably, in the above aspect, since the fourth impurity region formed below the first impurity region has a lower concentration than the first impurity region, when a negative voltage is applied to the control electrode layer when the main current is cut off, A p ⁺ inversion layer is formed along the side wall of the groove, holes can be drawn smoothly, and switching characteristics, switching tolerance and short-circuit tolerance can be improved.

  In the semiconductor device according to still another aspect of the present invention, the ratio Rn can be approximated by the size of each part, and the approximated ratio Rn is as high as 0.4 or more. The injection efficiency is improved, and the forward voltage drop Vf can be reduced.

  In the semiconductor device manufacturing method of the present invention, only the low concentration region of the semiconductor substrate is located on the semiconductor substrate sandwiched between the second and third grooves, and the first impurity region is not formed. For this reason, the purpose of improving the element characteristics can be achieved by increasing the ratio Rn, and the main breakdown voltage can be maintained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Hereinafter for convenience, there is a case where the n ⁺ emitter region of the cathode region and n ⁺ high concentration impurity region and the anode region which is p ⁺ high concentration impurity region is referred to as p ⁺ collector region.

(Embodiment 1)
FIG. 1 is a plan view schematically showing a configuration of a semiconductor device according to a first embodiment corresponding to claim 1 of the present invention, and FIG. 2 shows a state in which a cathode electrode 17 is formed in the state of FIG. It is a top view. FIG. 3 is a schematic cross-sectional view taken along the line AA ′ of FIG.

1 to 3, the present embodiment shows an example having a pin diode. This pin diode includes a second conductivity type p ⁺ anode (collector) region 1 formed on the second main surface, an n type buffer region 3, and an n ⁻ region which is a first conductivity type low impurity concentration semiconductor substrate. 5, an n ⁺ cathode region (n ⁺ emitter region) 7 of the first conductivity type formed on the first main surface, insulating films 11 and 15, a gate electrode layer 13 as a control electrode layer, and a first electrode layer A cathode electrode 17 and an anode electrode 19 as a second electrode layer.

A groove 9 is provided on the first main surface where the cathode region 7 is formed. This groove 9 passes through the n ⁺ cathode region 7 and reaches the n ⁻ region 5 of the substrate.

  As shown in FIG. 1, the groove 9 has a planar shape that generally surrounds a quadrangle, and has portions that run parallel to each other within the quadrangle.

The n ⁺ cathode region 7 is formed on the entire first main surface of the semiconductor substrate sandwiched between the parallel grooves 9.

The width W of the groove 9 is, for example, not less than 0.8 μm and not more than 1.2 μm, and the depth D ₁ is practically not less than 5.0 μm and not more than 15.0 μm.

A gate insulating film 11 (for example, a silicon thermal oxide film) is provided along the inner wall surface of the groove 9. A gate electrode layer 13 is formed of a phosphorus-doped polysilicon film so as to fill the groove 9 and to protrude from the inside of the groove 9 at the upper end. The gate electrode layer 13 is opposed to the side surface of the n ⁺ cathode region 7 and the side surface and bottom surface of the n ⁻ region 5 with the gate insulating film 11 interposed therebetween.

  Further, the gate electrode layer 13 may be pulled up from the trench to a portion having the insulating film on the first main surface (not shown).

  For example, an insulating film 15 of a BPSG (Boro Phospho-Silicate Glass) film is formed so as to cover the upper end of the gate electrode layer 13.

  Further, an opening is formed in a part of the BPSG insulating film 15, and a metal wiring is connected to the gate electrode through the opening (not shown).

  The cathode electrode 17 that is the first electrode layer is electrically connected to the cathode region 7. The cathode electrode 17 is formed on a region surrounded by the groove 9. In the present application, the planar region where the cathode electrode 17 is formed is referred to as a diode formation region.

On the other hand, the anode electrode 19 as the second electrode layer is electrically connected to the p ⁺ collector region 1 formed on the second main surface.

As for the impurity concentration of each part, the p ⁺ collector region 1 is 1 × 10 ¹⁶ cm ⁻³ or more and 5 × 10 ²¹ cm ⁻³ or less, and the n-type buffer region 3 is 1 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, n ⁻ region 5 is 1 × 10 ¹² cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less, cathode region 7 is 1 × 10 ¹⁷ cm ⁻³ or more, and n ⁻ semiconductor The impurity concentration is higher than that of the substrate region 5.

The impurity concentration of n-type buffer region 3 may be lower than the impurity concentration of p ⁺ collector region 1 and higher than the impurity concentration of n ⁻ region 5.

The n-type buffer region 3 is originally used for the purpose of improving the main breakdown voltage of the element, but is used for the purpose of suppressing the injection of holes from the p ⁺ anode region 1 in the present application.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
4 to 9 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. Referring first to FIG. 4, p ⁺ collector region 1, n type buffer region 3 and the n ^- region 5 is formed by laminating.

Referring to FIG. 5, trench 9a is formed by anisotropic dry etching or the like used in a normal semiconductor process so as to extend from the surface of n ⁻ region 5 to the inside thereof.

  Referring to FIG. 6, insulating film 11 made of a silicon oxide film serving as a gate insulating film is formed along the inner wall surface of trench 9 by, eg, thermal oxidation.

  Note that the MOS characteristics can be improved by performing a treatment such as sacrificial oxidation before the formation of the gate oxide film 11.

  Referring to FIG. 7, gate electrode layer 13 is formed so that trench 9 is embedded and the upper end protrudes from trench 9. This gate electrode layer 13 is formed of a material of polycrystalline silicon doped with an n-type impurity such as phosphorus (hereinafter referred to as doped polysilicon).

  Referring to FIG. 8, an insulating film 15 made of, for example, a CVD oxide film such as BPSG is formed so as to cover the upper end of the gate electrode layer 13 protruding from the trench 9.

Referring to FIG. 9, ion implantation of n-type impurity elements such as Sb, As, and P is selectively performed on the surface of n ⁻ region 5 sandwiched between grooves 9. Thereafter, impurities implanted by heat treatment or the like are diffused, and n ⁺ cathode region 7 is formed on the entire surface of n ⁻ region 5 sandwiched between the trenches. The cathode region 7 is formed shallower than the depth of the groove 9.

Thereafter, the cathode electrode 17 is formed so as to be electrically connected to the cathode region 7, and the anode electrode 19 is formed so as to be electrically connected to the p ⁺ collector region 1, so that the semiconductor shown in FIG. 2 and FIG. The device is completed.

  Next, a method for controlling the main current conduction state and the main current cutoff state of the semiconductor device of the present embodiment will be described.

Referring to FIG. 3, the main current conduction (ON) state is realized by applying a slight positive voltage to gate electrode layer 13. In this case, current flows from p ⁺ collector region 1 to n ⁺ cathode region 7. This operation is the same as the pin diode, n ⁺ a cathode region 7 n ^- electrons into the semiconductor substrate 5 is injected, are also holes injected from the p ⁺ collector region 1, n ^- in the substrate 5, conductivity Modulation occurs, and the voltage in the on state, that is, the on voltage is lowered.

  Next, the main current cutoff state is realized by applying a negative voltage to the gate electrode layer 13. When a negative voltage is applied to the gate electrode layer 13, a depletion layer extends around the trench 9, the current path of the main current is cut off, and the gate electrode layer 13 can be turned off.

In the semiconductor device of this embodiment, particularly the gate electrode layer 13 as shown in FIG. 3 the n ^- faces interposed an insulating film 11 on the side walls of the region 5 and cathode region 7. That is, the control method by the gate electrode layer 13 is a voltage control type. For this reason, in the turn-off operation, the gate electrode layer 13 does not draw a part of the main current as the gate current, unlike the case of SITh in which the gate is formed using the pn junction. Therefore, it is not necessary to supply a large current to the gate control circuit, the gate drive circuit can be simplified, and it is not necessary to provide a protection circuit in consideration of a surge voltage generated when the gate current flows, and the heat generation is considered. A cooling device is also unnecessary. Therefore, compared to the first and second conventional examples, the gate control circuit can be simplified in the semiconductor device of the present embodiment, and the entire system can be reduced in size, simplified, and energy-saving.

The pin diode is a bipolar device. In this bipolar device, both holes and electrons contribute to the operation. Therefore, the thickness of the substrate increases corresponding to the increase in breakdown voltage, and in particular, even if the thickness T ₀ of the n ⁻ region 5 in FIG. Therefore, the on-resistance (on-voltage) can be kept low. Therefore, an increase in steady loss can be suppressed and the amount of heat generated can be reduced.

As shown in FIG. 3, the gate electrode layer 13 faces the n ⁻ region 5 and the cathode region 7. Therefore, when a positive voltage is applied to the gate electrode layer 13 in the main current conduction state, an n ⁺ accumulation region 21 in which a large number of electrons are attracted is generated around the trench 9 as shown in FIG. As a result, the n ⁺ region that becomes the cathode region 7 is enlarged.

Here, as a method of improving the forward voltage drop Vf of the diode, there is a method of increasing the effective cathode area as described above. The effective cathode area referred to here is a contact area between the n ⁻ region 5 and the n ⁺ cathode region 7 in FIG.

In the semiconductor device of this embodiment, as shown in FIG. 10, the n ⁺ accumulation region 21 is formed, and the n ⁺ cathode region 7 is expanded. This increases the contact area between the n ⁻ region 5 and the total effective cathode region in which the n ⁺ accumulation region 21 is added to the n ⁺ cathode region 7. Therefore, the electron injection efficiency on the cathode side is improved, and the forward voltage drop Vf of the diode can be reduced. Thus, even when the first main surface (cathode side) is the entire surface of the n ⁺ cathode region, the on-state loss can be reduced by increasing the n ⁺ region in the entire semiconductor chip by expanding the effective cathode region. . That is, the power consumption of the semiconductor device can be reduced.

In the semiconductor device of this embodiment, since the n ⁺ cathode region 7 to the first major surface over the entire surface of the cathode side is formed, when (Fig. 100 to the first main surface and the n region and p region coexist Compared with FIG. 102), the electron current entering from the cathode side flows evenly on the first main surface of the semiconductor substrate sandwiched between the grooves 9. Therefore, a partial increase in current density is prevented and the on-state characteristics are improved.

(Embodiment 2)
FIG. 11 is a plan view schematically showing the configuration of the semiconductor device according to the second embodiment corresponding to claims 1 and 6 of the present invention. FIG. 12 shows a state in which the cathode electrode 17 is formed in the state of FIG. FIG. FIG. 13 is a schematic sectional view taken along line BB ′ of FIG.

Referring to FIGS. 11 to 13, the semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment in that p ⁺ isolation impurity region 23 is provided.

The p ⁺ isolation impurity region 23 is formed on the surface of the n ⁻ region 5 so as to surround the planar region of the diode forming region and to be in contact with the groove 9. The p ⁺ isolation impurity region 23 is formed deeper than the trench 9.

  In addition, since it is the same as that of Embodiment 1 about another structure, the same code | symbol is attached | subjected about the same member and the description is abbreviate | omitted.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
14 to 16 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

The semiconductor device manufacturing method of the present embodiment first undergoes the same steps as in the first embodiment shown in FIG. Thereafter, referring to FIG. 14, ap ⁺ region 23a is selectively formed at a position surrounding the diode formation region by an ion implantation method or a deposition method of an element such as B that becomes a p-type impurity. Thereafter, heat treatment or the like is performed.

Referring to FIG. 15, p-type impurities are diffused by the above heat treatment, and p ⁺ isolation impurity region 23 is formed at a predetermined position.

Referring to FIG. 16, thereafter, grooves 9a are formed on the surface of n ⁻ region 5 so as to have portions parallel to each other. Since the subsequent steps are substantially the same as those of the first embodiment, description thereof is omitted.

  The on / off state control method using the gate is almost the same as in the first embodiment.

Referring to FIG. 13, when a negative voltage is applied to gate electrode layer 13, the potential of p ⁺ isolation impurity region 23 is fixed by an inversion layer formed around gate electrode layer 13. As a result, the pn junction formed by p ⁺ isolation impurity region 23 and n ⁻ region 5 is in a reverse bias state. Thereby, the main breakdown voltage holding capability of the element can be enhanced.

  According to the semiconductor device of the present embodiment, as shown in FIGS. 12 and 13, the p-type impurity region 23 is formed deeper than the trench 9 so as to surround the diode formation region. Therefore, other elements and this diode can be electrically separated and the main withstand voltage holding capability of the elements can be enhanced.

(Embodiment 3)
FIG. 17 is a plan view schematically showing the configuration of the semiconductor device according to the third embodiment corresponding to claim 2 of the present invention, and FIG. 18 shows a state in which cathode electrode 17 is formed in the state of FIG. It is a top view. FIG. 19 is a schematic sectional view taken along the line CC ′ of FIG.

17 to 19, the semiconductor device of the present embodiment is provided with a p ⁺ high concentration region 31 (hereinafter referred to as a p ⁺ contact region) as compared with the semiconductor device of the first embodiment. Is different.

The p ⁺ contact region 31 is formed on the first main surface in the diode forming region so as to be adjacent to the n ⁺ cathode region 7 with the grooves 9b and 9c interposed therebetween. Further, the p ⁺ contact region 31 is formed in a surface region sandwiched between the parallel grooves 9b and 9c as shown in FIG. The p ⁺ contact region 31 is electrically connected to the cathode electrode 17. The p ⁺ contact region 31 has an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or more. The p ⁺ contact regions 31 and the n ⁺ cathode regions 7 are alternately arranged with a groove interposed. Moreover, the number of the grooves 9a, 9b,... Running in parallel can be arbitrarily selected.

  Since the configuration other than this is substantially the same as that of the first embodiment, the same members are denoted by the same reference numerals, and the description thereof is omitted.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
20 and 21 are schematic cross-sectional views illustrating the manufacturing method according to the third embodiment of the present invention in the order of steps.

One of the semiconductor device manufacturing methods of the present embodiment first undergoes the same steps as those of the first embodiment shown in FIGS. Thereafter, referring to FIG. 20, by using a normal photolithography process, a portion other than a portion where the p ⁺ contact region is to be formed is masked with a photoresist, and ion implantation and depletion of an element such as boron as a p-type impurity are performed. Using a method such as position, a p ⁺ contact region 31 is formed on the surface of the n ⁻ region 5 sandwiched between the parallel grooves 9b and 9c. The p ⁺ contact region 31 is in deep enough than 1.0μm or less 0.5 [mu] m, it is shallower than the groove 9.

Referring to FIG. 21, also a p ⁺ contact region 31, so as to be adjacent to each other through the groove 9b or 9c, the grooves 9a and 9b, n is sandwiched 9c and 9d ^- n on the entire surface of the regions 5 ⁺ cathode region 7 is formed by a combination of a photolithography process and an ion implantation process similar to those described above. Since the subsequent steps are substantially the same as those in the first embodiment, description thereof is omitted.

Further, the formation order of the p ⁺ contact region 31 and the n ⁺ cathode region 7 may be reversed, and the elements and heat treatment used for diffusion in each region are adjusted according to the required diffusion depth.

  Since the method for controlling the main current conduction state and the main current cutoff state of the semiconductor device of the present embodiment is also the same as that of the first embodiment, the description thereof will be omitted.

In the semiconductor device of the present embodiment, as shown in FIG. 19, the p ⁺ contact region 31 is arranged adjacent to the n ⁺ cathode region 7 through the groove 9b or 9c. For this reason, the forward voltage drop Vf can be reduced, and the turn-off time when the main current is interrupted can be shortened. This will be described in detail below.

  FIG. 22 is a graph showing the relationship between the forward voltage drop Vf and the ratio Rn, which is obtained by simulating a general trench IGBT, trench diode, or the like. Here, the ratio Rn is an abundance ratio of the n-type impurity region when the n-type impurity region 7 and the p-type impurity region 31 coexist on the first main surface side (cathode side) as shown in FIGS. Yes, given by

However, the effective cathode region referred to here includes an n ⁺ accumulation region 21 (FIG. 10) formed when a positive voltage is applied to the gate electrode.

Rn = n ⁺ region (effective cathode region) / (n ⁺ region (effective cathode region) + p-type region) (1)
As can be seen from FIG. 22, the forward voltage drop Vf decreases as the ratio Rn increases, that is, as the existence ratio of the n-type impurity region increases. For this reason, when the region in contact with the n ⁻ layer is entirely formed of the cathode region (n-type impurity region) and there is no p-type impurity region (when the ratio Rn = 1), the forward voltage drop Vf is most reduced. And power consumption of the semiconductor device can be reduced.

On the other hand, FIG. 23 is a graph showing the relationship between the current I flowing through the element and the time when the main current is cut off. Referring to FIG. 23, when a negative voltage is applied to the gate electrode layer (time t ₀ ) at the time of turn-off, the main current path sandwiched between the groove-shaped gate electrodes is depleted, and the n ⁺ cathode region 7 Since the injection of electrons is stopped, the current I flowing in the diode first decreases rapidly, and then gradually decreases while the carriers (holes) accumulated in the n ⁻ semiconductor substrate are attenuated. This slowly decreasing current portion is called a so-called tail current.

As shown in FIG. 19, in the semiconductor device of the present embodiment, p ⁺ contact region 31 is provided adjacent to n ⁺ cathode region 7. For this reason, a part of the hole current I ₁ of the current I ₀ flowing in the diode when the main current is cut off is drawn from the p ⁺ contact region 31 to the cathode electrode 17. As a result, the current I flowing in the diode is reduced, and in particular, the tail current is rapidly reduced. For this reason, the turn-off time can be shortened.

Thereby, in the semiconductor device of the present embodiment, by adjusting the abundance ratio of the cathode region 7 and the p ⁺ contact region 31 on the surface of the n ⁻ region 5, the performance of various diodes can be obtained from the above-described equation (1). It is possible to select the optimum forward voltage drop Vf and turn-off time according to the above.

(Embodiment 4)
FIG. 24 is a plan view schematically showing the configuration of the semiconductor device according to the fourth embodiment corresponding to claims 2 and 6 of the present invention. FIG. 25 shows a state in which the cathode electrode 17 is formed in the state of FIG. FIG. FIG. 26 is a schematic sectional view taken along the line DD ′ of FIG.

24 to 26, the semiconductor device of the present embodiment is different from that of the third embodiment in that p ⁺ isolation impurity region 23 is provided.

The p ⁺ isolation impurity region 23 is formed on the surface of the n ⁻ region 5 so as to surround the planar region of the diode formation region and to be in contact with the groove 9. The p ⁺ isolation impurity region 23 is formed deeper than the trench 9.

  In addition, since it is the same as that of Embodiment 3 about another structure, the same code | symbol is attached | subjected about the same member and the description is abbreviate | omitted.

When a negative voltage is applied to the gate electrode layer 13, the potential of the p ⁺ isolation impurity region 23 is fixed by an inversion layer formed around the gate electrode layer 13. As a result, the pn junction formed by p ⁺ isolation impurity region 23 and n ⁻ region 5 is in a reverse bias state. Thereby, the main breakdown voltage holding capability of the element can be enhanced.

  According to the semiconductor device of the present embodiment, as shown in FIGS. 25 and 26, the p-type impurity region 23 is formed deeper than the trench 9 so as to surround the diode formation region. For this reason, other elements and the diode can be electrically separated and the main breakdown voltage holding capability of the elements can be enhanced.

(Embodiment 5)
FIG. 27 is a plan view schematically showing a configuration of the semiconductor device according to the fifth embodiment corresponding to claim 3 of the present invention, and FIG. 28 shows a state in which cathode electrode 17 is formed in the state of FIG. It is a top view. FIG. 29 is a schematic sectional view taken along line EE ′ of FIG.

27 to 29, the present embodiment shows an example having a four-layer pnpn diode. The four-layer pnpn diode has a p ⁺ collector region 1, an n-type buffer region 3, an n ⁻ region 5, a p-type base region 41, and an n ⁺ cathode region 7. The p ⁺ collector region 1, the n-type buffer region 3, the n ⁻ region 5, the p-type base region 41 and the n ⁺ cathode region 7 are sequentially stacked. This n ⁺ cathode region 7 side of the surface, through the n ⁺ cathode region 7 and p type base region 41 n ^- to reach the region 5, and a groove 9 so as to have a portion running parallel to each other forming Has been. An n ⁺ cathode region 7 is formed on the entire surface sandwiched between the mutually parallel grooves 9.

The p-type base region 41 has an impurity concentration of 1 × 10 ¹⁴ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less, and the n ⁺ cathode region 7 has an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more. Have.

  In addition, since it is the same as that of Embodiment 1 about another structure, the same code | symbol is attached | subjected about the same member and the description is abbreviate | omitted.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
30 and 31 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention in the order of steps. The manufacturing method of the present embodiment first undergoes the same steps as those of the first embodiment shown in FIGS. Thereafter, referring to FIG. 30, p-type base region 41 is formed on a part of first main surface of n ⁻ region 5 sandwiched by parallel grooves 9 using a method such as ion implantation and diffusion. The The p-type base region 41 has an impurity concentration of 1 × 10 ¹⁴ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less, is shallower than the trench 9, and deeper than an n ⁺ cathode region 7 described later. For example, it is formed with a depth of 1.0 μm or more and 15.0 μm or less.

Referring to FIG. 31, n ⁺ cathode region 7 is formed on the first main surface sandwiched between grooves 9 running in parallel with each other by a method such as ion implantation and diffusion. The n ⁺ cathode region 7 is formed to have a peak concentration of 1 × 10 ¹⁸ cm ⁻³ or more and shallower than the p-type base region 41. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

  Next, a method for controlling the main current conduction state and the main current cutoff state of the semiconductor device of the present embodiment will be described.

The main current conduction state is realized by applying a positive voltage to the gate electrode layer 13 shown in FIG. When the gate electrode layer 13 applies a positive voltage, the gate electrode layer 13 and the facing portion of the p-type base region 41 is inverted channel is formed in the n ⁺ region, the electron current flows. Next, in response to this electron current, holes are injected into the n ⁻ semiconductor substrate 5 from the p ⁺ anode region 1 and conductivity modulation occurs. Further, this hole current enters the p base region 41. When this current increases, the potential of the p-type base region 41 rises, and when this potential becomes higher than the built-in potential, the diode formed from the p-type base region 41 and the n ⁺ cathode region 7 becomes conductive. As a result, current flows from the n ⁺ cathode region 7 through the p base region 41 and directly into the n ⁻ semiconductor substrate 5, so that the four-layer pnpn thyristor is turned on. The main current conduction state is established.

Note that the on-resistance (on-voltage) in the on-state greatly depends on the concentration of the p base region 41, but when the concentration is sufficiently lower than the number of stored carriers in the n ⁻ semiconductor substrate 5 in the on-state. As a result, a low on-state voltage almost the same as in the first to fourth embodiments having no p base region 41 can be obtained.

Next, the main current cut-off state is realized by applying a negative voltage to the gate electrode layer 13 shown in FIG. When a negative voltage is applied to the gate electrode layer 13, the n ⁺ channel formed in the on state disappears, and the supply of electrons from the n ⁺ cathode region 7 stops and simultaneously, the gate electrode layer 13 moves to the n ⁻ region 5. The depletion layer extends toward the main path, and the current path of the main current is reduced. As a result, the conduction current is reduced, and when the current is equal to or lower than the holding current, the diode formed by the p-type base region 41 and the n ⁻ region 5 is in the reverse bias state, and the main current is cut off.

  Since the main breakdown voltage is maintained by the p-type base region 41 after the main current is cut off, the present embodiment is characterized in that it is not necessary to apply a gate voltage to maintain the main current cut-off state. is there.

In the present embodiment, as shown in FIG. 29, gate electrode layer 13 faces n ⁻ region 5, p-type base region 41 and cathode region 7 with insulating layer 11 interposed therebetween. That is, the gate control method is a voltage control type. For this reason, the gate control circuit can be simplified as compared with the current control type as described in the first embodiment.

  A large-area cathode region 7 is formed on the first main surface sandwiched between the grooves 9. For this reason, the forward voltage drop Vf can be reduced as described in the first embodiment.

  In addition, the semiconductor device of this embodiment has a normally-off type structure in which it is not necessary to apply a gate voltage once the main current is cut off. For this reason, the gate control circuit can be simplified in this embodiment as compared with the structure in which the gate voltage needs to be continuously applied.

(Embodiment 6)
32 is a plan view schematically showing a configuration of the semiconductor device according to the sixth embodiment corresponding to claims 3 and 6 of the present invention, and FIG. 33 shows a state in which the cathode electrode 17 is formed in the state of FIG. FIG. FIG. 34 is a schematic sectional view taken along line FF ′ of FIG.

Referring to FIGS. 32 to 34, the semiconductor device of the present embodiment differs from that of the fifth embodiment in that p ⁺ isolation impurity region 23 is provided. The p ⁺ isolation impurity region 23 is formed so as to surround the planar region of the diode formation region and to be in contact with the groove 9. The p ⁺ isolation impurity region 23 is formed deeper than the trench 9.

  Since other configurations are the same as those in the fifth embodiment, the same members are denoted by the same reference numerals, and the description thereof is omitted.

The manufacturing method of this p ⁺ isolation impurity region 23 is substantially the same as the steps described with reference to FIGS.

When a negative voltage is applied to the gate electrode layer 13, the potential of the p ⁺ isolation impurity region 23 is fixed by an inversion layer formed around the gate electrode layer 13. As a result, the pn junction formed by p ⁺ isolation impurity region 23 and n ⁻ region 5 is in a reverse bias state. Thereby, the main withstand voltage holding ability to the element can be enhanced.

  According to the semiconductor device of the present embodiment, as shown in FIGS. 33 and 34, p-type impurity region 23 is formed deeper than trench 9 so as to surround the diode formation region. For this reason, the other elements and the diode can be electrically separated and the main breakdown voltage holding capability of the elements can be increased.

(Embodiment 7)
FIG. 35 is a plan view schematically showing a configuration of the semiconductor device according to the seventh embodiment corresponding to claim 4 of the present invention, and FIG. 36 shows a state in which the cathode electrode 17 is formed in the state of FIG. It is a top view. FIG. 37 is a schematic sectional view taken along the line GG ′ of FIG.

35 to 37, the semiconductor device of the present embodiment differs from that of the fifth embodiment in that p ⁺ contact region 31 is provided. The p ⁺ contact region 31 is provided so as to be adjacent to the cathode region 7 via the groove 9b or 9d, and is electrically connected to the cathode electrode 17. The p ⁺ contact region 31 has an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or more. The p ⁺ contact regions 31 and the n ⁺ cathode regions 7 are alternately arranged with a groove interposed therebetween. Further, the number of the grooves 9a, 9b,.

  In addition, since it is the same as that of Embodiment 5 about other structures, the same code | symbol is attached | subjected about the same member and the description is abbreviate | omitted.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
38 and 39 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the seventh embodiment of the present invention in the order of steps.

The manufacturing method of the present embodiment first undergoes the same steps as the manufacturing method of the first embodiment shown in FIGS. Thereafter, referring to FIG. 38, p ⁺ contact region 31 is formed on the surface of n ⁻ region 5 sandwiched between parallel grooves 9b and 9c by using a method such as a photoengraving process or ion implantation and diffusion. The

Referring to FIG. 39, p-type base region 41 and n ⁺ cathode are adjacent to p ⁺ contact region 31 through grooves 9b and 9c through the same steps as in FIG. 30 and FIG. 31 described above. Region 7 is formed. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

In the present embodiment, since the p ⁺ contact region 31 is formed adjacent to the n ⁺ cathode region 7 through the groove 9, the turn-off time can be shortened as described in the third embodiment. Is possible.

(Embodiment 8)
40 is a plan view schematically showing a configuration of the semiconductor device according to the eighth embodiment corresponding to claims 4 and 6 of the present invention. FIG. 41 shows a state in which the cathode electrode 17 is formed in the state of FIG. FIG. FIG. 42 is a schematic cross-sectional view taken along the line HH ′ of FIG.

40 to 42, the semiconductor device of the present embodiment is different from that of the seventh embodiment in that p ⁺ isolation impurity region 23 is provided. The p ⁺ isolation impurity region 23 is provided so as to surround the diode formation region in plan and to contact the groove 9. The p ⁺ isolation impurity region 23 is formed deeper than the trench 9.

  In addition, since it is the same as that of Embodiment 7 about the structure other than this, the same code | symbol is attached | subjected about the same member and the description is abbreviate | omitted.

The method for manufacturing p ⁺ isolation impurity region 23 in the semiconductor device of the present embodiment is the same as the process shown in FIGS.

When a negative voltage is applied to the gate electrode layer 13, the potential of the p ⁺ isolation impurity region 23 is fixed by an inversion layer formed around the gate electrode layer 13. As a result, the pn junction formed by p ⁺ isolation impurity region 23 and n ⁻ region 5 is in a reverse bias state. Thereby, the main withstand voltage holding ability to the element can be enhanced.

  According to the semiconductor device of the present embodiment, as shown in FIGS. 41 and 42, the p-type impurity region 23 is formed deeper than the trench 9 so as to surround the diode formation region. As a result, the other elements and the diode can be electrically separated and the main breakdown voltage holding capability of the element can be increased.

(Embodiment 9)
FIG. 43 is a plan view schematically showing a configuration of the semiconductor device according to the ninth embodiment corresponding to claim 5 of the present invention, and FIG. 44 shows a state in which the cathode electrode 17 is provided in the state of FIG. It is a top view. FIG. 45 is a schematic sectional view taken along the line II ′ of FIG.

43 to 45, this embodiment shows an example including a diode structure. This diode has a stacked structure of a p ⁺ collector region 1, an n-type buffer region 3, an n ⁻ region 5, and an n ⁺ cathode region 7. The groove 9 is provided so as to penetrate the n ⁺ cathode region 7 from the surface on the n ⁺ cathode region 7 side and reach the n ⁻ region 5. A p ⁺ contact region 62 is provided on the substrate surface so as to be in contact with the groove 9. Also beneath the p ⁺ contact region 62, n to be in contact with trench 9 and p ⁺ contact region 62 ^- have regions 61 are provided.

The p ⁺ contact region 62 has an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or more, and the n ⁻ region 61 has an n ^{+ of} 1 × 10 ¹² cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less, for example. The impurity concentration is lower than that of the cathode region 7.

  In addition, since it is the same as that of Embodiment 1 about another structure, the same code | symbol is attached | subjected about the same member and the description is abbreviate | omitted.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
46 to 49 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the ninth embodiment of the present invention in the order of steps.

Referring to FIG. 46, first, p ⁺ collector region 1, n-type buffer region 3 and n ⁻ region 5 are sequentially stacked. The surfaces of the regions 5, n ^{- -} The n low concentration epitaxial growth layer region 61 corresponds provided, then selectively performs ion implantation and diffusion, an island-shaped n ^- region 61 is left.

Referring to FIG. 47, n ⁺ cathode region 7 is formed in a region sandwiched between n ⁻ regions 61 by ion implantation and diffusion. The diffusion depth of the cathode region 7 is substantially the same as the diffusion depth of the n ⁻ region 61.

Referring to FIG. 48, p ⁺ contact region 62 is formed on the substrate surface above n ⁻ region 61 by ion implantation and diffusion. The p ⁺ contact region 62 is desirably formed shallower than the n ⁺ cathode region 7.

Referring to FIG. 49, trench 9a is formed from the substrate surface so as to penetrate p ⁺ contact region 62 and n ⁻ region 61 to reach n ⁻ region 5. Thereafter, the semiconductor device shown in FIG. 45 is completed through steps similar to those of the first embodiment.

Incidentally, n ^- region 61 the n ^- it is desirable to form a low impurity concentration than the region 5, n ^- n If region 5 has sufficiently low impurity concentration ^- region 61 the n ^- formed by leaving a region 5 You can also

Next, a method for controlling the semiconductor device of this embodiment will be described.
First, the main current conduction state is realized by applying a positive voltage to the gate electrode layer 13. At this time, an n-type accumulation region 65 having a high electron concentration is formed along the groove 9 as shown in FIG.

The main current cut-off state can be realized by applying a negative voltage to the gate electrode layer 13. When a negative voltage is applied to the gate electrode layer 13, the n ⁺ storage layer (channel), which is an electron current path, disappears, and the current path of the main current is depleted and cut off as in the first to eighth embodiments. At the same time, the n ⁻ regions 5 and 61 in contact with the trench 9 become p ⁺ inversion regions.

In order to shorten the turn-off time when the main current is cut off, it is necessary to quickly extract minority carriers (in this case, holes) remaining in the element at the time of interruption from the n ⁻ semiconductor substrate 5. In the present embodiment, holes which are minority carriers are extracted through the path of the p ⁺ inversion region and the p ⁺ contact region 62 generated around the groove 9. For this reason, as described in the second embodiment, the turn-off time can be shortened also in this embodiment.

Referring to FIG. 50, in the main current conduction state, n-type accumulation channel region 65 having a high electron density is generated around trench 9, and this n-type accumulation region 65 is an extension region of n ⁺ cathode region 7. It is regarded. That is, the n ⁺ cathode region 7 is regarded as expanded. As a result, the cathode area which is the contact area between the n ⁺ cathode region 7 and the n ⁻ region 5 increases. Therefore, the electron injection efficiency is increased, and the forward voltage drop Vf can be reduced.

(Embodiment 10)
51 is a plan view schematically showing a configuration of the semiconductor device according to the tenth embodiment corresponding to claims 5 and 6 of the present invention. FIG. 52 shows a state in which the cathode electrode 17 is formed in the state of FIG. FIG. FIG. 53 is a schematic sectional view taken along line JJ ′ of FIG.

51 to 53, the configuration of the semiconductor device of the present embodiment is different from that of the ninth embodiment in that p ⁺ isolation impurity region 23 is provided. The p ⁺ isolation impurity region 23 is provided so as to surround the diode formation region in a plane and in contact with the groove 9. The p ⁺ isolation impurity region 23 is formed deeper than the trench 9.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
FIG. 54 is a schematic cross sectional view showing the method for manufacturing the semiconductor device in the tenth embodiment of the present invention.

  The semiconductor device manufacturing method of the present embodiment first undergoes the same steps as those of the second embodiment shown in FIGS. Thereafter, the state shown in FIG. 54 is obtained through the steps shown in FIG. Thereafter, the semiconductor device shown in FIG. 53 is completed through steps similar to those of the first embodiment.

When a negative voltage is applied to the gate electrode layer 13, the potential of the p ⁺ isolation impurity region 23 is fixed by an inversion layer formed around the gate electrode layer 13. As a result, the pn junction formed by p ⁺ isolation impurity region 23 and n ⁻ region 5 is in a reverse bias state. Thereby, the main withstand voltage holding ability to the element can be enhanced.

  According to the semiconductor device of the present embodiment, as shown in FIGS. 52 and 53, the p-type impurity region 23 is formed deeper than the trench 9 so as to surround the diode formation region. For this reason, while isolating another element and a diode electrically, the main withstand voltage holding | maintenance capability of an element can be improved.

  In addition, the groove | channel 9 provided in each embodiment may be arrange | positioned concentrically as shown, for example in FIGS.

  55 corresponds to the second embodiment and the sixth embodiment, and the cross section taken along the line LL ′ of FIG. 55 is a schematic cross sectional view shown in FIG. 13 and FIG. Correspond.

  The plan structure shown in FIG. 56 corresponds to the fourth and eighth embodiments. A cross section taken along line MM ′ in FIG. 56 corresponds to the schematic cross sectional views shown in FIGS. The number of grooves 9 in FIGS. 26 and 42 can be arbitrarily selected.

  The plan structure shown in FIG. 57 corresponds to the tenth embodiment. A cross section taken along line NN ′ in FIG. 57 corresponds to the schematic cross sectional view shown in FIG.

(Embodiment 11)
FIG. 58 is a cross sectional view schematically showing a configuration of a semiconductor device according to the eleventh embodiment corresponding to claim 8 of the present invention. Referring to FIG. 58, the semiconductor device of the present embodiment shows an example of an IGBT. The structure of the semiconductor device in this embodiment is particularly different from the structure of the semiconductor device shown in FIG. That is, the groove 113 in this embodiment is formed deeper than the groove 413 shown in FIG. The depth T ₁₁ of the groove 113 is 5 to 15 μm, and the width W ₁₁ is 0.8 to 3.0 μm. The pitch P ₁₁ between the grooves 113 is, for example, 4 μm.

In the case of an element having a breakdown voltage of several hundred V as the first conductivity type semiconductor substrate, an n-type low impurity concentration epitaxial growth substrate of several tens of Ωcm is used as the n ⁻ substrate (n ⁻ region) 105. In the case of several thousand V-class elements, an n ^- substrate 105 having an n-type low impurity concentration and a high specific resistance of 100 Ωcm or more, more specifically, an FZ (Floating Zone) method having a thickness of about 350 Ωcm and a thickness of about 600 μm. The manufactured silicon polycrystalline substrate is irradiated with a neutron beam and the resistivity is adjusted by heat treatment.

  The high resistance substrate is doped with n-type or p-type impurities for resistivity control. However, in the on-state of the bipolar device, electrons and holes, which are current carriers, are sufficiently accumulated in the high resistance layer and cause conductivity modulation. In some cases, an intrinsic semiconductor (intrinsic) semiconductor)).

In the present embodiment, thickness T ₁₀₁ of p ⁺ collector region 101 is, for example, 3 to 350 μm, thickness T ₁₀₃ of n ⁺ buffer region ₁₀₃ is, for example, 8 to 30 μm, and thickness T ₁₀₅ of n ⁻ region ₁₀₅ is For example, the thickness T ₁₀₇ of the p-type base region 107 is 2.0 to 3.5 μm, for example, and the thickness T ₁₀₉ of the n ⁺ emitter region ₁₀₉ is 0.5 to 1.5 μm, for example.

  The p-type base region 107 only needs to be formed shallower than the trench 113, and is specifically about 3 μm.

As for the impurity concentration of each part, the p ⁺ collector region 101 is 1 × 10 ¹⁶ cm ⁻³ or more and 5 × 10 ²¹ cm ⁻³ or less, and the n ⁺ buffer region 103 is 1 × 10 ¹³ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, n ⁻ region 105 is 1 × 10 ¹² cm ⁻³ or more and 1 × 10 ¹⁴ cm ⁻³ or less, and the p-type base region 107 has a peak concentration of 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less, p ⁺ contact region 111 is 1 × 10 ²⁰ cm ⁻³ or more on the substrate surface, and n ⁺ emitter region 109 is 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 on the substrate surface. ²⁰ cm ⁻³ or less.

  Since the configuration other than this is substantially the same as that of the third conventional example shown in FIG. 99, the same members are denoted by the same reference numerals, and the description thereof is omitted.

Next, a method for manufacturing a semiconductor device in the present embodiment will be described.
59 to 63 are schematic cross sectional views showing the method for manufacturing the semiconductor device in the eleventh embodiment of the present invention in the order of steps. First, referring to FIG. 59, p ⁺ collector region 101, n ⁺ buffer region 103, and n ⁻ region 105 are formed by being stacked. Thereafter, p-type base region 107 and n ⁺ emitter region 109 are formed on the surface of n ⁻ region 105.

Referring to FIG. 60, by anisotropically etching the substrate, trench 113 is formed which penetrates n ⁺ emitter region 109 and p-type base region 107 and whose bottom reaches n ⁻ region 105. The groove 113 is formed to have a width of 0.8 to 3.0 μm and a depth of 5.0 to 15.0 μm by controlling etching. Further, the depth of the groove is more preferably 10.0 μm or more.

  Referring to FIG. 61, a gate oxide film 115 made of a silicon oxide film is formed along the inner wall surface of trench 113 and covering the surface by, eg, thermal oxidation.

  Note that isotropic plasma etching is performed before the formation of the gate oxide film 115 and after the formation of the groove 113, and then a silicon oxide film is formed once on the inner wall surface of the groove 113 by sacrificial oxidation, thereby forming the MOS. The characteristics and the gate oxide film characteristics can be improved.

  Referring to FIG. 62, a doped polysilicon layer doped with an n-type impurity such as phosphorus is formed so as to fill trench 113. By anisotropic etching of this doped polysilicon layer, a gate electrode layer 117 is formed that fills the groove 113 and has an upper end protruding from the groove 113.

Referring to FIG. 63, p ⁺ contact region 111 for reducing contact resistance is formed in a partial region between trenches 113 by a method such as implantation and diffusion of p-type ions. The p ⁺ contact region 111 needs to have a concentration of 1 × 10 ²⁰ cm ⁻³ or more, and the depth thereof may be about the same as that of the n ⁺ emitter region 109. An interlayer insulating layer 119 made of a CVD oxide film such as BPSG is formed so as to cover the upper end of the gate electrode layer 117 protruding from the trench 113.

Thereafter, the cathode electrode 121 is formed to be electrically connected to the n ⁺ emitter region 109 and the p ⁺ contact region 111, and the anode electrode 123 is formed to be electrically connected to the p ⁺ collector region 101. The semiconductor device shown in FIG. 58 is completed.

  The on / off state control method by the gate electrode layer 117 in the semiconductor device of the present embodiment is substantially the same as the third conventional example shown in FIG.

  The inventors of the present application have found that the forward voltage drop Vf can be reduced as the ratio Rn increases from the result of FIG. 22 described above. In particular, it was also found that the forward voltage drop Vf is low and stable when the ratio Rn is 0.4 or more. It has also been found that the ratio Rn is more preferably 0.7 or more. Further, when the ratio Rn of the IGBT structure of the third conventional example (FIG. 99) was evaluated, it was found that the ratio Rn was smaller than 0.4 and the ability of supplying electrons from the cathode surface was very poor.

According to the semiconductor device of the present embodiment, groove 113 has a depth of 5 μm or more and is formed deeper than the third conventional example shown in FIG. 99, and thus occurs in the main current conduction state as shown in FIG. The n ⁺ accumulation region 425a is distributed more largely than the third conventional example. Therefore, the effective cathode region composed of the n ⁺ accumulation region 425a and the n ⁺ emitter region 109 is wider than the third conventional example, and a large effective cathode area can be secured. As described above, since the effective cathode area n shown in FIG. 22 is increased, the ratio Rn (= n / (n + p)) is increased. Specifically, the ratio Rn shown in FIG. 22 can be set to 0.4 or more, which was not obtained in the third conventional example shown in FIG. Therefore, since the ratio Rn can be made larger than that in the third conventional example, the forward voltage drop Vf can also be made lower than that in the third conventional example.

More precisely, the n ⁺ accumulation region 425a referred to here is an n-type channel inversion region formed in a portion where the p-type base region 107 is formed, and a groove protruding to the n ⁻ substrate region 105. This is a combination of both the n-type accumulation region formed in the periphery. Since the n-type channel inversion region and the n-type accumulation region are the same in the sense that both are n-type regions of high concentration and are electron supply sources when the gate positive bias is on, there is virtually no distinction between them. . Therefore, in FIG. 100, for simplicity, both are collectively shown as the n ⁺ accumulation region 425a as described above.

Here, the area p, which is an element of the ratio Rn, refers to the contact area between the p-type base region 107 and the n ⁻ region 105 as shown by a thick line in FIG.

A groove depth T ₁₁ of 10 μm or more is more preferable because the forward voltage drop Vf can be further reduced.

  Further, according to the semiconductor device of the present embodiment, the control method by the gate electrode layer 117 is a voltage control type. Therefore, as described above, in the semiconductor device according to the present embodiment, the gate control circuit can be simplified as compared with the first and second conventional examples, and the entire system can be reduced in size and simplified. It can save energy.

(Embodiment 12)
FIG. 64 is a cross sectional view schematically showing a configuration of a semiconductor device according to the twelfth embodiment corresponding to claim 10 of the present invention. Referring to FIG. 64, the structure of the semiconductor device in the present embodiment is different from the structure of the semiconductor device in Embodiment 11 in the structure of the region sandwiched between the trenches and the structure of the gate electrode layer.

In the region sandwiched between grooves 113a and 113b and the region sandwiched between grooves 113c and 113d, p-type base region 107, n ⁺ emitter region 109, and p ⁺ contact region 111 are formed as in the eleventh embodiment. Yes. In the region sandwiched between the trench 113b and the trench 113c, the p-type base region 107 or the like is not formed, and only the n ⁻ region 105 is located.

  The gate electrode layer 117 that fills the groove 113b and the gate electrode layer 117 that fills the groove 113c are integrally formed by a conductive portion 117a and are electrically connected. The conductive portion 117a is formed on a region sandwiched between the groove 113b and the groove 113c with an insulating film 129 interposed therebetween.

  Since the configuration other than this is substantially the same as that of the eleventh embodiment, the same member is denoted by the same reference numeral, and the description thereof is omitted.

Hereinafter, this structure is referred to as a MAE (MOS Accumulated Emitter) structure.
The configuration of the present embodiment has a line-symmetric structure with respect to both the RR ′ line and the SS ′ line shown in FIG. For this reason, the concept of taking the unit cell as a structure between the R—R ′ line and the S—S ′ line and the concept of taking the unit cell as a structure between the R—R ′ line and the next R—R ′ line. There are types. Here, for the convenience of calculating the ratio Rn, the former structure between the RR ′ line and the SS line is defined as a unit cell.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
65 to 68 are schematic cross sectional views showing the method for manufacturing the semiconductor device in the twelfth embodiment of the present invention in the order of steps. First, referring to FIG. 65, p ⁺ collector region 101, n-type buffer region 103, and n ⁻ region 105 are stacked. Thereafter, p type base region 107 and n ⁺ emitter region 109 are selectively formed on the surface of n ⁻ region 105.

Referring to FIG. 66, for example, grooves 113a to 113d are formed on the substrate surface serving as the first main surface by anisotropic dry etching used in a normal semiconductor process. Each groove is formed to have a width of 0.8 to 3.0 [mu] m and a depth of 5 to 15 [mu] m by etching control, as in the eleventh embodiment. The p-type base region 107 and the n ⁺ emitter region 109 are located in the region sandwiched between the grooves 113a and 113b and the region sandwiched between the grooves 113c and 113d, and the region sandwiched between the grooves 113b and 113c Each groove is formed so that only n ⁻ region 105 is located. In this state, the n ⁺ emitter region 109 is located along the sidewall of the trench.

  For example, a gate oxide film 115 made of a silicon oxide film is formed along the inner wall surfaces of the trenches 113a to 113d by a thermal oxidation method or the like so as to cover the surface.

  It should be noted that isotropic plasma etching is performed before the formation of the gate oxide film 115 and after the formation of each groove, and then a silicon oxide film is formed on the inner wall surface of each groove by sacrificial oxidation, thereby obtaining MOS characteristics and gate oxidation. The characteristics of the film 115 can be improved.

  Referring to FIG. 67, a doped polysilicon layer doped with an n-type impurity such as phosphorus is formed so as to fill each groove. The doped polysilicon layer is anisotropically etched to form the gate electrode layer 117 so that each groove is buried and the upper end protrudes from each groove. The gate electrode layer 117 embedded in the grooves 113b and 113c is formed integrally with the conductive portion 117a and is formed so as to be electrically connected. Conductive portion 117a is formed on the surface region sandwiched between grooves 113b and 113c with an insulating film interposed.

Thereafter, a p ⁺ contact region for reducing contact resistance by selective p-type impurity implantation and diffusion in a partial region between trenches 113a and 113b and a partial region between trenches 113c and 113d. 111 is formed.

  Referring to FIG. 68, an interlayer insulating layer 119 made of, for example, a CVD oxide film such as BPSG is formed so as to cover the upper end of gate electrode layer 117 protruding from each groove.

Thereafter, the cathode electrode 121 is formed to be electrically connected to the n ⁺ emitter region 109 and the p ⁺ contact region 111, and the anode electrode 123 is formed to be electrically connected to the p ⁺ collector region 101. The semiconductor device shown in FIG. 64 is completed.

  The on / off state control method by the gate electrode layer 117 according to the present embodiment is substantially the same as that of the third conventional example shown in FIG.

However, when a positive voltage is applied to gate electrode layer 117 in the main current conduction state, n ⁺ accumulation layer 125b is generated as shown in FIG.

In the semiconductor device of this embodiment, as shown in FIG. 64, the conductive portion 117a is electrically connected to the gate electrode layer 117 that fills the trenches 113b and 113c. For this reason, when a positive voltage is applied to the gate electrode layer 117 in the main current conduction state, a positive voltage is also applied to the conductive portion 117a. The conductive portion 117a is opposed to the n ⁻ region 105 sandwiched between the grooves 113b and 113c with the insulating film 129 interposed therebetween. Therefore, when a positive voltage is applied to the conductive layer 117a, an n ⁺ accumulation region 125b is also generated in the surface region sandwiched between the grooves 113b and 113c as shown in FIG. Thus, since the n ⁺ surface region 125b can also be generated in the surface region sandwiched between the grooves 113b and 113c, the effective cathode area in the unit cell is larger than that in the eleventh embodiment. Therefore, the electron injection efficiency on the cathode side is further improved, and the forward voltage drop Vf can be further reduced. As a result, the ratio Rn becomes 0.4 or more and approaches 1.

  Further, according to the semiconductor device of the present embodiment, the control method by the gate electrode layer 117 is a voltage control type. Therefore, as described above, in the semiconductor device according to the present embodiment, the gate control circuit can be simplified as compared with the first and second conventional examples, and the entire system can be reduced in size and simplified. Energy saving can be achieved.

  Since the depth of the groove 113 is 5 μm or more, as described in the eleventh embodiment, the forward voltage drop Vf can be made lower than that in the third conventional example.

(Embodiment 13)
FIG. 70 is a cross sectional view schematically showing a configuration of a semiconductor device according to the thirteenth embodiment corresponding to claim 11 of the present invention. Referring to FIG. 70, the semiconductor device according to the present embodiment is different from the structure of the twelfth embodiment in that it has a second p-type base region 131. The second p-type base region 131 is formed, for example, in a surface region sandwiched between the grooves 113b and 113c. The second p-type base region 131 is formed for every other region sandwiched between grooves, for example. The second p-type base region 131 has a lower impurity concentration than the p-type base region 107.

  Since the configuration other than this is substantially the same as that of the twelfth embodiment, the same member is denoted by the same reference numeral, and the description thereof is omitted.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
FIG. 71 is a process diagram showing the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention. Referring to FIG. 71, p ⁺ collector region 101, n ⁺ buffer region 103, and n ⁻ region 105 are stacked. A p-type base region 107, a second p-type base region 131, and an n ⁺ emitter region 109 are formed on the surface of the n ⁻ region 105 by ion implantation and diffusion, respectively. Here, the second p-type base region 131 is formed to have a lower impurity concentration than the p-type base region 107.

Thereafter, a trench reaching the n ⁻ region 105 through the p type base region 107, the n ⁺ emitter region 109, and the second p type base region 131 using photolithography and etching technology (RIE). 113a to 113d are formed. Each groove is formed to have a width of 0.8 to 3.0 μm and a depth of 5 to 15 μm.

  Thereafter, gate oxide film 115 made of a silicon oxide film is formed along the inner wall surface of each groove by, eg, thermal oxidation.

  It is to be noted that isotropic plasma etching is performed before the gate oxide film 115 is formed and after each groove is formed, and then a silicon oxide film is formed on the inner wall surface of each groove by sacrificial oxidation, so that the MOS characteristics and The characteristics of the gate oxide film 115 can be improved.

  Thereafter, steps similar to those in the embodiment 12 shown in FIGS. 67 and 68 are completed, whereby the semiconductor device shown in FIG. 70 is completed.

  The on / off state control method by the gate electrode 117 in the present embodiment is substantially the same as that described in the third conventional example, and thus the description thereof is omitted.

However, when a positive voltage is applied to gate electrode layer 117 in the main current conduction state, n ⁺ accumulation region 125c in a high electron density state is generated as shown in FIG. A thyristor operation occurs in the region sandwiched between the grooves 113b and 113c.

In the semiconductor device of the present embodiment, as in the twelfth embodiment, as shown in FIG. 72, an n ⁺ accumulation region 125c can also be generated in the surface region between grooves 113b and 113c. Therefore, as in the twelfth embodiment, the electron injection efficiency on the cathode side can be improved, and the forward voltage drop Vf of the diode can also be reduced. As a result, the ratio Rn becomes 0.4 or more and approaches 1.

  Further, since the second p-type base region 131 has a lower concentration than the p-type base region 107, a thyristor operation occurs in a region sandwiched between the grooves 113b and 113c. As a result, there is an advantage that the ON voltage is lowered when the rated current is applied.

Further, a negative voltage is applied to the gate electrode layer 117 when the main current is interrupted. For this reason, ap ⁺ inversion region is formed in a portion of the second p-type base region 131 along the side walls of the grooves 113b and 113c and a region of the substrate surface. For this reason, as described with reference to FIG. 23, holes serving as carriers are easily removed from the p ⁺ inversion region, and there is an advantage that the turn-off time and tail current are reduced. Since the tail current at turn-off can be reduced, the turn-off loss E _off can also be reduced.

  Further, according to the semiconductor device of the present embodiment, the control method by the gate electrode layer 117 is a voltage control type. Therefore, as described above, in the semiconductor device according to the present embodiment, the gate control circuit can be simplified as compared with the first and second conventional examples, and the entire system can be reduced in size and simplified. It can save energy.

According to the semiconductor device of the present embodiment, as in Embodiment 11, the depth of the groove 113 a to 113 d T ₁₃ is 5μm or more. For this reason, as described in the eleventh embodiment, the forward voltage drop Vf can be made lower than that in the third conventional example.

(Embodiment 14)
FIG. 73 is a cross sectional view schematically showing a configuration of the semiconductor device according to the fourteenth embodiment corresponding to claim 12 of the present invention. Referring to FIG. 73, the configuration of the semiconductor device in the present embodiment is different from the configuration in the eleventh embodiment in that p ⁻ base region 133 is provided. The p ⁻ base region 133 is located below the p-type base region 107 and is disposed along the side wall of the groove 113. The impurity concentration of the p ⁻ base region 133 is 1 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less.

  Since the configuration other than this is substantially the same as that of the eleventh embodiment, the same members are denoted by the same reference numerals, and the description thereof is omitted.

In the semiconductor device of the present embodiment, when a negative voltage is applied to gate electrode layer 117 at the time of main current interruption, a p ⁺ inversion layer is formed in a portion along trench 113 in p ⁻ base region 133. For this reason, when the device is turned off, the holes that are carriers can be drawn smoothly, and the switching characteristics can be improved.

In addition, when a positive voltage is applied to gate electrode layer 117 during conduction of the main current, an inverted n layer is formed in a portion along p ^- base region 133 along groove 113, so that the ratio Rn is maintained high. The

  Thus, the ratio Rn can be kept high and the switching characteristics can be improved.

  Further, according to the semiconductor device of the present embodiment, the control method by the gate electrode layer 117 is a voltage control type. Therefore, as described above, in the semiconductor device according to the present embodiment, the gate control circuit can be simplified as compared with the first and second conventional examples, and the entire system can be reduced in size and simplified. It can save energy.

  Further, according to the semiconductor device of the present embodiment, the depth of the groove 113 is 5 μm or more, as in the eleventh embodiment. Therefore, as in the eleventh embodiment, the forward voltage drop Vf can be made lower than that in the third conventional example.

(Embodiment 15)
74 is a cross sectional view schematically showing a configuration of the semiconductor device in the fifteenth embodiment corresponding to claims 8 and 17 of the present invention, and is a cross sectional view schematically showing a part of the configuration shown in FIG. is there.

With reference to FIG. 74, the present inventors have found that the ratio Rn can be approximated in the dimensions of the respective parts of the IGBT. The ratio Rn can be expressed by Rn = n / (n + p) as described in the third embodiment. This n is the area of the portion indicated by the thick line in FIG. 74 as described above. Specifically, the area n is an area where the n ⁺ accumulation region 125a is in contact with the n ⁻ region 105 and the p-type base region 107 and an area where the n ⁺ emitter region 109 is in contact with the p-type base region 107 in the main current conduction state. And the sum. On the other hand, p is a contact area between the p-type base region 107 and the n ⁻ region 105 as described above.

Here, the width of the n ⁺ accumulation region 125a is very small. Therefore, the width of the groove 113 is Wt, the depth of the groove 113 from the cathode surface (first main surface) is Dt, the depth of the n ⁺ emitter region from the cathode surface is De, and one of the n ⁺ emitter regions 109 is The width in the direction from the groove 113 toward the other groove 113 is We, the width in the direction from one groove 113 to the other groove 113 in the p-type base region 107 is Wp, and the depth from the cathode surface of the p-type base region 107 is Is Dp, n and p are given by the following equations.

  By substituting the above formula into the ratio Rn, the ratio Rn is given by the following formula.

  Here, if the pitch of the grooves 113 is Pt (FIG. 74),

Therefore, the ratio Rn is rewritten as the following equation.

  In calculating the areas n and p, it is correct to use a value obtained by multiplying the total length in the depth direction (= trench length L × the number of trenches) in FIG. However, in a structure in which striped trenches run side by side, the total length in the depth direction is equally applied to each term, so that this can be omitted and approximated by the above formula.

  In FIG. 74, for convenience of explanation, the bottom surface of the groove 113 has a planar shape. However, in the actual device, the bottom of the groove 113 is rounded as shown in FIG. 58 for the purpose of improving the gate breakdown voltage. It is normal. For this reason, in the calculation of the ratio Rn, the area Wt at the bottom of the trench takes a coefficient larger than 1, but it is omitted for the sake of simplicity.

More specifically, when forming a deep trench gate, if Pt = 5.5 μm, Dt = 15 μm, Wt = 1 μm, De = 1 μm, We = 0.8 μm,
Rn = [1+ (0.8 + 15-1) × 2] / [5.5+ (0.8 + 15-1) × 2] = 15.8 / 20.3 = 0.78
Thus, a large ratio Rn can be realized.

(Embodiment 16)
FIG. 75 is a cross sectional view schematically showing a configuration of a semiconductor device in the sixteenth embodiment corresponding to claims 8 and 17 of the present invention. Referring to FIG. 75, it is effective to increase the width Wt of the groove 113 even if the groove 113 is shallow (the depth Dt of the groove 113 is small) in order to increase the ratio Rn from the above formula of the ratio Rn. It is.

More specifically, if Pt = 9 μm, Dt = 5 μm, Wt = 6 μm, De = 1 μm, We = 0.8 μm,
Rn = [6+ (0.8 + 5 + 1) × 2] / [9+ (0.8 + 5 + 1) × 2] = 19.6 / 22.6 = 0.87
Thus, a large ratio Rn can be realized.

(Embodiment 17)
The configuration of the semiconductor device of the present embodiment is substantially the same as the configuration of the twelfth embodiment shown in FIG. This structure is more complex than the fifteenth embodiment described above and has the disadvantage that the number of variables to be optimized increases and the manufacturing process becomes complicated. However, a larger ratio Rn is easily obtained, and the structure is low. There is an advantage that it is effective for the on-voltage.

  The method for controlling the on / off state by the gate electrode layer 117 according to the present embodiment is substantially the same as that of the above-described twelfth embodiment, and a description thereof will be omitted.

In particular, when a positive voltage is applied to the gate electrode layer 117 in the main current conduction state, an n ⁺ accumulation region 125b is generated as shown in FIG.

Here, when the structure between the R—R ′ line and the S—S ′ line is a unit cell, the area n is:
n = 2Dt−De + We + Wn + Wt
It becomes.

As is apparent from this equation, in the semiconductor device of the present embodiment, an n ⁺ accumulation region 125b is also generated in the surface region sandwiched between the grooves 113b and 113c, as shown in FIG. For this reason, the effective cathode area in the unit cell is larger than that in the fifteenth embodiment. For this reason, the electron injection efficiency on the cathode side is further improved, and the forward voltage drop Vf can be further reduced. Further, the ratio Rn becomes 0.4 or more and approaches 1.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
76 to 85 are schematic cross-sectional views showing the method of manufacturing a semiconductor device in the seventeenth embodiment corresponding to claims 18 and 20 of the present invention in the order of steps. In particular, as a manufacturing method of the present embodiment, a case where an element having a breakdown voltage of 4500 V class is manufactured will be described as an example.

First, referring to FIG. 76, n ^- silicon substrate 105 having a high resistivity of about 200 to 400 Ωcm is formed by FZ method. On the anode side which is the second main surface of the n ⁻ silicon substrate 105, an n ⁺ buffer region 103 having a first conductivity type n-type high impurity concentration and a thickness of about 10 to 30 μm, and a second conductivity type p A p ⁺ collector region (p ⁺ anode region) 101 having a high impurity concentration and a thickness of about 3 to 10 μm is formed.

One method of manufacturing n ⁺ buffer region 103, after ion implantation of large phosphorus diffusion coefficient, performed 20-30 hours drive-in at a high temperature of 1,200-1,250 ° C., after the final step of the n ⁺ buffer region 103 It is formed so that the peak concentration is about 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ and the depth is about 20 to 30 μm. Further, a vapor phase deposition method using a gas obtained by bubbling PH ₃ gas or POCl ₃ may be used instead of phosphorus ion implantation.

Another manufacturing method of the n ⁺ buffer region 103 is to form a silicon crystal layer having an n-type impurity concentration comparable to that formed by ion implantation using epitaxial growth.

The manufacturing method of the p ⁺ collector region 101 includes a method of performing drive-in after ion implantation or vapor phase deposition similar to the manufacturing method of the n ⁺ buffer region 103, and a method of forming a p-type silicon crystal layer by epitaxial growth. There is. However, in this case, boron or gallium is used as the p-type impurity. Therefore, the source gas of the vapor deposition method is a gas obtained by sublimation of boron glass (B ₂ O ₃ or the like) generated by oxidation of B ₂ H ₆ gas or BN (Boron Nitride) which is a solid source. The p ⁺ collector region 101 is formed to have a depth of 3 to 10 μm and a peak concentration higher than that of the n ⁺ buffer region 103 after the final process.

Referring to FIG. 77, boron ions are selectively implanted into a region sandwiched between grooves (dotted lines in the figure) formed in a later step, using resist pattern 151 as a mask. As a result, the p-type base region 107 a of the second conductivity type is formed on the first main surface of the n ⁻ silicon substrate 105. When the grooves are formed in stripes with a short repetition interval (pitch) of about 3 to 5 μm, a long heat treatment for diffusion of the p-type base region 107a (for example, a relatively high temperature of 1100 ° C. to 1150 ° C. for 30 hours) It is necessary to prevent the p-type base region 107a from penetrating into the region where the IGBT structure is not formed. For this reason, it is necessary to implant boron ions with a p base implantation width wp (imp) having a dimension smaller than the groove repeat interval (Tr-pitch).

Referring to FIG. 78, a resist pattern 152 is formed on the first main surface by a normal photolithography technique. Using this resist pattern 152 as a mask, an n-type impurity such as phosphorus, arsenic or antimony is ion-implanted to form a first conductivity type n ⁺ emitter region 109a. Thereafter, resist pattern 152 is removed.

Referring to FIG. 79, a resist pattern 153 is formed on the first main surface by a normal photolithography technique. Using this resist pattern 153 as a mask, grooves 113a to 113d are formed in stripes at predetermined repetition intervals by RIE or other silicon anisotropic etching. Thereafter, a long heat treatment of about 30 minutes to 7 hours at a relatively high temperature of 1100 ° C. to 1150 ° C. is performed for the diffusion of the p-type base region 107 as described above. By this heat treatment, p-type base region 107a and n ⁺ emitter region 109a are diffused.

Conditions such as the temperature and time of the heat treatment are determined so that the p-type base region 107 can be formed sufficiently deeply in accordance with the main breakdown voltage required for the manufactured element. Specifically, in an element having a breakdown voltage of 4500 V class, a p-type base region 107 of about 2 μm or more is required below the n ⁺ emitter region 109. Therefore, the diffusion depth of the p-type base region 107 from the substrate surface is a depth obtained by adding about 2 μm or more to the diffusion depth of the n ⁺ emitter region 109. Therefore, heat treatment for a long time at a high temperature as described above is required.

  In order to avoid such a long-time heat treatment at a high temperature, there is a method of selectively implanting deep ions using high energy ion implantation in the ion implantation step shown in FIG. In this case, the resist pattern 151 used as a mask has a viscosity of about 300 to 500 cp, which is higher than a normal viscosity (several tens of cp (centipoise; unit of viscosity)). In addition, since the resist pattern 151 is formed to a thickness of several μm, ions implanted with a high energy of about 3 to 5 MeV can be shielded. The range of boron ions in silicon when ions are implanted with such high energy is about 2 to 4 μm. Therefore, the desired diffusion depth of the p-type base region 107a can be obtained with little heat treatment.

  If the heat treatment for diffusion of the p-type base region 107 is excessively performed, or if the hole pattern of the resist for selective implantation (diffusion) is too large, as shown in FIGS. The p-type base region 107 protrudes to a region where no structure is formed. In this case, the purpose of improving the element characteristics by increasing the ratio Rn cannot be achieved.

On the other hand, if the heat treatment for the diffusion of the p-type base region 107 is too small, or if the hole pattern of the resist for selective implantation (diffusion) is too small, as shown in FIGS. A portion where the n ⁺ emitter region 109 is not covered with the p-type base region 107 occurs, and the main breakdown voltage cannot be maintained.

  As shown in FIG. 80, sacrificial oxidation is performed in a state where the patterned film 154 is formed, so that the oxide film 115 is formed on the inner walls of the grooves 113a to 113d. Thereafter, wet etching is performed as shown in FIG. 81, and oxide film 115 is removed.

  Referring to FIG. 82, silicon oxide film 115 is formed on the inner walls and first main surface of grooves 113a-113d by thermal oxidation. This silicon oxide film 115 is formed in accordance with the gate breakdown voltage, gate input capacitance and gate threshold voltage required for the element.

  A conductive film 117c made of phosphorus-doped polycrystalline silicon is formed on the first main surface so as to fill these grooves 113a to 113d. The conductive film 117c has a film thickness equal to or larger than the opening width of the grooves 113a to 113d and is formed by an apparatus such as low pressure CVD. Thereafter, the entire surface of the conductive film 117c is etched (usually referred to as etch back) to a relatively thin film thickness that can be easily processed in a later process.

  Further thereafter, the conductive film 117c is selectively removed by a normal photoengraving technique and dry etching technique so as to leave a gathered portion by the surface wiring of the control electrode (gate).

  Referring to FIG. 83, by this selective removal, a control electrode layer (gate electrode layer) having a portion 117a filling trenches 113a-113d and extending through an insulating film 129 over a region where an IGBT structure is not formed. ) 117 is formed.

Referring to FIG. 84, the p ⁺ contact region 111 of the second conductivity type is adjacent to the n ⁺ emitter region 109 by combining a normal photolithography technique and an ion implantation technique of p-type impurities such as boron. It is formed on the first main surface to fit.

  Referring to FIG. 85, a CVD silicon oxide film such as BPSG or a silicon nitride film is formed as interlayer insulating film 119a so as to cover gate electrode layer 117. A contact hole or a line-shaped contact portion is formed in the interlayer insulating film 119a. Thereafter, metal wiring such as aluminum is formed on the first main surface by sputtering, and the semiconductor device shown in FIG. 64 is completed.

Note that the n ⁺ emitter region 109 may not be formed by the process shown in FIGS. 78 and 79 but may be formed after the control electrode layer 117 shown in FIG. 83 is formed. Also in the case where n ⁺ emitter region 109 after the gate electrode layer 117 shown in FIG. 83 is formed is formed, the n ⁺ emitter region 109 is formed after the p ⁺ contact region 111 shown in FIG. 84 has been formed May be.

  In addition, after the grooves 113a to 113d are formed in the process of FIG. 79, isotropic dry etching is performed as shown in, for example, Japanese Patent Application Nos. 6-012559 and 7-001347. May be.

  Specifically, after the grooves 113a to 113d are formed in the step of FIG. 79, isotropic etching is performed as shown in FIG. 90, the corners of the openings of the grooves 113a to 113d are dropped, and the bottom of each groove is formed. Is rounded. Thereafter, the deposition film formed at the time of etching is removed by wet etching. Thereafter, as shown in FIGS. 80 and 81, an oxide film 115 is formed on the inner walls of the grooves 113a to 113d by sacrificial oxidation, and the oxide film 115 is removed by wet etching.

  As a result, the inside of the grooves 113a to 113d and the shape of the opening are adjusted, and at the same time, the contaminated layer and damaged layer caused by the anisotropic etching are removed.

  Note that at least one of the sacrificial oxidation and the low damage isotropic dry etching shown in FIG. 80 may be performed.

  The semiconductor device of this embodiment has a more complicated manufacturing process than that of the fifteenth embodiment. However, it is not necessary to make the grooves 113a to 113d extremely deep or wide. For this reason, the processing time of the trench forming etching process itself and the trench embedding process itself by the CVD method of the doped polysilicon film can be shortened, and the burden on the manufacturing apparatus can be reduced. Therefore, the overall cost / performance is comparable to that of the fifteenth embodiment.

(Embodiment 18)
FIG. 91 is a cross sectional view schematically showing a configuration of a semiconductor device in Embodiment 18 of the present invention. Referring to FIG. 91, the configuration of the present embodiment is different in the configuration of gate electrode layer 117 as compared to the configurations of embodiments 12 and 17 shown in FIG. That is, the gate electrode layer 117 does not extend over a region where the IGBT structure is not formed (hereinafter referred to as an IGBT non-formation region). That is, the cathode electrode 121 is formed on the IGBT non-formation region with only the insulating layers (the insulating layer 129 and the interlayer insulating film 119) interposed.

  Since the configuration other than this is the same as in the twelfth and seventeenth embodiments, the same reference numeral is given to the same member, and the description thereof is omitted.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
FIG. 92 is a process diagram showing the method for manufacturing the semiconductor device in the eighteenth embodiment corresponding to claims 18 and 21 of the present invention. The manufacturing method of the present embodiment first undergoes the same steps as those of the seventeenth embodiment shown in FIGS. Thereafter, referring to FIG. 92, the gate electrode layer does not extend on the IGBT non-formation region and projects on the first main surface by using the normal photolithography technique and the dry etching technique. Patterned.

  Thereafter, the semiconductor device shown in FIG. 91 is completed through steps similar to those in the seventeenth embodiment.

  As described above, when the gate electrode layer 117 is not extended on the IGBT non-formation region, the simplicity of the manufacturing process is obtained when the gate electrode layer is extended on the IGBT formation region in the seventeenth embodiment. And almost the same.

In the semiconductor device according to the present embodiment, the gate electrode layer does not extend over the IGBT non-formation region as compared with the seventeenth embodiment. For this reason, in the ON state, the extended n ⁺ emitter region (storage region) is not formed on the first main surface of the IGBT non-formation region, and the ratio Rn value in the ON state becomes small. However, by reducing the pitch between the grooves sandwiching the IGBT non-formation region as compared with the pitch of the trench sandwiching the IGBT formation region, the proportion of the expanded n ⁺ emitter region (accumulation region) in the ratio Rn value is reduced. Therefore, it is possible to obtain a ratio Rn substantially the same as that in the seventeenth embodiment.

  In the portion where the gate electrode layer extends on the first main surface, the thickness of the interlayer insulating film 119 is reduced. For this reason, a breakdown voltage failure between the gate electrode layer 117 and the emitter electrode 121 is likely to occur, and the manufacturing yield deteriorates. From the viewpoint of the manufacturing yield, it is desirable that the portion where the gate electrode extends on the first main surface is small. Therefore, the semiconductor device of the present embodiment is industrially effective as compared with the configuration of the seventeenth embodiment.

(Embodiment 19)
FIG. 93 is a cross sectional view schematically showing a configuration of a semiconductor device according to the nineteenth embodiment corresponding to claims 13 and 17 of the present invention. Referring to FIG. 93, in the configuration of the present embodiment, a plurality of IGBT non-formation regions are formed in a region sandwiched between two IGBT formation regions as compared to the configurations of the twelfth and seventeenth embodiments shown in FIG. Is arranged.

  The structure of the present embodiment is a line-symmetric structure with respect to both the RR ′ line and the SS line in FIG. For this reason, the concept of taking the unit cell as the structure between the R—R ′ line and the S—S ′ line, and the concept of taking the structure between the R—R ′ line and the next R—R ′ line, There are two types. Here, the structure between the latter RR ′ line and the next RR ′ line is defined as a unit cell. Therefore, the number of IGBT non-forming regions sandwiched between two IGBT forming regions in the unit cell is three. In other words, four grooves sandwiching each IGBT non-formation region are arranged between the two IGBT formation regions.

The ratio Rn value approaches 1 as the number of IGBT non-formation regions sandwiched between two IGBTs increases. However, although the situation is somewhat different depending on the pitch between the grooves and the depth of the grooves, when the number of IGBT non-formation regions sandwiched between the two IGBT formation regions exceeds about 2 to 4, the ratio Rn value starts to saturate. Further, the n ⁺ emitter region (n ⁺ accumulation region) expanded in the ON state is formed only in the vicinity of the interface between the silicon substrate and the gate oxide film (in the range of about 100 mm). For this reason, if the expanded n ⁺ emitter region (storage region) becomes too long, the resistance of the storage region becomes too large to be ignored. Therefore, the number of IGBT non-formation regions sandwiched between two IGBT formation regions is preferably 4 or less. In other words, the number of grooves located between two IGBT formation regions is preferably 5 or less.

  The semiconductor device of the present embodiment can be manufactured by almost the same manufacturing method as that of the seventeenth embodiment.

(Embodiment 20)
FIG. 94 is a cross sectional view schematically showing a configuration of the semiconductor device according to the twentieth embodiment corresponding to claims 15 and 17 of the present invention. Referring to FIG. 94, the present embodiment is different from the nineteenth embodiment shown in FIG. 93 in the configuration of gate electrode layer 117. In the present embodiment, the gate electrode layer 117 does not extend over the IGBT non-formation region.

  Since other configurations are substantially the same as those in the nineteenth embodiment, the same members are denoted by the same reference numerals, and the description thereof is omitted.

  The semiconductor device of the present embodiment can be manufactured by almost the same manufacturing method as that of the eighteenth embodiment.

In the semiconductor device of the present embodiment, since the gate electrode layer 117 does not extend on the IGBT non-formation region, the ratio Rn value in the on state is small. However, the ratio of the expanded n ⁺ emitter region (n ⁺ accumulation region) indicated by the ratio Rn value is reduced by reducing the pitch of the groove that sandwiches the IGBT non-formation region compared to the pitch of the trench that sandwiches the IGBT formation region. Thus, the substantially same ratio Rn as in the nineteenth embodiment can be obtained.

  On the other hand, in the portion where gate electrode layer 117 extends on the first main surface, the thickness of interlayer insulating film 119 on the gate electrode layer is reduced. For this reason, as the number of portions where the gate electrode layer 117 extends on the first main surface increases, a breakdown voltage defect between the gate electrode layer 117 and the cathode electrode 121 is more likely to occur, and the manufacturing yield deteriorates. For this reason, from the viewpoint of manufacturing yield, the gate electrode layer 117 does not extend on the IGBT non-formation region, and the smaller the portion extending on the first main surface, the more desirable. It is industrially effective as compared with Form 19.

(Embodiment 21)
FIG. 95 is a cross sectional view schematically showing a configuration of a semiconductor device according to the twenty-first embodiment corresponding to claims 14 and 17 of the present invention. Referring to FIG. 95, the configuration of the present embodiment differs from that of the nineteenth embodiment shown in FIG. 93 in that p ⁺ diverter region 141 is provided on the first main surface. A plurality of IGBT non-forming regions are arranged between the p ⁺ diverter region 141 and the IGBT forming region.

The configuration of the present embodiment has a line-symmetric structure with respect to both the RR ′ line and the U-U ′ line in FIG. For this reason, the concept of taking the unit cell as a structure between the RR 'line and the U-U' line and the concept of taking the structure between the RR 'line and the next RR' line are two. There are types. Here, the structure between the latter RR ′ line and the next RR ′ line is defined as a unit cell. Therefore, for example, three IGBT non-formation regions are arranged in a region sandwiched between the p ⁺ diverter region 141 and the IGBT formation region. In other words, four grooves are arranged between the p ⁺ diverter region 141 and the IGBT formation region.

As in the nineteenth embodiment, the ratio Rn value approaches 1 as the number of IGBT non-formation regions sandwiched between the p ⁺ diverter region 141 and the IGBT formation region is increased. However, although the situation differs somewhat depending on the groove pitch and groove depth, the ratio Rn value is saturated when the number of IGBT non-forming regions sandwiched between the p ⁺ diverter region 141 and the IGBT forming region exceeds about 2 to 4. start.

Further, the n ⁺ emitter region (n ⁺ accumulation region) expanded in the ON state is formed only in the very vicinity (in the range of about 100 mm) of the interface between the silicon substrate 105 and the gate oxide film 115 as the n ⁻ region. For this reason, if the expanded n ⁺ emitter region (n ⁺ storage region) becomes too long, the resistance of the storage region also becomes so large that it cannot be ignored. Therefore, the practical number of IGBT non-formation regions sandwiched between the p ⁺ diverter region 141 and the IGBT formation region is 4 or less. In other words, the number of grooves sandwiched between the p ⁺ diverter region 141 and the IGBT formation region is 5 or less.

In the semiconductor device of the present embodiment, p ⁺ diverter region 141 is provided to assist the turn-off function when the number of grooves sandwiched between IGBT formation regions is large and the number of IGBT non-formation regions is large. . The p ⁺ diverter region 141 has a function of commutating a part of the main current at turn-off from the IGBT structure portion. This will be described in more detail below.

Normally, in the IGBT turn-off, as described above, after the n-channel disappears in the negative gate bias state, the hole current finally flows out from the p ⁺ contact region 111 as the collector current of the pnp transistor. At this time, when the n ⁺ emitter region is greatly expanded by the MAE structure, the proportion of the p ⁺ contact region 111 included in the IGBT structure on the cathode side in the unit cell becomes small. For this reason, holes are concentrated in the p ⁺ collector region 111 at the time of turn-off. Therefore, holes cannot be removed from the p ⁺ collector region 111, and the turn-off time becomes long.

The p ⁺ diverter region 141 is provided for the purpose of increasing the proportion of the p-type region in the unit cell. In other words, by providing the p ⁺ diverter region 141, from p ⁺ diverter region 141 not only p ⁺ collector region 111 at turn-off, the hole current comes out as a collector current of the pnp transistor. As a result, the problem that holes are concentrated in the p ⁺ collector region 111 and the turn-off time becomes long is solved.

Further, the p ⁺ diverter region 141 also has a function of reducing current deviation in off-state. Therefore, it is more effective to form the p ⁺ diverter region 141 in a portion that is relatively far away from the IGBT formation region.

(Embodiment 22)
FIG. 96 is a cross sectional view schematically showing a configuration of a semiconductor device according to the twenty-second embodiment corresponding to claims 16 and 17 of the present invention. Referring to FIG. 96, the configuration of the present embodiment is different from the configuration of the twenty-first embodiment shown in FIG. 95 in that gate electrode layer 117 does not extend on the IGBT non-formation region.

  Since the configuration other than this is substantially the same as the configuration of the twenty-first embodiment, the same members are denoted by the same reference numerals and the description thereof is omitted.

In the semiconductor device according to the present embodiment, the gate electrode layer 117 does not extend over the IGBT non-formation region as compared with the twenty-first embodiment, so that the n ⁺ emitter region (n ⁺ accumulation region) expanded in the on state ) And the ratio Rn value in the ON state becomes small. However, the proportion of the expanded n ⁺ emitter region (n ⁺ accumulation region) in the ratio Rn value is reduced by reducing the pitch of the groove that sandwiches the IGBT non-formed region compared to the pitch of the groove that sandwiches the IGBT forming region. A ratio Rn substantially equal to that in the twenty-first embodiment can be obtained.

  On the other hand, in the portion where the gate electrode layer 117 extends on the first main surface, the thickness of the interlayer insulating film 119 is reduced. Therefore, the gate electrode layer 117 extends on the IGBT non-formation region, and if the ratio of the gate electrode layer 117 extending on the first main surface is large, the breakdown voltage between the gate electrode layer 117 and the emitter electrode 121 is increased. Defects are likely to occur, and the manufacturing yield deteriorates. Therefore, from the viewpoint of manufacturing yield, it is desirable that the portion of the gate electrode layer 117 covering the first main surface is as small as possible. Therefore, the configuration of this embodiment is more industrial than the configuration of Embodiment 21. It is effective for.

In Embodiments 11 to 22 described above, as described with reference to FIGS. 22 and 23, if the ratio of the n ⁺ emitter region 109 is increased, the ratio Rn increases. The directional voltage drop Vf can be reduced. On the other hand, if the ratio of the p ⁺ contact region 111 is increased, the tail current at the time of turn-off can be reduced, so that the turn-off loss E _off can be reduced.

In Embodiments 11 to 22 above, the width of the n ⁺ emitter region 109 and the width of the p ⁺ contact region 111 are formed to be substantially the same, but according to the requirements for the forward voltage drop Vf and the turn-off loss E _off . Thus, the widths of the n ⁺ emitter region 109 and the p ⁺ contact region 111 can be changed.

In addition, the n ⁺ emitter regions 109 and the p ⁺ contact regions 111 of the embodiments 11 to 22 are alternately arranged in a straight line, but are arranged concentrically as described with reference to FIGS. It may be. If the p ⁺ contact region 111 is appropriately arranged on a concentric circle, minority carriers can be extracted with good uniformity, and a faster and more stable turn-off can be achieved.

  In all the above embodiments, the p-type and n-type conductivity types may be opposite to each other.

  In all the above embodiments, the n-type buffer regions 3 and 103 are shown as examples. However, the n-type buffer regions 3 and 103 may not be formed depending on the rating of the element and the performance of possession. Good. Further, by changing the thickness and impurity concentration of the n-type buffer regions 3 and 103, necessary main breakdown voltage, on-voltage, switching characteristics, etc. of each element can be obtained.

In each embodiment, the entire surface of the p ⁺ collector regions 1 and 101 is in contact with the anode electrodes 19 and 123. However, the semiconductor substrate 5 or a part of the n ⁻ region 105 is partly connected to the anode electrodes 19 and 123. An n-type high concentration region may be electrically connected for the purpose of short-circuiting part of 123. Further, by connecting the n-type region to the anode electrodes 19 and 123, it becomes possible to change the electrical characteristics of each diode.

  Moreover, although the cross-sectional shape of the bottom part of the groove | channel 9 is flat in Embodiment 1-10, as shown in Embodiment 11-14, the cross-sectional shape of the bottom part of the groove | channel 9 may be rounded. Conversely, the cross-sectional shape of the bottom of the grooves 113 and the like shown in the embodiments 11 to 22 may be flat as shown in the embodiments 1 to 10.

  In the first to tenth embodiments, similarly to the first to eleventh embodiments, by setting the depth of the groove 9 to 5 μm or more and 15 μm or less, it is possible to obtain a semiconductor device having a more excellent forward voltage drop Vf.

  Further, in each embodiment, it is preferable that the depth of the grooves 9 and 113 is 10 μm or more because the forward voltage drop Vf can be further reduced.

  Although common to all the above-described embodiments, the gate electrode layers 13 and 117 are electrically connected in a region not shown.

  In each embodiment, the gate electrode layers 13 and 117 are formed so as to protrude upward from the first main surface (cathode surface) of the semiconductor substrate. For this reason, the controllability of etching for forming the gate electrode layer is easy, and a stable operation of the element can be obtained. This will be described in detail below.

  In the element structure shown in FIGS. 101 to 103, the gate electrode layer 507 is embedded in the groove 505. In this case, the gate electrode layer 507 is obtained by once forming a conductive layer on the entire first main surface of the semiconductor substrate so as to fill the groove 505, and then etching the entire conductive layer. However, when the etching amount is too large, the gate electrode layer 507 does not face part or all of the n-type turn-off channel layer 508. In such a case, even when a voltage is applied to the gate electrode layer 507, no channel is generated in the n-type turn-off channel layer 508, and the device does not operate.

  On the other hand, in each embodiment of the present invention, the gate electrode layers 13 and 117 need only be formed so as to protrude above the first main surface of the semiconductor substrate, so that the etching control is easy. In this case, since the gate electrode layers 13 and 117 are always completely filled in the trenches, the operation is not unstable because no channel is generated.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a plan view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. It is a schematic plan view which shows a mode that the cathode electrode was provided in FIG. It is a schematic sectional drawing in alignment with the AA 'line of FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the main current conduction state of the semiconductor device in Embodiment 1 of this invention. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 2 of this invention. It is a schematic plan view which shows a mode that the cathode electrode was provided in FIG. It is a schematic sectional drawing in alignment with the BB 'line of FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 3 of this invention. It is a schematic plan view which shows a mode that the cathode electrode was provided in FIG. It is a schematic sectional drawing in alignment with the CC 'line of FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a graph which shows the relationship between the forward voltage drop Vf and ratio Rn. It is a graph which shows the relationship between the electric current I which flows in a device, and time. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 4 of this invention. It is a schematic plan view which shows a mode that the cathode electrode was provided in FIG. It is a schematic sectional drawing in alignment with the DD 'line of FIG. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 5 of this invention. It is a schematic plan view which shows a mode that the cathode electrode was provided in FIG. It is a schematic sectional drawing which follows the EE 'line of FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 5 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 5 of this invention. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 6 of this invention. It is a schematic plan view which shows a mode that the cathode electrode was provided in FIG. It is a schematic sectional drawing in alignment with the FF 'line of FIG. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 7 of this invention. FIG. 36 is a schematic plan view showing a state in which a cathode electrode is provided in FIG. It is a schematic sectional drawing in alignment with the GG 'line | wire of FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 7 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 7 of this invention. It is a top view which shows schematically the structure of the semiconductor device in Embodiment 8 of this invention. It is a schematic plan view which shows a mode that the cathode electrode was provided in FIG. It is a schematic sectional drawing in alignment with the HH 'line of FIG. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 9 of this invention. It is a schematic plan view which shows a mode that the cathode electrode was provided in FIG. It is a schematic sectional drawing in alignment with the II 'line of FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 9 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 9 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 9 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 9 of this invention. It is a schematic sectional drawing which shows the mode of the main electric current conduction state of the semiconductor device in Embodiment 9 of this invention. It is a top view which shows schematically the structure of the semiconductor device in Embodiment 10 of this invention. It is a schematic plan view which shows a mode that the cathode electrode was provided in FIG. It is a schematic sectional drawing in alignment with the JJ 'line of FIG. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 10 of this invention. It is a schematic plan view which shows a mode that the groove | channel was arrange | positioned concentrically. It is a schematic plan view which shows a mode that the groove | channel was arrange | positioned concentrically. It is a schematic plan view which shows a mode that the groove | channel was arrange | positioned concentrically. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 11 of this invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 11 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 11 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 11 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 11 of this invention. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 11 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 12 of this invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 12 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 12 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 12 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 12 of this invention. It is a schematic sectional drawing which shows the main current conduction state of the semiconductor device in Embodiment 12 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 13 of this invention. It is process drawing of the manufacturing method of the semiconductor device in Embodiment 13 of this invention. It is a schematic sectional drawing which shows the mode of the main electric current conduction state of the semiconductor device in Embodiment 13 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 14 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 15 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 16 of this invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 17 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 17 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 17 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 17 of this invention. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 17 of this invention. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the semiconductor device in Embodiment 17 of this invention. It is a schematic sectional drawing which shows the 7th process of the manufacturing method of the semiconductor device in Embodiment 17 of this invention. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the semiconductor device in Embodiment 17 of this invention. It is a schematic sectional drawing which shows the 9th process of the manufacturing method of the semiconductor device in Embodiment 17 of this invention. It is a schematic sectional drawing which shows the 10th process of the manufacturing method of the semiconductor device in Embodiment 17 of this invention. FIG. 10 is a first process diagram when a p-type base region protrudes. FIG. 10 is a second process diagram when the p-type base region protrudes. FIG. 10 is a first process diagram when the p-type base region is small. FIG. 10 is a second process diagram when the p-type base region is small. It is process drawing which shows a mode that isotropic dry etching was performed after groove | channel formation. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 18 of this invention. It is process drawing which shows the manufacturing method of the semiconductor device in Embodiment 18 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 19 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 20 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 21 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 22 of this invention. It is a schematic sectional drawing which shows roughly the structure of the semiconductor device in a 1st prior art example. It is sectional drawing which shows schematically the structure of the semiconductor device in a 2nd prior art example. It is sectional drawing which shows roughly the structure of the semiconductor device in a 3rd prior art example. It is a schematic sectional drawing which shows a mode that the n ^<+> storage layer in the 3rd prior art example was produced. It is a top view which shows roughly the structure of the semiconductor device in a 4th prior art example. It is a schematic sectional drawing in alignment with the PP line of FIG. It is a schematic sectional drawing in alignment with the QQ 'line of FIG.

Explanation of symbols

1,101 p ⁺ collector region, 3,103 n-type buffer region, 5,105 n ⁻ region, 7,109 cathode region (n ⁺ emitter region), 9, 9a to 9d, 113, 113a to 113d groove, 11 insulation Film, 13,117 Gate electrode layer, 15 Insulating film, 17, 121 Cathode electrode, 19, 123 Anode electrode, 23 p ⁺ isolation impurity region, 31 p ⁺ contact region, 41 p-type base region, 61 n ⁻ region, 62 p ⁺ contact region.

Claims (19)

A semiconductor device including a pnpn structure in which a main current flows between both main surfaces across a genuine or first conductivity type semiconductor substrate,
A first impurity region of a first conductivity type formed on a first main surface of the semiconductor substrate;
A second impurity region of a second conductivity type formed on the second main surface of the semiconductor substrate;
A third impurity region of a second conductivity type formed under the first impurity region and sandwiching the region of the semiconductor substrate with the second impurity region;
The semiconductor substrate has a plurality of grooves running in parallel on the first main surface, and each of the grooves penetrates the first and third impurity regions from the first main surface. Formed to reach the area,
The plurality of grooves have first and second grooves,
The first impurity region is formed on the entire surface of the first main surface of the semiconductor substrate sandwiched between the first groove and the second groove, and
A control electrode layer formed so as to face the first and third impurity regions and the region of the semiconductor substrate with an insulating film interposed in the trench;
A first electrode layer formed on the first main surface of the semiconductor substrate and electrically connected to the first impurity region;
A semiconductor device comprising: a second electrode layer formed on the second main surface of the semiconductor substrate and electrically connected to the second impurity region. The plurality of grooves include the first groove, the second groove, and the third groove that run parallel to each other,
A fourth impurity region of a second conductivity type is formed on the first main surface of the semiconductor substrate sandwiched between the second groove and the third groove;
2. The semiconductor device according to claim 1, wherein the fourth impurity region is formed shallower than the trench and is electrically connected to the first electrode layer. A semiconductor device including a diode structure in which a main current flows between both main surfaces across a genuine or first conductivity type semiconductor substrate,
A first impurity region of a first conductivity type formed on the first main surface of the semiconductor substrate and having an impurity concentration higher than the concentration of the semiconductor substrate;
A second impurity region of a second conductivity type formed on the second main surface of the semiconductor substrate,
The semiconductor substrate has a parallel running groove formed in the first main surface so as to sandwich the first impurity region, and
A third impurity region of a second conductivity type formed on the first main surface so as to be adjacent to the first impurity region on the side wall of the groove;
First conductivity lower in concentration than the first impurity region, which is provided immediately below the third impurity region so as to be in contact with the side wall of the trench and the region of the semiconductor substrate and adjacent to the first impurity region. A fourth impurity region of the mold;
A control electrode layer formed so as to face the third and fourth impurity regions and the region of the semiconductor substrate with an insulating film interposed in the trench;
A first electrode layer formed on the first main surface of the semiconductor substrate and electrically connected to the first and third impurity regions;
A semiconductor device comprising: a second electrode layer formed on the second main surface of the semiconductor substrate and electrically connected to the second impurity region. An isolation impurity region formed on the first main surface of the semiconductor substrate;
Among the plurality of grooves, the other groove is disposed on one side of the grooves disposed in the outermost row,
The isolation impurity region is disposed on the other side of the groove disposed in the outermost row,
4. The semiconductor device according to claim 1, wherein the isolation impurity region is formed in contact with the groove arranged in the outermost row and deeper than the groove. 5.   The semiconductor device according to claim 1, wherein a depth of the groove from the first main surface is not less than 5 μm and not more than 15 μm. A semiconductor device in which a current flows between both main surfaces of a genuine or first conductivity type semiconductor substrate,
A first impurity region of a second conductivity type formed on the first main surface side of the semiconductor substrate;
A second impurity region of a second conductivity type formed on a second main surface of the semiconductor substrate and sandwiching a low concentration region of the semiconductor substrate with the first impurity region;
The semiconductor substrate has a groove reaching the low concentration region of the semiconductor substrate through the first impurity region from the first main surface,
A third impurity region of a first conductivity type formed on the first impurity region and in contact with a sidewall of the groove on the first main surface of the semiconductor substrate;
A fourth impurity having a second conductivity type higher in concentration than the first impurity region, formed on the first impurity region and adjacent to the third impurity region on the first main surface of the semiconductor substrate. Area,
The first and second impurity regions and the low-concentration region of the semiconductor substrate are opposed to the first and third impurity regions and the low-concentration region of the semiconductor substrate with a first insulating film interposed in the trench. A control electrode layer for controlling the current flowing between the main surfaces;
A first electrode layer formed on the first main surface of the semiconductor substrate and electrically connected to the third and fourth impurity regions;
A second electrode layer formed on the second main surface of the semiconductor substrate and electrically connected to the second impurity region;
When the first and second main surfaces of the semiconductor substrate are in a conductive state, a first conductivity type accumulation region is formed in contact with the third impurity region and along the periphery of the groove;
The effective cathode region including the third impurity region and the accumulation region is in contact with the first impurity region and the low concentration region of the semiconductor substrate, and the first impurity region is the low concentration region of the semiconductor substrate. The ratio Rn = (n / n + p) to the area p in contact with the semiconductor device is 0.4 or more and 1.0 or less in the conductive state.   The depth of the said groove | channel from the said 1st main surface is a semiconductor device of Claim 6 which is 5 micrometers or more and 15 micrometers or less. A plurality of the grooves are formed so as to have first, second and third grooves,
The first, third and fourth impurity regions are formed in the semiconductor substrate sandwiched between the first and second grooves,
Only the low-concentration region of the semiconductor substrate is located on the first main surface of the semiconductor substrate sandwiched between the second and third grooves,
On the semiconductor substrate sandwiched between the second and third grooves, a conductive layer is formed with a second insulating film interposed therebetween,
The semiconductor device according to claim 6, wherein the conductive layer is electrically connected to each of the control electrode layers embedded in the second and third grooves. A plurality of the grooves are formed so as to have first, second and third grooves,
The first, third and fourth impurity regions are formed in the semiconductor substrate sandwiched between the first and second grooves,
A fifth impurity region of a second conductivity type is formed on the first main surface of the semiconductor substrate sandwiched between the second and third grooves,
On the semiconductor substrate sandwiched between the second and third grooves, a conductive layer is formed with a second insulating film interposed therebetween,
The semiconductor device according to claim 6, wherein the conductive layer is electrically connected to each of the control electrode layers embedded in the second and third grooves.   The lower portion of the first impurity region is formed so as to be in contact with the sidewall of the groove and sandwich the low concentration region of the semiconductor substrate with the second impurity region, and has a lower concentration than the first impurity region. The semiconductor device according to claim 6, further comprising a fifth impurity region of the second conductivity type having the following characteristics. A plurality of the grooves are formed so as to have first, second, third and fourth grooves,
The first and second grooves are arranged adjacent to each other, and the first, third, and fourth impurity regions are formed in the region of the semiconductor substrate sandwiched between the first and second grooves. The first area,
The third and fourth grooves are arranged adjacent to each other, and the region of the semiconductor substrate sandwiched between the third and fourth grooves is formed on the first main surface with the low concentration of the semiconductor substrate. Only the area is the second area,
A plurality of the second regions are disposed between the two first regions,
In the plurality of second regions sandwiched between the first regions, a conductive layer is formed on the first main surface with a second insulating film interposed therebetween,
The semiconductor device according to claim 6, wherein the conductive layer is electrically connected to each of the control electrode layers embedded in the third and fourth grooves sandwiching each of the second regions. A plurality of the grooves are formed to have first, second, third, fourth, fifth and sixth grooves,
The first and second trenches are disposed adjacent to each other, and the first, third, and fourth impurity regions are formed in a region of the semiconductor substrate that is sandwiched between the first and second trenches. The first area,
The third and fourth grooves are arranged adjacent to each other, and the region of the semiconductor substrate sandwiched between the third and fourth grooves is formed on the first main surface with the low concentration of the semiconductor substrate. Only the area is the second area,
The fifth and sixth grooves are arranged so as to be adjacent to each other, and the region of the semiconductor substrate sandwiched between the fifth and sixth grooves is the second conductivity type fifth on the first main surface. A third region in which an impurity region is formed;
A plurality of the second regions are disposed between the first region and the third region,
The first electrode layer is electrically connected to the fifth impurity region,
In the plurality of second regions sandwiched between the first region and the third region, a conductive layer is formed on the first main surface with a second insulating film interposed. ,
The semiconductor device according to claim 6, wherein the conductive layer is electrically connected to each of the control electrode layers embedded in the third and fourth grooves sandwiching each of the second regions. A plurality of the grooves are formed so as to have first, second, third and fourth grooves,
The first and second grooves are arranged adjacent to each other, and the first, third, and fourth impurity regions are formed in the region of the semiconductor substrate sandwiched between the first and second grooves. The first area,
The third and fourth grooves are arranged adjacent to each other, and the region of the semiconductor substrate sandwiched between the third and fourth grooves is formed on the first main surface with the low concentration of the semiconductor substrate. Only the area is the second area,
A plurality of the second regions are disposed between the two first regions,
In the plurality of second regions sandwiched between the first regions, the first electrode layer is formed on the first main surface with only the second insulating film interposed therebetween,
The semiconductor device according to claim 6, wherein the control electrode layer protrudes upward from the first main surface. A plurality of the grooves are formed to have first, second, third, fourth, fifth and sixth grooves,
The first and second grooves are arranged adjacent to each other, and the first, third, and fourth impurity regions are formed in the region of the semiconductor substrate sandwiched between the first and second grooves. The first area,
The third and fourth grooves are arranged adjacent to each other, and the region of the semiconductor substrate sandwiched between the third and fourth grooves is formed on the first main surface with the low concentration of the semiconductor substrate. Only the area is the second area,
The fifth and sixth grooves are arranged so as to be adjacent to each other, and the region of the semiconductor substrate sandwiched between the fifth and sixth grooves is the second conductivity type fifth on the first main surface. A third region in which an impurity region is formed;
A plurality of the second regions are disposed between the first region and the third region,
The first electrode layer is electrically connected to the fifth impurity region,
In the plurality of second regions sandwiched between the first region and the third region, the first electrode layer is provided with only a second insulating film interposed on the first main surface. Is formed,
The semiconductor device according to claim 6, wherein the control electrode layer protrudes upward from the first main surface. A semiconductor device in which a current flows between both main surfaces of a genuine or first conductivity type semiconductor substrate,
A first impurity region of a second conductivity type formed on the first main surface side of the semiconductor substrate;
A second impurity region of a second conductivity type formed on a second main surface of the semiconductor substrate and sandwiching a low concentration region of the semiconductor substrate with the first impurity region;
The semiconductor substrate has a groove reaching the low concentration region of the semiconductor substrate through the first impurity region from the first main surface,
A third impurity region of a first conductivity type formed on the first impurity region and in contact with a sidewall of the groove on the first main surface of the semiconductor substrate;
A fourth impurity having a second conductivity type higher in concentration than the first impurity region, formed on the first impurity region and adjacent to the third impurity region on the first main surface of the semiconductor substrate. Area,
The first and second impurity regions and the low-concentration region of the semiconductor substrate are opposed to the first and third impurity regions and the low-concentration region of the semiconductor substrate with a first insulating film interposed in the trench. A control electrode layer for controlling the current flowing between the main surfaces;
A first electrode layer formed on the first main surface of the semiconductor substrate and electrically connected to the third and fourth impurity regions;
A second electrode layer formed on the second main surface of the semiconductor substrate and electrically connected to the second impurity region;
The depth of the groove from the first main surface is Dt, the width of the groove is Wt, the depth of the third impurity region from the first main surface is De, and one of the grooves in the third impurity region When the width in the direction from the groove to the other groove is We and the pitch between the adjacent grooves is Pt,

The semiconductor device characterized by satisfy | filling. A method of manufacturing a semiconductor device in which a current flows between both main surfaces of a genuine or first conductivity type semiconductor substrate,
Forming a second conductivity type first impurity region by selectively implanting ions into the first main surface of the first conductivity type semiconductor substrate;
Forming a second impurity region of a second conductivity type on the second main surface of the semiconductor substrate;
Forming a third impurity region of the first conductivity type on the first main surface in the first impurity region by selectively implanting ions;
Forming a plurality of grooves having first, second and third grooves in the semiconductor substrate by performing anisotropic etching on the first main surface,
First and third impurity regions are formed on the first main surface sandwiched between the first and second grooves, and the first main surface sandwiched between the second and third grooves is formed on the first main surface. Only the low concentration region of the semiconductor substrate is located;
A control electrode layer is formed in the trench so as to face the low concentration region of the semiconductor substrate and the first and third impurity regions sandwiched between the first and second impurity regions with a first insulating film interposed therebetween. Forming a step;
By selectively implanting ions, a fourth impurity of a second conductivity type having an impurity concentration higher than that of the first impurity region on the first main surface in the first impurity region so as to be adjacent to the third impurity region. Forming a region;
Forming a first electrode layer on the first main surface so as to be electrically connected to the first and fourth impurity regions;
Forming a second electrode layer on the second main surface so as to be electrically connected to the second impurity region.   The method of manufacturing a semiconductor device according to claim 16, further comprising a step of forming an oxide film by oxidizing an inner wall of the groove after the formation of the groove, and removing the oxide film. The step of forming the control electrode layer includes
Forming a conductive film on the first main surface so as to fill the groove;
By patterning the conductive film, the conductive film in the groove is left, the conductive film on the first main surface sandwiched between the first and second grooves is removed, and the first The method of manufacturing a semiconductor device according to claim 16, further comprising a step of leaving the conductive film on the first main surface sandwiched between the second and third grooves with a second insulating film interposed therebetween. The step of forming the control electrode layer includes
Forming a conductive film on the first main surface so as to fill the groove;
By patterning the conductive film, the conductivity between the first main surface sandwiched between the first and second grooves and the first main surface sandwiched between the second and third grooves. 17. The method of manufacturing a semiconductor device according to claim 16, further comprising: forming a control electrode layer that fills the groove and removes the film and protrudes upward from the first main surface.

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