CN113643968A - Insulated gate bipolar transistor and manufacturing method thereof - Google Patents

Insulated gate bipolar transistor and manufacturing method thereof Download PDF

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Publication number
CN113643968A
CN113643968A CN202010346503.XA CN202010346503A CN113643968A CN 113643968 A CN113643968 A CN 113643968A CN 202010346503 A CN202010346503 A CN 202010346503A CN 113643968 A CN113643968 A CN 113643968A
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bipolar transistor
insulated gate
gate bipolar
manufacturing
trench
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Inventor
钟圣荣
钟子期
周东飞
孙永生
董志意
刘欢
孟宪博
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Shanghai Beiling Co Ltd
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Shanghai Beiling Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

The invention discloses an insulated gate bipolar transistor and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: etching the plurality of substrate units to form a plurality of grooves, wherein the plurality of grooves comprise a first groove and a second groove, the first groove is used for forming a groove gate of a first insulated gate bipolar transistor, the first insulated gate bipolar transistor is an insulated gate bipolar transistor manufactured and formed on the first substrate unit, the second groove is used for forming a groove gate of a second insulated gate bipolar transistor, and the second insulated gate bipolar transistor is an insulated gate bipolar transistor manufactured and formed on the second substrate unit; the extending direction of the first groove is orthogonal to the extending direction of the second groove; and manufacturing and forming a trench gate. The invention is beneficial to releasing the stress in the horizontal direction and the vertical direction and reducing the problem of wafer warping caused by etching of the deep groove.

Description

Insulated gate bipolar transistor and manufacturing method thereof
Technical Field
The invention belongs to the technical field of insulated gate bipolar transistors, and particularly relates to an insulated gate bipolar transistor and a manufacturing method thereof.
Background
The IGBT (insulated gate bipolar transistor) integrates MOS (metal-oxide semiconductor) gate control and BJT (bipolar junction transistor) conductance modulation current, has the characteristics of high input impedance, small switching loss, high speed, low voltage driving power and the like, and is widely applied to occasions of high voltage, high current, high power and medium and high frequency. The conduction voltage drop determines the conduction loss of the device during operation, limits the maximum output power of the device, and in order to improve the performance of the IGBT as much as possible, the conduction voltage drop needs to be continuously reduced, which is mainly determined by factors such as a cell structure, a cell size, an arrangement layout, a substrate thickness and the like. The IGBT device turn-on equivalent resistance mainly comprises a front MOS resistor RC, a JFET (junction field effect transistor) area resistor RJ, a drift region resistor RD and a substrate PN junction resistor RP.
For the IGBT, the device turn-on voltage drop is reduced mainly by reducing the front MOS resistance RJ and the drift region resistance RD resistance.
For the drift region resistance RD, it is mainly achieved by reducing the drift region thickness. So far, three structures of a punch-through type PT-IGBT, a non-punch-through type NPT-IGBT and a field stop type FS-IGBT are mainly available, and the main difference among the three structures is different substrate PN junction structures and different drift region thicknesses. Compared with a PT-IGBT and an NPT-IGBT, the FS-IGBT has the thinnest thickness, the forward conduction voltage drop of the FS-IGBT is obviously reduced, and the structure is widely applied to IGBT products. However, as the size of semiconductor wafers increases, the process complexity and high chipping rate severely limit the performance of IGBTs.
For the resistor RJ, there are currently three main types of methods: firstly, a groove gate is adopted to replace a planar gate structure, a JFET (junction field effect transistor) area in the planar gate is removed, and the current density of a device is effectively increased; secondly, on the basis of a common trench gate structure, Mitsubishi company proposes a new structure called CSTBT (carrier stored trench gate bipolar transistor) which is provided with an N-type carrier storage layer below Pbody (P-type body region) to improve the front carrier concentration, but the introduction of the N-type carrier storage layer will cause the reduction of the breakdown voltage; and thirdly, the cell size is continuously reduced, the method can improve the cell density and reduce the conduction voltage drop, however, the wafer is easy to warp along with the reduction of the size of the trench gate, and the high fragmentation rate is caused.
Fig. 1-5 show some steps in the prior art for manufacturing an IGBT. Referring to fig. 1, impurity ions are implanted into a semiconductor wafer in a direction indicated by an arrow to form an N-type heavily doped layer 201 as an N-type carrier storage layer. Fig. 1 shows only a part of the semiconductor wafer in the longitudinal direction, and therefore the broken line is used for illustration. Then, according to fig. 2, the semiconductor wafer is etched to form a first trench 202 and a second trench 203. In the manufacturing process, a plurality of trenches are etched on a semiconductor wafer to simultaneously manufacture a plurality of IGBTs. Referring to fig. 3, as an illustration, the trenches formed by etching include a first trench 202, a second trench 203, a third trench 301, and a fourth trench 302. The grooves are often arranged in parallel, and due to stress, the wafer is prone to warping, resulting in a high chipping rate.
After the trenches are formed, referring to fig. 4, a first trench gate 204 is formed in the first trench 202, and a second trench gate 221 is formed in the second trench 203. Then, the other structure of the IGBT is fabricated to finally form the structure of the IGBT shown in fig. 5. Wherein, N + represents an N type heavily doped region, N represents an N type doped region, P + represents a P type heavily doped region, P represents a P type doped region, E represents an emitter, and C represents a collector.
In the manufacturing process, the N-type heavily doped layer 201 is formed as an N-type carrier storage layer, which can increase the front carrier concentration, however, the introduction of the N-type carrier storage layer will cause the breakdown voltage to decrease.
Disclosure of Invention
The invention provides an insulated gate bipolar transistor and a manufacturing method thereof, aiming at overcoming the defect that a wafer is easy to warp in the manufacturing process of the insulated gate bipolar transistor in the prior art.
The invention solves the technical problems through the following technical scheme:
the invention provides a manufacturing method of an insulated gate bipolar transistor, wherein a wafer is provided with a plurality of substrate units, the substrate units are used for manufacturing at least one insulated gate bipolar transistor, and the insulated gate bipolar transistor comprises a trench gate; the plurality of substrate units comprise a first substrate unit and a second substrate unit;
the manufacturing method comprises the following steps:
etching the plurality of substrate units to form a plurality of grooves, wherein the plurality of grooves comprise a first groove and a second groove, the first groove is used for forming a groove gate of a first insulated gate bipolar transistor, the first insulated gate bipolar transistor is an insulated gate bipolar transistor manufactured and formed on the first substrate unit, the second groove is used for forming a groove gate of a second insulated gate bipolar transistor, and the second insulated gate bipolar transistor is an insulated gate bipolar transistor manufactured and formed on the second substrate unit; the extending direction of the first groove is orthogonal to the extending direction of the second groove;
and manufacturing and forming a trench gate.
Preferably, the plurality of substrate units are arranged in a matrix.
Preferably, the first substrate unit is adjacent to the second substrate unit.
Preferably, one substrate unit is used for manufacturing a plurality of insulated gates, and the extending directions of a plurality of trench gates are parallel to each other.
Preferably, after the step of etching the plurality of substrate units to form the plurality of trenches, the manufacturing method further comprises the steps of:
a carrier storage region is formed in the substrate unit, the carrier storage region extending from a sidewall of the trench to an inside of the substrate unit by a predetermined distance.
Preferably, the bottom of the carrier storage region is not higher than the bottom surface of the trench.
Preferably, the preset distance is smaller than half of the first distance, the first distance is a distance between two sidewalls, and the two sidewalls are adjacent sidewalls respectively belonging to the two trenches.
Preferably, after the step of forming the carrier storage region, the manufacturing method further includes the steps of:
and etching the bottom of the groove to enable the groove to reach a preset depth.
Preferably, the step of forming the trench gate comprises:
and manufacturing and forming a trench gate in the trench.
The invention also provides an insulated gate bipolar transistor which is manufactured and formed according to the manufacturing method of the insulated gate bipolar transistor.
The positive progress effects of the invention are as follows: the invention adopts the orthogonal arrangement mode of the groove gate, is beneficial to releasing the stress in the horizontal direction and the vertical direction and reduces the problem of wafer warping caused by etching the deep groove.
Drawings
Fig. 1 is a schematic diagram of a carrier storage layer formed in a process of manufacturing an insulated gate bipolar transistor in the prior art.
Fig. 2 is a schematic diagram of a trench formed in the prior art process of manufacturing an insulated gate bipolar transistor.
Fig. 3 is a schematic diagram of the layout of trenches on a wafer in the prior art process of manufacturing insulated gate bipolar transistors.
Fig. 4 is a schematic diagram of a trench gate formed in a process of manufacturing an insulated gate bipolar transistor in the prior art.
Fig. 5 is a schematic structural diagram of an insulated gate bipolar transistor in the prior art.
Fig. 6 is a schematic diagram illustrating the layout of trenches on a wafer according to the method for manufacturing an insulated gate bipolar transistor in embodiment 1.
Fig. 7 is a flowchart of a method of manufacturing an insulated gate bipolar transistor according to embodiment 1.
Fig. 8 is a schematic structural view of an insulated gate bipolar transistor manufactured and formed by the method for manufacturing an insulated gate bipolar transistor according to embodiment 1.
Fig. 9 is a flowchart of a method of manufacturing an insulated gate bipolar transistor according to embodiment 2.
Fig. 10 is a schematic diagram of a substrate unit after step S502 is performed in the method for manufacturing an insulated gate bipolar transistor according to embodiment 2.
Fig. 11 is a schematic diagram of the substrate unit after step S503 is performed in the method for manufacturing an insulated gate bipolar transistor according to embodiment 2.
Fig. 12 is a schematic view of the substrate unit after step S504 is performed in the method of manufacturing an insulated gate bipolar transistor according to embodiment 2.
Fig. 13 is a schematic structural view of an insulated gate bipolar transistor manufactured and formed by the method for manufacturing an insulated gate bipolar transistor according to embodiment 2.
Fig. 14 is a schematic view of the layout of trenches on a wafer in the method for manufacturing an insulated gate bipolar transistor according to embodiment 3.
Fig. 15 is a schematic view of the layout of trenches on a wafer in the method of manufacturing an insulated gate bipolar transistor according to embodiment 4.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
The invention provides a manufacturing method of an insulated gate bipolar transistor. Referring to fig. 6, a plurality of substrate units are disposed on a wafer, and the boundaries of the substrate units are indicated by dashed lines for convenience of illustration. The substrate unit is used for manufacturing at least one insulated gate bipolar transistor, and the insulated gate bipolar transistor comprises a groove gate. As an illustration, referring to fig. 6, the plurality of substrate units includes a first substrate unit 401 and a second substrate unit 402.
Referring to fig. 7, the method of manufacturing the insulated gate bipolar transistor includes the steps of:
step S101, field oxygen is prepared, and a P-type ring (Ring) is prepared.
And S102, preparing a current carrier storage layer.
And step S103, etching the substrate units to form grooves. Referring to fig. 6, the plurality of trenches includes a first trench 403 and a second trench 404. The first trench 403 is used to form a trench gate of a first insulated gate bipolar transistor, which is manufactured and formed in the first substrate unit 401, the second trench 404 is used to form a trench gate of a second insulated gate bipolar transistor, which is manufactured and formed in the second substrate unit 402. The extending direction of the first trench 403 is orthogonal to the extending direction of the second trench 404.
And step S104, manufacturing and forming a trench gate.
Step S105, preparing a P-type body region, carrying out N-type source/drain doping to prepare NSD, and carrying out P-type source/drain doping to prepare PSD.
Then, the front side metallization is performed, and the back side process is performed, so that the insulated gate bipolar transistor structure shown in fig. 8 can be formed. Wherein 405 represents a carrier storage layer, 406 represents a trench gate, 407 represents a P-type body region, 408 represents an NSD, 409 represents a PSD, N + represents an N-type heavily doped region, N represents an N-type doped region, P + represents a P-type heavily doped region, P represents a P-type doped region, E represents an emitter, C represents a collector, a field oxide and the specific position of a P-type ring are clear to those skilled in the art and are not shown in the figure.
As an alternative embodiment, several substrate units are arranged in a matrix. Specifically, referring to fig. 6, the trench gate formed in any one substrate unit is arranged orthogonally to the trench gate formed in the substrate unit adjacent to the substrate unit.
As an alternative embodiment, several substrate units are arranged in a matrix.
In an alternative embodiment, a substrate unit is used to manufacture several insulated gates, and the extension directions of several trench gates are parallel to each other. Referring to fig. 6, the second substrate unit 402 includes a second trench 404 and a third trench 415, the second trench 404 is used for manufacturing one insulated gate, the third trench 415 is used for manufacturing one insulated gate, and the extending directions of the second trench 404 and the third trench 415 are parallel, that is, the extending directions of two insulated gates manufactured and formed in the second substrate unit 402 are parallel.
In an alternative embodiment, in any two adjacent substrate units, the extending direction of the trench in one substrate unit is orthogonal to the extending direction of the trench in the other substrate unit.
Compared with the manufacturing method in the prior art in which all trench gates on a wafer are distributed in parallel, the manufacturing method of the insulated gate bipolar transistor in the embodiment has the advantages that the trench gates are distributed orthogonally, so that stress in the horizontal direction and the vertical direction can be released, and wafer warping caused by deep trench etching can be reduced.
The present embodiment also provides an insulated gate bipolar transistor manufactured according to the method of manufacturing an insulated gate bipolar transistor of the present embodiment. The specific structure of the insulated gate bipolar transistor is shown in fig. 8, and will not be described herein.
Example 2
The invention provides a manufacturing method of an insulated gate bipolar transistor. Referring to fig. 6, a plurality of substrate units are disposed on a wafer, and the boundaries of the substrate units are indicated by dashed lines for convenience of illustration. The substrate unit is used for manufacturing at least one insulated gate bipolar transistor, and the insulated gate bipolar transistor comprises a groove gate. As an illustration, referring to fig. 6, the plurality of substrate units includes a first substrate unit 401 and a second substrate unit 402.
Referring to fig. 9, the method of manufacturing the insulated gate bipolar transistor includes the steps of:
in step S501, a field oxide is prepared, and a P-type ring (Ring) is prepared.
Step S502, etching the substrate units to form grooves. Referring to fig. 6, the plurality of trenches includes a first trench 403 and a second trench 404. The first trench 403 is used to form a trench gate of a first insulated gate bipolar transistor, which is manufactured and formed in the first substrate unit 401, the second trench 404 is used to form a trench gate of a second insulated gate bipolar transistor, which is manufactured and formed in the second substrate unit 402. The extending direction of the first trench 403 is orthogonal to the extending direction of the second trench 404.
Effect of forming the trench referring to fig. 10, the third trench 415 is a trench belonging to the second substrate unit 402 together with the second trench 404.
Step S503, forming a carrier storage region in the substrate unit. The carrier storage region extends from a sidewall of the trench to an inside of the substrate unit by a predetermined distance. Referring to fig. 11, the first carrier storage region 416 is a carrier storage region formed extending from the first sidewall 418, and the first sidewall 418 is one sidewall of the second trench 404; the second carrier storage region 417 is a carrier storage region formed extending from the second sidewall 419, and the second sidewall 419 is one sidewall of the third trench 415. The first sidewall 418 and the second sidewall 419 are two adjacent sidewalls belonging to the second trench 404 and the third trench 415, respectively. First carrier storage region 416 extends into the substrate cell from first sidewall 418 a distance D, and the distance between first sidewall 418 and second sidewall 419 is D1, D being less than half of D1, i.e., first carrier storage region 416 is not contiguous with second carrier storage region 417.
The step of forming the carrier storage region may be performed by means of angled injection.
As an alternative embodiment, the bottom of the carrier storage region is slightly below the bottom surface of the trench.
In an alternative embodiment, during the ion implantation to form the carrier storage region, the implanted impurity ions diffuse to the bottom of the trench (i.e., the substrate region below the bottom surface of the trench), so the carrier storage region includes a partial region extending from the bottom surface of the trench toward the back surface of the substrate unit.
Step S504, etching the bottom of the groove to enable the groove to reach a preset depth. Referring to fig. 12, after the etching, the depth of the trench is increased to form a deepened second trench 424 and a deepened third trench 425, and bottoms of the deepened second trench 424 and the deepened third trench 425 are lower than that of the carrier storage region.
And step S505, manufacturing and forming a trench gate.
Step S506, preparing a P-type body region, carrying out N-type source/drain doping to prepare NSD, and carrying out P-type source/drain doping to prepare PSD.
Then, the front side metallization is performed, and the back side process is performed, so that the insulated gate bipolar transistor structure shown in fig. 13 can be formed. Wherein 405 represents a carrier storage layer, 406 represents a trench gate, 407 represents a P-type body region, 408 represents an NSD, 409 represents a PSD, N + represents an N-type heavily doped region, N represents an N-type doped region, P + represents a P-type heavily doped region, P represents a P-type doped region, E represents an emitter, C represents a collector, a field oxide and the specific position of a P-type ring are clear to those skilled in the art and are not shown in the figure.
Because the carrier storage regions are adopted and are not connected, the manufacturing method of the insulated gate bipolar transistor optimizes the distribution of carriers when the insulated gate bipolar transistor is in forward conduction on the basis of not reducing the breakdown voltage of the device, and reduces the conduction voltage drop Vce (on) so as to reduce the conduction loss of the device.
The present embodiment also provides an insulated gate bipolar transistor manufactured according to the method of manufacturing an insulated gate bipolar transistor of the present embodiment. The specific structure of the insulated gate bipolar transistor is shown in fig. 13, and will not be described herein.
Example 3
This embodiment provides a method for manufacturing an insulated gate bipolar transistor based on embodiment 1 or embodiment 2. The steps of the method for manufacturing an insulated gate bipolar transistor are the same as those of the method for manufacturing an insulated gate bipolar transistor of embodiment 1 or embodiment 2, except that the number of trenches included in each substrate unit on the wafer is different. Referring to fig. 14, a substrate unit includes 3 trenches, each of which is used to form a trench gate. The 3 trenches in one substrate unit are arranged in parallel, that is, the extending directions of the 3 insulated gates fabricated and formed in one substrate unit are parallel.
Example 4
This embodiment provides a method for manufacturing an insulated gate bipolar transistor based on embodiment 1 or embodiment 2. The steps of the method for manufacturing an insulated gate bipolar transistor are the same as those of the method for manufacturing an insulated gate bipolar transistor of embodiment 1 or embodiment 2, except that the number of trenches included in each substrate unit on the wafer is different. Referring to fig. 15, a substrate unit includes 4 trenches, each of which is used to form a trench gate. The 4 trenches in one substrate unit are arranged in parallel, i.e. the extension directions of the 4 insulated gates fabricated and formed in one substrate unit are parallel.
In other alternative embodiments, the number of the grooves included in each substrate unit on the wafer may be set as required. The number of trenches included in different substrate units may be different.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (10)

1. The manufacturing method of the insulated gate bipolar transistor is characterized in that a plurality of substrate units are arranged on a wafer, the substrate units are used for manufacturing at least one insulated gate bipolar transistor, and the insulated gate bipolar transistor comprises a trench gate; the plurality of substrate units comprise a first substrate unit and a second substrate unit;
the manufacturing method comprises the following steps:
etching the substrate units to form grooves, wherein the grooves comprise a first groove and a second groove, the first groove is used for forming the groove gate of a first insulated gate bipolar transistor, the first insulated gate bipolar transistor is the insulated gate bipolar transistor manufactured and formed on the first substrate unit, the second groove is used for forming the groove gate of a second insulated gate bipolar transistor, and the second insulated gate bipolar transistor is the insulated gate bipolar transistor manufactured and formed on the second substrate unit; the extending direction of the first groove is orthogonal to the extending direction of the second groove;
and manufacturing and forming the trench gate.
2. The method of manufacturing an insulated gate bipolar transistor according to claim 1, wherein a plurality of the substrate units are arranged in a matrix form.
3. The method of manufacturing an insulated gate bipolar transistor according to claim 1, wherein the first substrate unit is adjacent to the second substrate unit.
4. The method of manufacturing an insulated gate bipolar transistor according to claim 1, wherein one substrate unit is used for manufacturing a plurality of the insulated gates, and the extending directions of a plurality of the trench gates are parallel to each other.
5. The method of manufacturing an insulated gate bipolar transistor according to claim 1, wherein after the step of etching a number of the substrate units to form a number of trenches, the method of manufacturing further comprises the steps of:
and forming a carrier storage region in the substrate unit, wherein the carrier storage region extends from the side wall of the groove to the inner part of the substrate unit by a preset distance.
6. The method of manufacturing an insulated gate bipolar transistor according to claim 5, wherein a bottom of the carrier storage region is not higher than a bottom surface of the trench.
7. The method according to claim 5, wherein the predetermined distance is less than half of a first distance between two of the sidewalls, the two sidewalls being adjacent sidewalls respectively belonging to the two trenches.
8. The manufacturing method of an insulated gate bipolar transistor according to claim 5, wherein after the step of forming a carrier storage region, the manufacturing method further comprises the steps of:
and etching the bottom of the groove to enable the groove to reach a preset depth.
9. The method of manufacturing an insulated gate bipolar transistor according to claim 8, wherein the step of manufacturing to form the trench gate comprises:
and manufacturing and forming the trench gate in the trench.
10. An insulated gate bipolar transistor, characterized in that the insulated gate bipolar transistor is manufactured according to the method for manufacturing an insulated gate bipolar transistor according to any one of claims 1 to 9.
CN202010346503.XA 2020-04-27 2020-04-27 Insulated gate bipolar transistor and manufacturing method thereof Pending CN113643968A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023193339A1 (en) * 2022-04-08 2023-10-12 苏州东微半导体股份有限公司 Method for manufacturing igbt device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023193339A1 (en) * 2022-04-08 2023-10-12 苏州东微半导体股份有限公司 Method for manufacturing igbt device

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