CN112652536B - Preparation method of low-conduction voltage drop planar gate IGBT - Google Patents
Preparation method of low-conduction voltage drop planar gate IGBT Download PDFInfo
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- 238000002347 injection Methods 0.000 claims description 28
- 239000007924 injection Substances 0.000 claims description 28
- 238000000206 photolithography Methods 0.000 claims description 9
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- 230000004888 barrier function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
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- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
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- H10D12/031—Manufacture or treatment of IGBTs
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Abstract
本发明属于功率半导体器件设计技术领域，具体涉及一种低导通压降平面栅IGBT的制备方法，该方法依次制备了N型增强层、P型体区、N+区、介质层、发射极、P型集电区和集电极，制备出P型体区的底部和侧面为N型增强层的N‑P‑N结构，且P型体区底部和侧面的N型增强层不相连。本发明制备的低导通压降平面栅IGBT具有击穿电压高，反向传输电容低和导通压降较低的优点。
The invention belongs to the technical field of power semiconductor device design, and specifically relates to a method for preparing a low conduction voltage drop planar gate IGBT. The method sequentially prepares an N-type enhancement layer, a P-type body region, an N+ region, a dielectric layer, an emitter, The P-type collector region and collector electrode prepare an N-P-N structure in which the bottom and sides of the P-type body region are N-type enhancement layers, and the N-type enhancement layers at the bottom and sides of the P-type body region are not connected. The low conduction voltage drop planar gate IGBT prepared by the invention has the advantages of high breakdown voltage, low reverse transmission capacitance and low conduction voltage drop.
Description
技术领域Technical field
本发明属于功率半导体器件设计技术领域，具体涉及一种低导通压降平面栅IGBT的制备方法。The invention belongs to the technical field of power semiconductor device design, and specifically relates to a preparation method of a low conduction voltage drop planar gate IGBT.
背景技术Background technique
平面栅IGBT器件相比于沟槽栅IGBT器件具有优越的可靠性，在具有较高可靠性要求的领域得到了大规模的应用。Planar gate IGBT devices have superior reliability compared to trench gate IGBT devices and have been widely used in fields with higher reliability requirements.
在针对平面栅IGBT器件的改进工艺中，降低平面栅IGBT导通压降普遍采用的方法是注入增强型N型杂质，形成的N型增强层位于整个晶圆的表面，以降低IGBT元胞间的电阻，但是此方法会造成IGBT的击穿电压(BV)下降，反向传输电容(Cres)升高。针对此方法改进的方法是在多晶刻蚀之后，利用多晶做阻挡层，局部注入增强型N型杂质，再推进，在P形体区外，主要是底部形成N型增强层来降低IGBT导通压降，此方法中N型增强层位于P形体区的底部，但是此方法会存在IGBT的导通压降(Vcesat)偏大的问题。In the improvement process of planar gate IGBT devices, a commonly used method to reduce the conduction voltage drop of planar gate IGBTs is to inject enhancement-type N-type impurities. The formed N-type enhancement layer is located on the surface of the entire wafer to reduce the resistance, but this method will cause the breakdown voltage (BV) of the IGBT to decrease and the reverse transmission capacitance (Cres) to increase. An improved method for this method is to use polycrystalline as a barrier layer after polycrystalline etching, locally inject enhancement-type N-type impurities, and then proceed to form an N-type enhancement layer at the bottom outside the P-shaped body region to reduce IGBT conductivity. In this method, the N-type enhancement layer is located at the bottom of the P-shaped body region, but this method will have the problem that the IGBT conduction voltage drop (Vcesat) is too large.
发明内容Contents of the invention
为解决现有技术的不足，本发明提供一种低导通压降平面栅IGBT的制备方法，能够解决现有技术在降低平面栅IGBT导通压降同时引起的击穿电压下降、反向传输电容升高的问题。In order to solve the deficiencies of the existing technology, the present invention provides a method for preparing a low conduction voltage drop planar gate IGBT, which can solve the problems of breakdown voltage drop and reverse transmission caused by the existing technology while reducing the conduction voltage drop of the planar gate IGBT. Capacitance rise problem.
为解决现有技术的不足，本发明提供的技术方案为：In order to solve the deficiencies of the existing technology, the technical solutions provided by the present invention are:
本发明提供一种低导通压降平面栅IGBT的制备方法，包括，The invention provides a method for preparing a low conduction voltage drop planar gate IGBT, which includes:
1)在N型漂移区正面进行光刻，注入N型杂质形成并列的第一N型增强部和第二N型增强部；所述第二N型增强部位于第一N型增强部外围，第一N型增强部和第二N型增强部存在间隙；所述第二N型增强部的注入深度小于第一N型增强部；1) Perform photolithography on the front side of the N-type drift region, and inject N-type impurities to form a parallel first N-type enhancement part and a second N-type enhancement part; the second N-type enhancement part is located on the periphery of the first N-type enhancement part, There is a gap between the first N-type enhancement part and the second N-type enhancement part; the injection depth of the second N-type enhancement part is smaller than the first N-type enhancement part;
2)对第一N型增强部和第二N型增强部进行N型杂质热推，形成呈阶梯形相连的N型增强层；2) Perform N-type impurity hot pushing on the first N-type enhancement part and the second N-type enhancement part to form an N-type enhancement layer connected in a ladder shape;
3)在N型漂移区正面进行栅氧生长和多晶淀积，制备栅极；3) Perform gate oxide growth and polycrystalline deposition on the front side of the N-type drift region to prepare the gate electrode;
4)对N型增强层上方的栅极进行光刻，注入P型杂质，进行P型杂质推进，在N型增强层内形成P型体区，构成P型体区的底部和侧面为N型增强层的N-P-N结构，且底部和侧面的N型增强层不相连；4) Photolithography is performed on the gate above the N-type enhancement layer, P-type impurities are injected, and P-type impurities are advanced to form a P-type body region in the N-type enhancement layer. The bottom and sides of the P-type body region are N-type. The N-P-N structure of the enhancement layer, and the N-type enhancement layers on the bottom and side are not connected;
5)在P型体区正面形成N+区；5) An N+ region is formed on the front side of the P-type body region;
6)在栅极和N+区正面沉积介质，形成介质层；6) Deposit dielectric on the front side of the gate and N+ area to form a dielectric layer;
7)在介质层正面进行接触孔光刻和金属溅射，形成发射极；7) Perform contact hole photolithography and metal sputtering on the front side of the dielectric layer to form the emitter;
8)在N型漂移区的背面注入P型杂质并退火形成P型集电区；8) Inject P-type impurities on the back side of the N-type drift region and anneal to form a P-type collector region;
9)在P型集电区背面进行金属溅射形成集电极。9) Perform metal sputtering on the back of the P-type collector area to form a collector.
优选的，所述步骤1)中的N型杂质通过注入模板注入；Preferably, the N-type impurities in step 1) are injected through an injection template;
所述注入模板包括第一注入部和第二注入部；The injection template includes a first injection part and a second injection part;
所述第一注入部用于注入N型杂质在N型漂移区形成第一N型增强部；The first injection part is used to inject N-type impurities into the N-type drift region to form a first N-type enhancement part;
所述第二注入部为环形，用于在第一N型增强部外围注入N型杂质形成第二N型增强部。The second injection part is annular and is used to inject N-type impurities around the periphery of the first N-type enhancement part to form a second N-type enhancement part.
优选的，所述第一N型增强部为圆柱或条形。Preferably, the first N-shaped reinforcement part is cylindrical or strip-shaped.
优选的，所述第二N型增强部与第一N型增强部形状相同。Preferably, the second N-type reinforced part has the same shape as the first N-type reinforced part.
优选的，所述P型体区与第一N型增强部形状相同。Preferably, the P-type body region has the same shape as the first N-type reinforcement part.
优选的，通过在P型体区正面注入N+杂质并推进，形成N+区。Preferably, the N+ region is formed by injecting and advancing N+ impurities on the front side of the P-type body region.
本发明的有益效果：Beneficial effects of the present invention:
本发明采用特殊的注入模板注入N型杂质，注入模板定义了N型杂质的注入区域，制备的N型增强层位于圆柱形P型体区的底部和侧面，形成N-P-N结构，这样制备出的N型增强层不在P型体区与栅极形成的沟道中，因此击穿电压不会下降；同时N型增强层在栅极下面的范围较小，不会升高反向传输电容；P型体区侧面的N型增强层能够降低该区域的电阻，降低平面栅IGBT的导通压降。The present invention uses a special injection template to inject N-type impurities. The injection template defines the injection area of N-type impurities. The prepared N-type enhancement layer is located at the bottom and side of the cylindrical P-type body region to form an N-P-N structure. The N-type enhanced layer prepared in this way The N-type enhancement layer is not in the channel formed by the P-type body region and the gate, so the breakdown voltage will not decrease; at the same time, the N-type enhancement layer has a smaller range under the gate and will not increase the reverse transmission capacitance; the P-type body The N-type enhancement layer on the side of the area can reduce the resistance of this area and reduce the conduction voltage drop of the planar gate IGBT.
附图说明Description of drawings
图1为现有技术中采用普遍注入法制备的平面栅IGBT的结构示意图；Figure 1 is a schematic structural diagram of a planar gate IGBT prepared by a universal injection method in the prior art;
图2为现有技术中采用多晶层做阻挡层制备的平面栅IGBT的结构示意图；Figure 2 is a schematic structural diagram of a planar gate IGBT prepared using a polycrystalline layer as a barrier layer in the prior art;
图3为本发明提供的低导通压降平面栅IGBT的结构示意图；Figure 3 is a schematic structural diagram of the low conduction voltage drop planar gate IGBT provided by the present invention;
图4为本发明提供的注入模板的示意图；Figure 4 is a schematic diagram of the injection template provided by the present invention;
图5为本发明制备的N型增强层的结构示意图；Figure 5 is a schematic structural diagram of the N-type enhancement layer prepared by the present invention;
图6为本发明制备的栅氧化层和栅极的示意图；Figure 6 is a schematic diagram of the gate oxide layer and gate electrode prepared by the present invention;
图7为本发明提供的P型杂质注入模板的结构示意图；Figure 7 is a schematic structural diagram of the P-type impurity implantation template provided by the present invention;
图8为本发明制备的N-P-N结构的示意图；Figure 8 is a schematic diagram of the N-P-N structure prepared by the present invention;
图9为本发明制备的N+区的结构示意图；Figure 9 is a schematic structural diagram of the N+ region prepared by the present invention;
图10为本发明制备的介质层的结构示意图；Figure 10 is a schematic structural diagram of the dielectric layer prepared by the present invention;
图11为本发明制备的发射极的结构示意图；Figure 11 is a schematic structural diagram of the emitter prepared by the present invention;
其中，1、N型漂移区；2、N型增强层；3、栅极；4、P型体区；5、N+区；6、介质层；7、发射极；8、P型集电区；9、集电极；10、栅氧化层；11、第一注入部；12、第二注入部；13、P型杂质注入器。Among them, 1. N-type drift region; 2. N-type enhancement layer; 3. Gate; 4. P-type body region; 5. N+ region; 6. Dielectric layer; 7. Emitter; 8. P-type collector region ; 9. Collector; 10. Gate oxide layer; 11. First injection part; 12. Second injection part; 13. P-type impurity injector.
具体实施方式Detailed ways
下面结合实施方式对本发明作进一步描述。以下实施方式仅用于更加清楚地说明本发明的技术方案，而不能以此来限制本发明的保护范围。The present invention will be further described below in conjunction with the embodiments. The following embodiments are only used to illustrate the technical solutions of the present invention more clearly, but cannot be used to limit the scope of the present invention.
本发明实施例提供一种低导通压降平面栅IGBT的制备方法，包括以下步骤：An embodiment of the present invention provides a method for preparing a low conduction voltage drop planar gate IGBT, which includes the following steps:
步骤一：在N型漂移区1正面进行光刻，注入N型杂质形成并列的第一N型增强部和第二N型增强部；第二N型增强部位于第一N型增强部外围，第一N型增强部和第二N型增强部存在间隙；第二N型增强部的注入深度小于第一N型增强部。Step 1: Perform photolithography on the front side of the N-type drift region 1, and inject N-type impurities to form a parallel first N-type enhancement part and a second N-type enhancement part; the second N-type enhancement part is located on the periphery of the first N-type enhancement part. There is a gap between the first N-type enhancement part and the second N-type enhancement part; the implantation depth of the second N-type enhancement part is smaller than the first N-type enhancement part.
第一N型增强部和第二N型增强部中N型杂质的掺杂浓度高于N型漂移区1。The doping concentration of N-type impurities in the first N-type enhancement part and the second N-type enhancement part is higher than that of the N-type drift region 1 .
N型漂移区1为圆片状，本发明中图3至图11均为以N型漂移区1的中心轴为边界的右半部的剖视图。The N-type drift region 1 is in the shape of a disc. In the present invention, FIGS. 3 to 11 are cross-sectional views of the right half of the N-type drift region 1 with the central axis as the boundary.
优选的，N型漂移区1通过在硅衬底表面进行磷注入形成。Preferably, the N-type drift region 1 is formed by phosphorus implantation on the surface of the silicon substrate.
优选的，注入的N型杂质为磷。Preferably, the injected N-type impurity is phosphorus.
优选的，第一N型增强部为圆柱形或第一N型增强部为条形。Preferably, the first N-type reinforced part is cylindrical or the first N-shaped reinforced part is strip-shaped.
优选的，第二N型增强部与第一N型增强部形状相同。Preferably, the second N-type reinforced part has the same shape as the first N-type reinforced part.
优选的，N型杂质通过注入模板注入。参见图4，注入模板包括第一注入部11和第二注入部12。第一注入部11用于注入N型杂质在N型漂移区1形成第一N型增强部，第二注入部12为环形，用于注入N型杂质在第一N型增强部外围形成第二N型增强部。Preferably, N-type impurities are injected through an injection template. Referring to FIG. 4 , the injection template includes a first injection part 11 and a second injection part 12 . The first injection part 11 is used to inject N-type impurities to form a first N-type enhancement part in the N-type drift region 1. The second injection part 12 is annular and is used to inject N-type impurities to form a second N-type enhancement part around the periphery of the first N-type enhancement part. N-type reinforcement.
步骤二：参见图5，对第一N型增强部和第二N型增强部进行N型杂质热推，形成呈阶梯形相连的N型增强层2。Step 2: Referring to FIG. 5 , perform N-type impurity hot pushing on the first N-type enhancement part and the second N-type enhancement part to form an N-type enhancement layer 2 connected in a ladder shape.
步骤三：在N型漂移区1正面进行栅氧生长和多晶淀积，制备栅极3，图6为制备的栅氧化层10和栅极3的结构示意图。Step 3: Perform gate oxide growth and polycrystalline deposition on the front side of the N-type drift region 1 to prepare the gate electrode 3. Figure 6 is a schematic structural diagram of the prepared gate oxide layer 10 and the gate electrode 3.
步骤四：参见图7及图8，对N型增强层2上方的栅极3进行光刻，采用P型杂质注入器13注入P型杂质，进行P型杂质推进，在N型增强层2内形成P型体区4，构成P型体区4的底部和侧面为N型增强层4的N-P-N结构，且底部和侧面的N型增强层4不相连。Step 4: Referring to Figures 7 and 8, perform photolithography on the gate 3 above the N-type enhancement layer 2, use the P-type impurity injector 13 to inject P-type impurities, and push the P-type impurities into the N-type enhancement layer 2 A P-type body region 4 is formed, and the bottom and sides of the P-type body region 4 are N-P-N structures of N-type enhancement layers 4, and the N-type enhancement layers 4 at the bottom and side are not connected.
优选的，P型杂质为硼。Preferably, the P-type impurity is boron.
优选的，P型体区与第一N型增强部形状相同。Preferably, the P-type body region has the same shape as the first N-type reinforcement part.
步骤五：参见图9，在P型体区4正面形成N+区5。Step 5: Referring to Figure 9, an N+ region 5 is formed on the front side of the P-type body region 4.
优选的，通过在P型体区4正面注入N+杂质并推进，形成N+区5。Preferably, the N+ region 5 is formed by injecting and advancing N+ impurities on the front side of the P-type body region 4 .
步骤六：参见图10，在栅极3和N+区5正面沉积介质，形成介质层6。Step 6: Referring to Figure 10, deposit dielectric on the front side of gate 3 and N+ region 5 to form dielectric layer 6.
步骤七：参见图11，在介质层6正面进行接触孔光刻和金属溅射，形成发射极7。Step 7: Referring to Figure 11, contact hole photolithography and metal sputtering are performed on the front side of the dielectric layer 6 to form the emitter 7.
步骤八：在N型漂移区1的背面注入P型杂质并退火形成P型集电区8。Step 8: Inject P-type impurities on the back side of the N-type drift region 1 and anneal to form a P-type collector region 8 .
步骤九：在P型集电区8背面进行金属溅射形成集电极9。最终形成结构如图3所示的低导通压降平面栅IGBT。Step 9: Perform metal sputtering on the back side of the P-type collector region 8 to form the collector electrode 9 . Finally, a low conduction voltage drop planar gate IGBT with a structure as shown in Figure 3 is formed.
表1为本发明所提供的低导通压降平面栅IGBT与现有平面栅IGBT的性能数据对比，其中结构1为图1所示的现有技术中采用普遍注入法制备的平面栅IGBT，结构2为图2所示的现有技术中采用多晶层做阻挡层制备的平面栅IGBT。从表1可以看出，本发明提供的低导通压降平面栅IGBT具有击穿电压高、反向传输电容低和导通压降较低的优点。Table 1 is a comparison of the performance data of the low conduction voltage drop planar gate IGBT provided by the present invention and the existing planar gate IGBT. Structure 1 is a planar gate IGBT prepared by the universal injection method in the prior art shown in Figure 1. Structure 2 is a planar gate IGBT prepared using a polycrystalline layer as a barrier layer in the prior art as shown in FIG. 2 . It can be seen from Table 1 that the low conduction voltage drop planar gate IGBT provided by the present invention has the advantages of high breakdown voltage, low reverse transmission capacitance and low conduction voltage drop.
表1三种结构IGBT参数对比Table 1 Comparison of IGBT parameters of three structures
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和变形，这些改进和变形也应视为本发明的保护范围。The above are only preferred embodiments of the present invention. It should be noted that those of ordinary skill in the art can also make several improvements and modifications without departing from the technical principles of the present invention. These improvements and modifications It should also be regarded as the protection scope of the present invention.
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| CN102569373A (en) * | 2012-03-08 | 2012-07-11 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with low-conductivity saturation voltage drop and manufacturing method for IGBT |
| CN107799587A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of reverse blocking IGBT and its manufacture method |
| KR20190100990A (en) * | 2018-02-21 | 2019-08-30 | 극동대학교 산학협력단 | Field stop insulated gate bipolar transistor |
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| CN102569373A (en) * | 2012-03-08 | 2012-07-11 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with low-conductivity saturation voltage drop and manufacturing method for IGBT |
| CN107799587A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of reverse blocking IGBT and its manufacture method |
| KR20190100990A (en) * | 2018-02-21 | 2019-08-30 | 극동대학교 산학협력단 | Field stop insulated gate bipolar transistor |
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| 3300 V FS型IGBT器件研制;朱涛;刘江;高明超;冷国庆;赵哿;王耀华;金锐;温家良;潘艳;;固体电子学研究与进展(04);全文 * |
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