CN112652536B - Preparation method of low-conduction voltage drop planar gate IGBT - Google Patents
Preparation method of low-conduction voltage drop planar gate IGBT Download PDFInfo
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- CN112652536B CN112652536B CN202011397875.1A CN202011397875A CN112652536B CN 112652536 B CN112652536 B CN 112652536B CN 202011397875 A CN202011397875 A CN 202011397875A CN 112652536 B CN112652536 B CN 112652536B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims description 37
- 238000002347 injection Methods 0.000 claims description 27
- 239000007924 injection Substances 0.000 claims description 27
- 210000000746 body region Anatomy 0.000 claims description 21
- 230000003014 reinforcing effect Effects 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 5
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000005540 biological transmission Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000002787 reinforcement Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 238000002513 implantation Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H01L29/66333—
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- H01L29/0638—
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- H01L29/7395—
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Abstract
The invention belongs to the technical field of power semiconductor device design, and particularly relates to a preparation method of a low-conduction voltage drop planar gate IGBT. The low-conduction voltage drop planar gate IGBT prepared by the method has the advantages of high breakdown voltage, low reverse transmission capacitance and low conduction voltage drop.
Description
Technical Field
The invention belongs to the technical field of power semiconductor device design, and particularly relates to a preparation method of a low-conduction voltage drop planar gate IGBT.
Background
Compared with a trench gate IGBT device, the planar gate IGBT device has superior reliability, and is applied in the field with higher reliability requirements on a large scale.
In the improved process for the planar gate IGBT device, a method for reducing the on-voltage drop of the planar gate IGBT is generally adopted to inject enhanced N-type impurities, and the formed N-type enhanced layer is located on the surface of the whole wafer to reduce the resistance between the IGBT cells, but this method may cause the Breakdown Voltage (BV) of the IGBT to decrease and the reverse transfer capacitance (Cres) to increase. The improved method for the method is characterized in that after polycrystalline etching, polycrystalline is used as a blocking layer, enhanced N-type impurities are locally injected, then the enhancement is carried out, an N-type enhancement layer is mainly formed at the bottom outside a P-shaped body region to reduce the conduction voltage drop of the IGBT, in the method, the N-type enhancement layer is positioned at the bottom of the P-shaped body region, but the method has the problem that the conduction voltage drop (Vcesat) of the IGBT is larger.
Disclosure of Invention
In order to solve the defects of the prior art, the invention provides a preparation method of a low-conduction voltage drop planar gate IGBT, which can solve the problems of breakdown voltage drop and reverse transmission capacitance rise caused by the reduction of the conduction voltage drop of the planar gate IGBT in the prior art.
In order to solve the defects in the prior art, the technical scheme provided by the invention is as follows:
the invention provides a preparation method of a low-conduction voltage drop planar gate IGBT, which comprises the following steps of,
1) Photoetching the front surface of the N-type drift region, and injecting N-type impurities to form a first N-type enhancement part and a second N-type enhancement part which are in parallel; the second N-type reinforcing part is positioned at the periphery of the first N-type reinforcing part, and a gap exists between the first N-type reinforcing part and the second N-type reinforcing part; the injection depth of the second N-type enhancement part is smaller than that of the first N-type enhancement part;
2) Performing N-type impurity hot pushing on the first N-type reinforcing part and the second N-type reinforcing part to form an N-type reinforcing layer connected in a stepped manner;
3) Performing gate oxide growth and polycrystalline deposition on the front surface of the N-type drift region to prepare a gate;
4) Photoetching a grid above the N-type enhancement layer, injecting P-type impurities, pushing the P-type impurities, forming a P-type body region in the N-type enhancement layer, forming an N-P-N structure with the bottom and the side of the P-type body region being the N-type enhancement layer, wherein the bottom and the N-type enhancement layer on the side are not connected;
5) Forming an N+ region on the front surface of the P-type body region;
6) Depositing a medium on the front sides of the grid electrode and the N+ region to form a medium layer;
7) Carrying out contact hole photoetching and metal sputtering on the front surface of the dielectric layer to form an emitter;
8) Injecting P-type impurities into the back surface of the N-type drift region and annealing to form a P-type collector region;
9) And performing metal sputtering on the back surface of the P-type collector region to form a collector.
Preferably, the N-type impurity in the step 1) is injected through an injection template;
the injection template comprises a first injection part and a second injection part;
the first injection part is used for injecting N-type impurities to form a first N-type enhancement part in the N-type drift region;
the second injection part is annular and is used for injecting N-type impurities at the periphery of the first N-type enhancement part to form a second N-type enhancement part.
Preferably, the first N-type reinforcement part is cylindrical or bar-shaped.
Preferably, the second N-type reinforcement portion has the same shape as the first N-type reinforcement portion.
Preferably, the P-type body region is the same shape as the first N-type enhancement.
Preferably, the n+ region is formed by implanting and advancing an n+ impurity in the front surface of the P-type body region.
The invention has the beneficial effects that:
the N-type impurity is injected by adopting the special injection template, the injection template defines an injection region of the N-type impurity, the prepared N-type enhancement layer is positioned at the bottom and the side surface of the cylindrical P-type body region to form an N-P-N structure, and the prepared N-type enhancement layer is not positioned in a channel formed by the P-type body region and the grid electrode, so that the breakdown voltage is not reduced; meanwhile, the range of the N-type enhancement layer below the grid electrode is smaller, so that the reverse transmission capacitance cannot be increased; the N-type enhancement layer on the side surface of the P-type body region can reduce the resistance of the region and reduce the conduction voltage drop of the planar gate IGBT.
Drawings
Fig. 1 is a schematic structural diagram of a planar gate IGBT fabricated by a common injection method in the prior art;
fig. 2 is a schematic structural diagram of a planar gate IGBT fabricated using a polycrystalline layer as a barrier layer in the prior art;
fig. 3 is a schematic structural diagram of a low-turn-on voltage drop planar gate IGBT according to the present invention;
FIG. 4 is a schematic illustration of an injection template provided by the present invention;
FIG. 5 is a schematic view of the structure of an N-type enhancement layer prepared according to the present invention;
FIG. 6 is a schematic diagram of a gate oxide and a gate electrode prepared according to the present invention;
FIG. 7 is a schematic diagram of a structure of a P-type impurity implantation template according to the present invention;
FIG. 8 is a schematic diagram of the N-P-N structure prepared according to the present invention;
FIG. 9 is a schematic structural view of the N+ region prepared according to the present invention;
FIG. 10 is a schematic diagram of a dielectric layer made in accordance with the present invention;
FIG. 11 is a schematic diagram of an emitter made in accordance with the present invention;
the device comprises a 1, N-type drift region; 2. an N-type enhancement layer; 3. a gate; 4. a P-type body region; 5. an N+ region; 6. a dielectric layer; 7. an emitter; 8. a P-type collector region; 9. a collector electrode; 10. a gate oxide layer; 11. a first injection part; 12. a second injection part; 13. p-type impurity injector.
Detailed Description
The invention is further described below in connection with embodiments. The following embodiments are only for more clearly illustrating the technical aspects of the present invention, and should not be used to limit the scope of the present invention.
The embodiment of the invention provides a preparation method of a low-conduction voltage drop planar gate IGBT, which comprises the following steps:
step one: photoetching the front surface of the N-type drift region 1, and injecting N-type impurities to form a first N-type enhancement part and a second N-type enhancement part which are in parallel; the second N-type reinforcing part is positioned at the periphery of the first N-type reinforcing part, and a gap exists between the first N-type reinforcing part and the second N-type reinforcing part; the second N-type enhancement portion is implanted to a depth less than that of the first N-type enhancement portion.
The doping concentration of the N-type impurity in the first N-type enhancement section and the second N-type enhancement section is higher than that in the N-type drift region 1.
The N-type drift region 1 has a circular plate shape, and fig. 3 to 11 are cross-sectional views of the right half of the N-type drift region 1.
Preferably, the N-type drift region 1 is formed by performing phosphorus implantation on the surface of the silicon substrate.
Preferably, the implanted N-type impurity is phosphorus.
Preferably, the first N-type reinforcement portion is cylindrical or the first N-type reinforcement portion is bar-shaped.
Preferably, the second N-type reinforcement is the same shape as the first N-type reinforcement.
Preferably, the N-type impurity is implanted through the implantation template. Referring to fig. 4, the injection mold includes a first injection part 11 and a second injection part 12. The first injection part 11 is used for injecting N-type impurities to form a first N-type enhancement part in the N-type drift region 1, and the second injection part 12 is annular and is used for injecting N-type impurities to form a second N-type enhancement part at the periphery of the first N-type enhancement part.
Step two: referring to fig. 5, the first N-type reinforcement portion and the second N-type reinforcement portion are thermally pushed with N-type impurities to form an N-type reinforcement layer 2 connected in a stepped shape.
Step three: gate oxide growth and polycrystalline deposition are performed on the front surface of the N-type drift region 1 to prepare a gate electrode 3, and fig. 6 is a schematic structural diagram of the prepared gate oxide layer 10 and the gate electrode 3.
Step four: referring to fig. 7 and 8, the gate electrode 3 above the N-type enhancement layer 2 is subjected to photolithography, P-type impurities are injected by a P-type impurity injector 13, P-type impurity propulsion is performed, a P-type body region 4 is formed in the N-type enhancement layer 2, an N-P-N structure with the bottom and the side of the P-type body region 4 being the N-type enhancement layer 4 is formed, and the bottom and the side of the N-type enhancement layer 4 are not connected.
Preferably, the P-type impurity is boron.
Preferably, the P-type body region is the same shape as the first N-type enhancement.
Step five: referring to fig. 9, n+ region 5 is formed on the front surface of P-type body region 4.
Preferably, n+ region 5 is formed by implanting and advancing n+ impurities in the front side of P-type body region 4.
Step six: referring to fig. 10, a dielectric layer 6 is formed by depositing a dielectric on the front sides of the gate electrode 3 and the n+ region 5.
Step seven: referring to fig. 11, contact hole lithography and metal sputtering are performed on the front surface of the dielectric layer 6 to form the emitter 7.
Step eight: p-type impurities are injected into the back surface of the N-type drift region 1 and annealed to form a P-type collector region 8.
Step nine: metal sputtering is performed on the back surface of the P-type collector region 8 to form a collector 9. The low on voltage drop planar gate IGBT with the structure shown in fig. 3 is finally formed.
Table 1 is a comparison of performance data of the low-turn-on voltage drop planar gate IGBT provided by the present invention and the conventional planar gate IGBT, wherein structure 1 is a planar gate IGBT prepared by a common injection method in the prior art shown in fig. 1, and structure 2 is a planar gate IGBT prepared by using a polycrystalline layer as a barrier layer in the prior art shown in fig. 2. As can be seen from table 1, the low-conduction voltage drop planar gate IGBT provided by the invention has the advantages of high breakdown voltage, low reverse transmission capacitance and low conduction voltage drop.
Table 1 comparison of IGBT parameters for three structures
| Index (I) | Structure 1 | Structure 2 | The invention is that |
| Vcesat(V) | 2.3 | 2.6 | 2.48 |
| BV(V) | 885 | 1000 | 1000 |
| Cres(nf) | 6.84 | 1 | 1.01 |
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (6)
1. A preparation method of a low-conduction voltage drop planar gate IGBT is characterized by comprising the steps of,
1) Photoetching the front surface of the N-type drift region, and injecting N-type impurities to form a first N-type enhancement part and a second N-type enhancement part which are in parallel; the second N-type reinforcing part is positioned at the periphery of the first N-type reinforcing part, and a gap exists between the first N-type reinforcing part and the second N-type reinforcing part; the injection depth of the second N-type enhancement part is smaller than that of the first N-type enhancement part;
2) Performing N-type impurity hot pushing on the first N-type reinforcing part and the second N-type reinforcing part to form an N-type reinforcing layer connected in a stepped manner;
3) Performing gate oxide growth and polycrystalline deposition on the front surface of the N-type drift region to prepare a gate;
4) Photoetching a grid above the N-type enhancement layer, injecting P-type impurities, pushing the P-type impurities, forming a P-type body region in the N-type enhancement layer, forming an N-P-N structure with the bottom and the side of the P-type body region being the N-type enhancement layer, wherein the bottom and the N-type enhancement layer on the side are not connected;
5) Forming an N+ region on the front surface of the P-type body region;
6) Depositing a medium on the front sides of the grid electrode and the N+ region to form a medium layer;
7) Carrying out contact hole photoetching and metal sputtering on the front surface of the dielectric layer to form an emitter;
8) Injecting P-type impurities into the back surface of the N-type drift region and annealing to form a P-type collector region;
9) And performing metal sputtering on the back surface of the P-type collector region to form a collector.
2. The method for manufacturing the low-turn-on voltage drop planar gate IGBT according to claim 1, wherein the N type impurity in step 1) is injected through an injection template;
the injection template comprises a first injection part and a second injection part;
the first injection part is used for injecting N-type impurities to form a first N-type enhancement part in the N-type drift region;
the second injection part is annular and is used for injecting N-type impurities at the periphery of the first N-type enhancement part to form a second N-type enhancement part.
3. The method for manufacturing a low-turn-on voltage drop planar gate IGBT of claim 1 wherein the first N type enhancement section is cylindrical or bar-shaped.
4. The method for manufacturing a low on-voltage drop planar gate IGBT of claim 3 wherein the second N type enhancement section is the same shape as the first N type enhancement section.
5. The method for manufacturing a low turn-on voltage drop planar gate IGBT of claim 1 wherein the P type body region is the same shape as the first N type enhancement.
6. The method for manufacturing the low-turn-on voltage drop planar gate IGBT of claim 1, wherein the n+ region is formed by injecting and advancing n+ impurities into the front surface of the P-type body region.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569373A (en) * | 2012-03-08 | 2012-07-11 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with low-conductivity saturation voltage drop and manufacturing method for IGBT |
| CN107799587A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of reverse blocking IGBT and its manufacture method |
| KR20190100990A (en) * | 2018-02-21 | 2019-08-30 | 극동대학교 산학협력단 | Field stop insulated gate bipolar transistor |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569373A (en) * | 2012-03-08 | 2012-07-11 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with low-conductivity saturation voltage drop and manufacturing method for IGBT |
| CN107799587A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of reverse blocking IGBT and its manufacture method |
| KR20190100990A (en) * | 2018-02-21 | 2019-08-30 | 극동대학교 산학협력단 | Field stop insulated gate bipolar transistor |
Non-Patent Citations (1)
| Title |
|---|
| 3300 V FS型IGBT器件研制;朱涛;刘江;高明超;冷国庆;赵哿;王耀华;金锐;温家良;潘艳;;固体电子学研究与进展(04);全文 * |
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