CN108242465B - A gate commutated thyristor and its preparation method - Google Patents

Abstract

The invention discloses a gate electrode current conversion thyristor and a gate electrode current conversion thyristorA preparation method. The layered structure of the thyristor of the invention is sequentially P from bottom to top in the vertical direction⁺Transparent emission anode, N' buffer layer, N-base region, P⁺Base region and semi-buried in P⁺N at the top of the base region⁺An emitter region, wherein: said N is⁺The emission area covers the P⁺A portion of the base tip; gate G is located at P⁺The part which is not covered by the N + emitter region is arranged on the top of the base region; the P is⁺The base region comprises P horizontally arranged side by side₁ ⁺Short base region and P₂ ⁺Short base region, wherein the P₁ ⁺The short base region is positioned right below the gate electrode G, and P₂ ⁺The short base region is positioned at the N⁺Directly below the emission area, P₁ ⁺The doping concentration of the short base region is lower than that of the P₂ ⁺The doping concentration of the short base region. Compared with the prior art, the invention not only improves the GCT current turn-off capability, but also reduces the turn-off energy; and the GCT trigger current is reduced, and the advantage of low-pass voltage drop of the GCT is kept.

Description

A gate commutated thyristor and its preparation method

technical field

The invention relates to the technical field of semiconductors, in particular to a gate commutated thyristor and a preparation method thereof.

Background technique

Gate Commutated Thyristors (GCT) are a kind of semiconductor device with super power capacity in the field of power electronics. The vertical structure of the existing GCT chip is sequentially from anode to cathode as P-type semiconductor layer P ₁ , N-type semiconductor layer N ₁ , P-type semiconductor layer P ₂ and N-type semiconductor four layers N ₂ , there are three PN junctions inside the device, from Anode to cathode are anode transparent junction ₍ J1 junction), blocking voltage main junction (J2 junction) and gate cathode junction _{( J3} junction).

GCT is divided into four working states: triggering (on), on-state, off and blocking. The working process is as follows:

Blocking state: When a forward voltage V _DC is applied between the anode and the cathode, the device is in a forward blocking state, and the blocking voltage is mainly borne by the reverse biased J ₂ junction. However, when GCT is blocked, a reverse bias voltage (or short circuit) within -20V must be applied to the gate-cathode of the device to avoid a significant reduction in the withstand voltage of the device due to the forward bias injection effect of the J ₃ junction.

Triggering (turning on) process: Before triggering, the device is in a blocking state, that is, the J ₂ and J ₃ junctions are in a reverse-biased blocking state. When a forward bias voltage is applied to the gate-cathode (J ₃ junction) of the chip and the gate forward pulse current amplitude ( _IG T ) and rate of rise (di/dt) are large enough, the J ₃ junction will inject electrons uniformly. Diffusion is finally pumped away from the anode end, and holes are injected uniformly into the J1 junction _of the PNP tube and finally pumped away from the cathode end through diffusion. When the sum of the current amplification factors of the two equivalent transistors is greater than 1 (that is, α _PNP + P _NPN >1), the GCT is turned on and kept on, and the macroscopic performance is that the GCT changes from a high-resistance state to a low-resistance state.

On-state: The GCT enters the on-state after it is turned on, and the device behaves as a thyristor. Due to the "hold-in" effect, the GCT can still maintain forward conduction even if the gate current is removed. At the same time, due to the conductance modulation effect generated by the ambipolar carriers in the N ₁ layer and the P ₂ layer, the GCT has the advantages of reduced on-state voltage and strong current capacity.

Turn-off process: apply -20V bias to the gate-cathode of the conducting GCT to turn off the J ₃ junction. Before the voltage of the J ₂ junction rises, the cathode current is fully switched to the gate (this is the so-called hard turn-off), GCT Enter the PNP tube working mode with open base. At this time, the excess electron carriers in the _N1 layer can be extracted through the transparent anode J1, and the excess hole carriers in the _P2 layer are extracted and drained through the gate electrode, so that the anode current _of the GCT is reliable in a very short time. turned off, while the _J2 junction regains its blocking capability. Macroscopically, the GCT switch changes from a low-resistance state to a high-resistance state.

In the above process, due to the reasons of the external circuit and/or the internal structure of the GCT, the GCT may turn off and fail in the actual application process. The main reasons are:

1) The hard turn-off condition cannot be met, that is, before the cathode current is fully switched to the gate, the voltage of the J ₂ junction starts to rise. This failure mechanism mainly occurs at low voltage (≤~2000V). _The gate cathode junction is not fully depleted, which means that the _J3 junction also has reverse electron current injected into the P2 layer and diffused to the _J2 junction depletion layer. This current acts as the base current of the pnp transistor with an open base, which activates the pnp transistor with a positive current gain. In a feedback mechanism, the anode injects holes into the base region, thereby accelerating the collapse of the depletion layer of the J junction, thereby preventing the GCT from _turning off. Under the unbuffered circuit, the GCT enters the GTO shutdown mode, and the GCT chip is easily destroyed.

2) The dynamic avalanche damage mechanism, that is, when the excess carriers generated by the dynamic avalanche accumulate enough under the N ₂ layer, the J ₃ can be turned on, thereby causing the device to turn off and fail. During the turn-off process of a large-sized GCT chip, due to the large gate impedance in the region far from the GCT gate contact area, the turn-off completion also occurs later, which is likely to cause current accumulation. On the other hand, the carriers generated by the dynamic avalanche _of the N1 layer act as the base current of the pnp transistor contained in the device, which is equivalent to an avalanche transistor positive feedback current gain mechanism, which accelerates further current accumulation in this region, Therefore, it may happen that the current under one or more of the cathode bars is high enough to trigger the thyristor to begin to resume conduction, thus causing the turn-off failure.

At present, in the prior art, the following methods are usually adopted to improve the turn-off capability of the GCT to avoid turn-off failure.

1) Develop 6-inch GCT by increasing device size.

2) By increasing the maximum turn-off current density as described below.

In the prior art, a method for increasing the maximum current density that can be turned off—high power GCT technology (HPT), is to form a transverse electric field by fabricating a corrugated P base region to extract holes under the cathode bars and reduce the current density under the bars. To prevent retriggering, a corrugated protrusion is formed in the N base region, resulting in the formation of a lateral electric field, which is beneficial to the gate electrode to extract the carriers of the P base region. Another feature is that the doping concentration of the P base region under the cathode comb is 2 to 5 times lower than the doping concentration of the gate P base region. However, the formation of the structure requires one ion implantation process and one selective ion implantation to form the aluminum, and the process is complicated and the manufacturing process cost is high.

Another method in the prior art to improve the turn-off current of the GCT is to insert a low-conductivity layer under the gate G, the purpose is to quickly extract the carrier concentration in the P base region to reduce the accumulation of carriers during the turn-off process. Below the cathode comb. The simulation shows that comparing the turn-off waveforms under the same turn-off conditions, the anode voltage rise time of the chip with this structure is slower than that of the standard GCT, which means that its storage time is longer, which means that the surrounding cathode combs are Inserting a low-conductivity layer under the GCT gate G is not conducive to extracting free carriers in the P base region.

Another GCT structure in the prior art to improve the GCT turn-off current is to insert a layer of low conductivity between the P ⁺ base region and the cathode comb around the cathode comb, or to form a layer of P in the P ⁺ layer through high-energy injection. ⁺ band layer, the simulation shows that although the off current can be increased, high-energy injection from the cathode side will greatly reduce the minority carrier lifetime of the P base region (the P ⁺ base region is highly doped, and its minority carrier lifetime is inherently very low), thereby improving The trigger current and on-state voltage drop of the chip are not conducive to improving the overall performance of the chip. On the other hand, the use of high-energy implantation results in higher cost of the chip manufacturing process.

In addition, by optimizing the width of the bars to achieve the same purpose of turning off the bars in the GCT chip, and controlling the gate hole current path to reduce the current density under the bars, the purpose of increasing the turn-off current density is achieved.

The above-mentioned methods in the prior art all have problems such as unsatisfactory improvement effect and complicated implementation process to varying degrees.

SUMMARY OF THE INVENTION

The invention provides a gate commutated thyristor, the vertical direction of the layered structure of the thyristor is P ⁺ transparent emission anode, N' buffer layer, N ^- base region, P base region, P ⁺ Base and N ⁺ emitter half-buried on top of the P ⁺ base, where:

the N ⁺ emitter region covers a portion of the top of the P ⁺ base region;

The gate electrode G is located on the part of the top of the P ⁺ base region that is not covered by the N ⁺ emitter region;

Cathode K is on top of the N ⁺ emitter;

the anode is located at the bottom of the P ⁺ transparent emitting anode;

The P ⁺ base region includes a horizontally side-by-side P ₁ ⁺ short base region and a P ₂ ⁺ short base region, wherein the P ₁ ⁺ short base region is located directly below the gate G, the P ₂ ⁺ short base region The region is located directly below the N ⁺ emitter region, and the P ₁ ⁺ short base region has a lower doping concentration than the P ₂ ⁺ short base region.

In one embodiment, the doping concentration of the P ₁ ⁺ short base region is 1E15˜1E18 cm ⁻³ , and the doping concentration of the P ₂ ⁺ short base region is 1E15˜8E18 cm ⁻³ .

In one embodiment, the diffusion depth of the P ₁ ⁺ short base region and the P ₂ ⁺ short base region is 40-80 μm.

In one embodiment, the doping concentration of the P ₁ ⁺ short base region and the P ₂ ⁺ short base region is controlled by the implantation dose of P-type impurities, the P ₁ ⁺ short base region and the P ₂ ⁺ The short base region is formed by ion implantation followed by high temperature diffusion advancement.

In one embodiment, the doping concentration of the P base region is 5E14˜2E16 cm ⁻³ .

In one embodiment, the diffusion coefficients of the P-type impurities in the P ₁ ⁺ short base region and the P ₂ ⁺ short base region are slower than the diffusion coefficients of the P-type impurities in the P base region.

In one embodiment, the P-type impurity of the P ₁ ⁺ short base region and the P ₂ ⁺ short base region is boron, and the P-type impurity of the P base region is aluminum or gallium.

In one embodiment, in the direction looking down on the thyristor from right above, the lateral range y of the coverage area of the P ₂ ⁺ short base region is 50 μm≤y≤6 mm, and the coverage area of the P ₂ ⁺ short base region The longitudinal extent x is 10 μm≦x≦500 μm.

In one embodiment, the wafer of the thyristor includes a plurality of N ⁺ emitter regions at different positions, and each N ⁺ emitter region corresponds to one of the P ₂ ⁺ short base regions, wherein, when viewed from right above In the direction of the thyristor, the coverage area of the P ₂ ⁺ short base region gradually increases in the order of distance from the gate lead-out portion of the thyristor from near to far.

The present invention also provides a method for preparing a thyristor, the method comprising:

Preparation of N ^- type single crystal silicon substrate;

The P ⁺ base region is formed by means of implantation diffusion, wherein the selective implantation is performed twice on the front side of the single crystal silicon substrate corresponding to the P ₁ ⁺ and P ₂ ⁺ short base doping concentrations respectively, or, firstly, in the The front side of the single crystal silicon substrate is implanted on the whole surface with the doping concentration corresponding to the P ₁ ⁺ short base region, and then the injection window corresponding to the P ₂ ⁺ short base region on the front side of the single crystal silicon substrate corresponds to the P ₂ ⁺ short base region. Implant with the difference in doping concentration of P ₁ ⁺ short base region;

The P base region is formed by aluminum injection diffusion or closed tube aluminum expansion process;

Perform full-surface implantation on the backside of the single crystal silicon substrate to form an N' buffer layer;

Manufacture and form N ⁺ emitter region on the front side of single crystal silicon substrate;

Full-surface implantation is performed on the back of the single crystal silicon substrate to form a P ⁺ transparent emitting anode;

Metal electrodes are formed.

Compared with the prior art, the present invention not only improves the turn-off current capability of the GCT and reduces the turn-off energy, but also reduces the trigger current of the GCT and maintains the advantage of the low on-state voltage drop of the GCT. The manufacturing method of the gate commutated thyristor of the present invention is simple and compatible with the existing process platform.

Other features or advantages of the present invention will be set forth in the description that follows. And some of the features or advantages of the invention will become apparent from the description, or will be learned by practice of the invention. The objectives and some advantages of the invention may be realized and attained by means of the steps particularly pointed out in the description, claims and drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the specification, and together with the embodiments of the present invention, are used to explain the present invention, and do not constitute a limitation to the present invention. In the attached image:

Fig. 1 is the existing GCT sectional structure diagram;

2 and 3 are GCT cross-sectional structural views according to an embodiment of the present invention;

FIG. 4 is a doping concentration distribution diagram of the P ⁺ base region according to an embodiment of the present invention;

Fig. 5 is the current density comparison chart under the GCT structure comb bar;

6 is a comparison diagram of the turn-off waveform of the GCT and the standard GCT according to an embodiment of the present invention;

7 is a comparison diagram of on-state voltage drop between a GCT and a standard GCT according to an embodiment of the present invention;

8 and 9 are schematic diagrams of the coverage of the P ₂ ⁺ short base region according to an embodiment of the present invention;

10 is a schematic diagram of the arrangement of the cathode combs of the GCT chip;

11 is a top view of a GCT chip according to an embodiment of the present invention;

12 is a cross-sectional view of a GCT chip according to an embodiment of the present invention;

13 is a schematic diagram of cross-sectional parameters of a GCT chip according to an embodiment of the present invention;

14 to 26 are flowcharts of chip fabrication according to embodiments of the present invention.

Detailed ways

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples, whereby the practitioners of the present invention can fully understand how the present invention applies technical means to solve technical problems, and achieve the realization process of technical effects and according to the above realization process The present invention is specifically implemented. It should be noted that, as long as there is no conflict, each embodiment of the present invention and each feature of each embodiment can be combined with each other, and the formed technical solutions all fall within the protection scope of the present invention.

The main structures in the longitudinal direction of the existing GCT chip are, from anode to cathode, a P-type semiconductor layer P ₁ , an N-type semiconductor layer N ₁ , a P-type semiconductor layer P ₂ and four N-type semiconductor layers N ₂ in sequence. There are three PN junctions inside the device, which are anode transparent junction (J ₁ junction), blocking voltage main junction (J ₂ junction) and gate cathode junction (J ₃ junction) from anode to cathode.

According to the degree of doping, the main structure in the longitudinal direction of the GCT chip can be subdivided into six layers, as shown in Figure 1, from bottom to top are 1 (P ⁺ transparent emission anode), 2 (N' buffer layer ), 3 (N ^- base/substrate), 4 (P base), 5 (P ⁺ base) and 6 (N ⁺ emitter), where 6 (N ⁺ emitter) is also known as the cathode comb strip.

6 (N ⁺ emitter) is half buried on top of 5 (P ⁺ base), 7 (Anode A) is connected at the bottom of 1 (P ⁺ transparent emitter anode); 8 and 10 (Gate G) are connected at 5 (P ⁺ base) without the top covered by 6 (N ⁺ emitter); 9 (cathode K) is connected on top of 6 (N ⁺ emitter). 11 is the J1 junction, ₁₂ is the J2 junction, and ₁₃ is the _J3 junction.

Generally, one GCT chip usually contains multiple basic GCT cells. In the top view of the cathode surface of the GCT, many "strip cathodes" are arranged radially, and each "strip cathode" (usually these "strip cathodes" are called cathode combs) corresponds to a basic GCT unit. On the cathode surface of GCT, with the center of the circle as the axis, the cathode surface is divided into several equal parts, and each equal part is a sector; several concentric circles are drawn on the cathode surface according to the length and number of the comb strips; the strips in the sector are along the arc Arranged and oriented parallel to the center line of the sector; the boundary area of the sector adds a single sliver according to the size of the area.

In this specification, a single GCT cell structure is mainly described to illustrate the GCT chip structure of the embodiment of the present invention.

As shown in FIG. 2 or FIG. 3 , in an embodiment of the present invention, the vertical direction of the layered structure of the thyristor is, from bottom to top, a P ⁺ transparent emitting anode, an N′ buffer layer, an N ^- base region, and a P base region. , a P ⁺ base, and an N ⁺ emitter half-buried on top of the P ⁺ base, where:

The N ⁺ emitter region covers part of the top of the P ⁺ base region;

The gate G is located on the part of the top of the P ⁺ base that is not covered by the N ⁺ emitter;

The cathode K is on top of the N ⁺ emitter;

The anode is at the bottom of the P ⁺ transparent emissive anode.

The P ⁺ base region is divided into two parts, which include the horizontally arranged P ₁ ⁺ short base region and the P ₂ ⁺ short base region, wherein the P ₁ ⁺ short base region is located directly under the gate G, and the P ₂ ⁺ short base region is located in The N ⁺ launch area is directly below. Further, the doping concentration of the P ₂ ⁺ short base region is higher than that of the P ₁ ⁺ short base region. FIG. 4 is a distribution diagram of the doping concentration of the P ⁺ base region, the abscissa is the depth, and the ordinate is the doping concentration. As shown in FIG. 4 , the doping concentration of BB (P ₂ ⁺ short base region) in FIG. 2 or FIG. 3 is higher than that of CC (P ₁ ⁺ short base region) in FIG. 2 or FIG. 3 .

The advantages of the GCT structure in an embodiment of the present invention are described below by comparing the relevant parameters of the standard GCT structure in the prior art and the GCT structure in an embodiment of the present invention in different states.

(a) Current density distribution under the cathode bar

Along the position indicated by the AA tangent in FIG. 1 , compare the current density under the same conditions between the standard GCT structure in the prior art and the GCT structure in an embodiment of the present invention under the same conditions. As shown in Figure 5, the ◇ line represents the standard GCT structure, the × line represents the GCT structure in an embodiment of the present invention, the abscissa is the position change in the lateral direction (AA tangent), and the ordinate is the current density. The structure proposed by the present invention greatly reduces the current density under the cathode comb, which is due to the high doping concentration of the P2 ₊ short base region ^, which provides a large number of holes, where the electrons recombine with the holes to reduce the P The amount of electron injection in the base and N-base regions, which results in a lower current density under the cathode bars. According to the GCT dynamic avalanche damage mechanism, this is beneficial to improve the GCT turn-off current.

(b) Turn-off waveform

Compare the turn-off waveforms under the same conditions between the standard GCT structure in the prior art and the GCT structure in an embodiment of the present invention under the same conditions. As shown in FIG. 6 , the ◇ line represents the standard GCT structure, the × line represents the GCT structure in an embodiment of the present invention, the abscissa is time, and the ordinate is voltage/current. The anode voltage rise time of the GCT of an embodiment of the present invention is earlier than that of the standard GCT, indicating that the extraction efficiency of all excess carriers in the J ₂ junction is higher, so a depletion layer is formed earlier to establish the anode voltage. This is due to two reasons: one is that the carrier density under the GCT cathode combs is less, and the other is that due to the high doping concentration of the P ₂ ⁺ base region under the GCT cathode combs, a lateral electric field will also be formed, which is conducive to the extraction of P Hole carriers in the base region to the gate.

(c) Trigger characteristics and on-state characteristics

According to the characteristics of the thyristor, the GCT trigger current is mainly determined by the lateral resistance R _G of the P ⁺ base region. The doping concentration of the P ₁ ⁺ base region (its resistance is R _G1 ) under the gate electrode of GCT remains basically unchanged, while the P ₂ ⁺ base region (its resistance is R _G2 ) under the cathode bar is highly doped, resulting in R _G2 It is much smaller than R _G1 , so the GCT triggering characteristic will not deteriorate basically.

In general, the smaller the P ⁺ base concentration is, the better it is to reduce the GCT on-state voltage drop, which is due to the fact that the injection efficiency of the _J3 emitter junction increases as the P ⁺ base concentration decreases. Figure 7 is a comparison of the on-state voltage drop between the GCT of an embodiment of the present invention and the standard GCT at 4000A@normal temperature, the ◇ line represents the standard GCT structure (the hollow ◇ line corresponds to the P ⁺ base concentration 1E17, the solid ◇ line corresponds to P ⁺ base concentration 1E18), the × line represents the GCT structure in an embodiment of the present invention (corresponding to P ₁ ⁺ base concentration 1E17, P ₂ ⁺ base concentration 1E18), the abscissa is the on-state current, and the ordinate is the on-state pressure drop. As shown in Fig. 7, increasing the doping concentration of the P ₂ ⁺ base region under the cathode bar will slightly increase the on-state voltage drop by about 0.1V. If the doping concentration is increased, the doping concentration of the entire P base region will be increased, and the on-state anode increase ≥ the region doping Miscellaneous (solid ◇ line). Therefore, the partition design of the doping concentration of the P ⁺ base region can take into account the turn-off capability, on-state voltage drop and triggering characteristics of the GCT.

To sum up, for a standard GCT chip, within a certain range, the GCT chip's turn-off current capability increases with the increase in the doping concentration of the P base region, but it is not conducive to reducing the trigger current and on-state voltage drop. On the other hand, according to the dynamic avalanche damage mechanism, when the GCT is turned off, if the carrier concentration accumulates too much under the cathode combs, according to the thermal effect and the negative temperature characteristics of the resistance, it is easy to cause the carrier to accumulate and eventually lead to breakdown and turn off. invalid. According to the relationship between the GCT structure of the prior art and its electrical characteristics, the novel GCT chip structure proposed by the present invention can not only maintain the advantages of low on-state voltage drop and trigger current of the GCT, but also reduce the current density under the cathode bar, thereby improving the GCT turns off current.

Further, one of the key points of the thyristor structure of the present invention is that the doping concentration of the P ₂ ⁺ short base region is higher than that of the P ₁ ⁺ short base region. Specifically, in an embodiment of the present invention, the doping concentration of the P ₁ ⁺ short base region is 1E15-1E18 cm ^-3 , and the doping concentration of the P ₂ ⁺ short base region is 1E15-8E18 cm ^-3 .

Further, the diffusion depth of the P ₁ ⁺ short base region and the P ₂ ⁺ short base region (the distance from the surface of the N ⁺ emitter junction to the dotted line shown in FIG. 2 or FIG. 3 ) is 40-80 μm.

Further, in order to control the doping concentration of the P ₂ ⁺ short base region and the P ₁ ⁺ short base region, in one embodiment, the P ₁ ⁺ short base region and the P ₂ ⁺ short base region are controlled by the implantation dose of P-type impurities. doping concentration. Specifically, the P ₁ ⁺ short base region and the P ₂ ⁺ short base region are formed by ion implantation followed by high temperature diffusion advancement.

Further, in an embodiment of the present invention, the diffusion coefficients of the P-type impurities in the P ₁ ⁺ short base region and the P ₂ ⁺ short base region are slower than the diffusion coefficients of the P-type impurities in the P base region. Specifically, the P-type impurities in the P ₁ ⁺ short base region and the P ₂ ⁺ short base region are boron (B) impurities, and the P-type impurities in the P base region are aluminum (Al) or gallium (Ga) impurities.

Further, in an embodiment of the present invention, the doping concentration of the P base region is 5E14˜2E16 cm ⁻³ , and the junction depth of the P base region is controlled by ion implantation of aluminum or the advancing time of closed aluminum diffusion.

In the GCT structure of the present invention, the P2 ₊ short base region is located directly below the N ⁺ emitter region ^. In one embodiment, the border of the P ₂ ⁺ short base region may exceed the border of the N ⁺ emitter region. As shown in FIG. 8 , the width of the P ₂ ⁺ short base region in the lateral direction is greater than the lateral width of the N ⁺ emitter region, That is, the coverage of the P ₂ ⁺ short base region can exceed the coverage of the N ⁺ emitting region, where the dotted line portion represents the coverage of the P ₂ ⁺ short base region, and the solid line portion represents the coverage of the N ⁺ emitting region.

Further, in another embodiment, the boundary of the P ₂ ⁺ short base region may be located inside the boundary of the N ⁺ emission region. As shown in FIG. 9 , the width of the P ₂ ⁺ short base region in the lateral direction is smaller than that of the N ⁺ emission region. Width in landscape. In the direction of looking down on the thyristor from right above, that is, the coverage of the P ₂ ⁺ short base region can be located within the coverage of the N ⁺ emitter region, where the dotted line part represents the coverage of the P ₂ ⁺ short base region, and the solid line part is the coverage of the N ⁺ emission area.

It should be noted here that when the boundary position of the P ₂ ⁺ short base region is beyond the cathode comb, if the P ₂ ⁺ short base region is designed too wide, the triggering characteristics and on-state characteristics will be affected. When the boundary position of the P ₂ ⁺ short base region is located inside the cathode comb, if the P ₂ ⁺ short base region is designed too narrowly, the effect of the P ₂ ⁺ short base region will be reduced, and the process difficulty will also be increased. Therefore, in an embodiment of the present invention, the width of the P ₂ ⁺ short base region is determined based on specific process constraints and GCT performance requirements. Specifically, in an embodiment of the present invention, in the direction of looking down the thyristor from right above, the lateral range y of the coverage area of the P ₂ ⁺ short base region is 50 μm≤y≤6 mm, and the P ₂ ⁺ short base region The longitudinal extent of the coverage area x is 10 μm ≤ x ≤ 500 μm.

Further, in the prior art, viewed from the lateral direction of the GCT chip, the cathode combs of the chip are uniformly arranged in a wafer using sector arcs or circumferences (as shown in FIG. 10 ). For GCT dies of different diameters, the cathode combs are generally arranged in a radial pattern according to 2 to 16 turns.

According to the size of the GCT turn-off current, the GCT gate lead-out position is mainly divided into three cases.

(a) Center gate: The gate is set at the center of the chip and is circular. Its contact area is small (about 0.5cm ² ), and the gate mechanical structure is simple, so it is more suitable for devices with low current capacity. Figure 9 shows the center gate arrangement.

(b) Ring gate: The gate is arranged in the middle of the chip and is in a circular shape. Its contact area is medium (about 2.5cm ² ), and the gate mechanical structure is relatively complex, so it is more suitable for devices with medium and high current capacity.

(c) Edge gate: The gate is arranged at the edge of the chip and is circular. Its contact area is large (about 5cm ² ), and the gate mechanical structure is complex. This structure is often used in large-scale reverse conduction GCT structures.

For the gate structure of GCT, because the gate impedance of the GCT chip is slightly different between the gate lead-out area and the gate lead-out area, the turn-off signal of the GCT chip has a slight time deviation between different GCT units. As a result, current redistribution is caused and current accumulation is generated in the region far from the gate extraction area (the current distribution away from the gate extraction area is denser), and finally, the GCT chip often fails at the location far away from the gate extraction area.

In the GCT structure of the present invention, due to the existence of the P ₂ ⁺ short base region and its width design, the off-current density of the cathode comb bars can be adjusted. Therefore, in one embodiment, by designing the P ₂ ⁺ short base widths under the cathode comb strips at different positions in the GCT wafer, current accumulation is avoided in the region away from the GCT gate during the turn-off process. Specifically, the width of the P ₂ ⁺ short base region under the cathode strip away from the GCT gate extraction site is designed to be wider to reduce the on-state current density and increase the turn-off speed, while the cathode near the GCT gate extraction site is designed to be wider. The width of the P2 ₊ short base area under the comb bar is designed to be narrower to increase the on-state current density ^and slow down the turn-off speed, so that the chip can be turned off uniformly, thereby improving the turn-off current capability of the GCT chip.

Figure 11 shows the top view of the GCT. The GCT contains multiple N ⁺ emitter regions (solid line ellipse) at different positions, and each N ⁺ emitter region corresponds to a P ₂ ⁺ short base region (dotted line ellipse), where, in the Looking down on the thyristor from above, the coverage area of the P ₂ ⁺ short base region (the area of the dotted ellipse) gradually increases in order from near to far from the thyristor gate lead-out portion.

Figure 12 shows a cross-sectional view of the GCT. The distance from the left to the right to the thyristor gate lead-out portion in the lateral direction gradually increases, and the width of the P ₂ ⁺ short base region also gradually increases.

Next, the detailed parameters of the GCT structured according to the embodiment of the present invention are described in detail through specific application examples.

Taking a 4-inch 4500V GCT design as an example, according to an embodiment of the present invention, the standard 4-inch 4500V GCT P ⁺ base is divided into two parts, ^{and the P2+} _base under the cathode combs has a higher doping concentration. In addition, the widths of the P ₂ ⁺ base regions under the cathode combs with different turns are designed differently to achieve the purpose of uniform GCT turn-off. The 4-inch GCT cathode comb bars are marked as No.1, No.2, . The design parameters of the 4-inch asymmetric GCT structure are defined as shown in Figure 13.

The doping concentration NP of the GCT _P base region is 1E15cm ^-3 to 5E15cm ^-3 , and the junction depth X _jP is 110μm to 130μm.

The GCT P ₁ ⁺ base doping concentration N _P1+ is 1E17cm ^-3 -5E17cm ^-3 , the P ₂ ⁺ base doping concentration N _P2+ is 1E18cm ^-3 -5E18cm ^-3 , and the junction depth X _jP+ is 55μm-65μm.

When the position of the middle annular gate electrode of the 4-inch asymmetric GCT is located between the 5th and 6th circles of cathode combs, the design of P ₂ ⁺ base region width x in each circle of cathode combs is shown in Table 1.

Table 1

Cathode sliver turns P₂⁺ base width X(μm) Cathode sliver turns P₂⁺ base width x (μm) No.1 80 No.6 40 No.2 40 No.7 40 No.3 40 No.8 80 No.4 40 No.9 120 No.5 40 No.10 120

When the middle annular gate position of the 4-inch reverse conducting GCT is designed to be located between the middle FRD and the first circle of cathode combs, the design of P ₂ ⁺ base region width x in each circle of cathode combs is shown in Table 2 or Table 3.

Table 2

Cathode sliver turns P₂⁺ base width x (μm) No.1 40 No.2 40 No.3 40 No.4 80 No.5 120

table 3

Cathode sliver turns P₂⁺ base width x (μm) No.1 20 No.2 40 No.3 60 No.4 80 No.5 120

Further, the present invention also provides a method for manufacturing a thyristor structured according to an embodiment of the present invention. Taking the formation process of a basic GCT unit of GCT as an example, in an embodiment of the present invention, the specific implementation steps are as follows:

1) N ^- type single crystal silicon substrate preparation

First, prepare an N-type doped monocrystalline silicon substrate (as shown in Figure 14). The substrate doping concentration and thickness are mainly determined by the GCT blocking voltage, on-state voltage drop and other parameters.

2) Fabrication to form a P ⁺ base region

The P ⁺ base region is formed by means of implantation diffusion, wherein the selective implantation is performed twice on the front side of the single crystal silicon substrate corresponding to the P ₁ ⁺ and P ₂ ⁺ short base region doping concentrations respectively, or, firstly, the single crystal silicon substrate is implanted on the front side of the single crystal silicon substrate. The bottom surface is implanted with the doping concentration corresponding to the P ₁ ⁺ short base region, and then the implantation window corresponding to the P ₂ ⁺ short base region on the front side of the single crystal silicon substrate corresponds to the P ₂ ⁺ short base region and the P ₁ ⁺ short base region. The difference in doping concentration in the region is implanted.

Specifically, in this embodiment, the P ⁺ base region of GCT is formed by boron B implantation and diffusion, which includes two schemes:

①P ₁ ⁺ and P ₂ ⁺ short base regions are formed by selective implantation and diffusion on the front surface of the single crystal silicon substrate twice. First, a selective implantation window of the P ₁ ⁺ base region is formed, the implantation doping impurity is B ⁺ , and the implant dose E _B1 is determined according to the doping concentration of the P ₁ ⁺ base region (as shown in FIG. 15 ). Then, according to the width of the P ₂ ⁺ base region of each turn of the GCT, an implantation window of corresponding size is formed, and the doping impurity B ⁺ is implanted again. This time, the implant dose E _B2 is determined according to the doping concentration of the P ₂ ⁺ base region (eg Figure 16). Finally, high-temperature diffusion is performed at the same time to control the boron junction depth in the P ⁺ base region within the design range (as shown in Figure 17).

②The P ₂ ⁺ short base region is formed by one selective implantation and diffusion in the P ₁ ⁺ short base region. First, the whole surface is implanted on the front side of the single crystal silicon substrate, and the implanted doping impurity is B+, and the dose E _B1 is determined according to the doping concentration of the P ₁ ⁺ short base region (as shown in FIG. 18 ). Then, according to the width of the P ₂ ⁺ short base region of each turn of the GCT, an implantation window of the corresponding size is formed, and the doping impurity B ⁺ is implanted again. The implant dose this time should be △ _{EB =E B2 -E B1} , where the dose E _B2 depends on the doping concentration of the P2 ₊ short base region ⁽ as shown in Figure 19). Finally, high temperature diffusion is performed at the same time to control the boron junction depth in the P ⁺ base region within the design range (as shown in Figure 20).

Compared with scheme ①, scheme ② is simpler to manufacture and has lower cost, and this scheme is preferred in the manufacturing process.

3) P base region formation

The formation process of the P base region is shown in FIG. 21 and FIG. 22 . First, the P base region is formed (as shown in FIG. 21 ), and then the rear P-type doped layer is removed (as shown in FIG. 22 ). Specifically, in this embodiment, the P base region is formed by using the aluminum injection diffusion or closed-tube aluminum expansion process. The two process solutions are as follows:

a) Diffusion process of aluminum injection: firstly, the whole surface is implanted on the front side of the single crystal silicon substrate, and the implanted impurity is Al ⁺ , and the implantation dose E _Al is determined according to the doping concentration of the P base region. Then, a layer of Si ₃ N ₄ film is deposited by LPCVD process, and then high temperature pushing is carried out in a nitrogen atmosphere to control the Al junction depth in the P base region within the design range. Then the P-type doped layer on the backside is removed by etching or single-side grinding.

b) Closed tube aluminum expansion: in the vacuum furnace tube saturated aluminum atmosphere, carry out high temperature advance for a certain time t, the time t is controlled according to the design value of the Al junction depth in the P base region, and then etch or single-side grinding and polishing to remove the P-type doping on the back side Floor.

The two processes have their own advantages and disadvantages: the surface quality of the chip formed by the aluminum injection diffusion process is better, and the subsequent formation of the cathode comb structure is used. The closed-tube aluminum expansion process is simple, and the mass production cost is low.

4) N' buffer layer formation

The N' buffer layer is implanted on the back of the single crystal silicon substrate, and the implantation impurity is phosphorus ( _P ⁺ ). , the junction depth of the N' buffer layer is controlled within the design range (as shown in Figure 23).

5) Formation of N ⁺ emitter (cathode bar)

N ⁺ phosphorus diffusion is carried out on the front side of the single crystal silicon substrate, and the doping gas source flow and diffusion time in the phosphorus diffusion furnace are determined according to the doping concentration and junction depth of the N ⁺ bar structure ^. Structural controls are within the design limits. Then, selective etching is performed on the cathode comb layer to form a GCT cathode comb structure (as shown in FIG. 24 ).

6) Transparent anode P ⁺ formation

The transparent anode P ⁺ layer is implanted on the back of the single crystal silicon substrate, and the implanted impurity is boron (B), and the implantation dose E _AP is determined according to the doping concentration of the transparent anode P ⁺ layer. Push forward to control the transparent anode P ⁺ layer junction depth within the design range (as shown in Figure 25).

Full-surface implantation is performed on the back of the single crystal silicon substrate to form a P ⁺ transparent emitting anode;

7) Metal electrode formation

After the gate and cathode passivation isolation is formed, metal electrode layers are deposited on all surfaces of the die, and after etching, a GCT unit cell structure is formed (as shown in FIG. 26 ).

In conclusion, the present invention proposes a gate commutated thyristor. The invention independently designs the turn-off speed of the GCT unit and improves the turn-off uniformity. Compared with the prior art, the present invention not only improves the turn-off current capability of the GCT and reduces the turn-off energy, but also reduces the trigger current of the GCT and maintains the advantage of the low on-state voltage drop of the GCT. Further, the gate commutated thyristor structure of the present invention is suitable for all types and sizes of GCT unit cell designs, especially on large-sized GCTs, and the turn-off uniformity can be adjusted. The manufacturing method of the gate commutated thyristor of the present invention is simple and compatible with the existing process platform.

Although the disclosed embodiments of the present invention are as above, the content described is only an embodiment adopted to facilitate understanding of the present invention, and is not intended to limit the present invention. There are also various other embodiments of the method described in the present invention. Without departing from the essence of the present invention, those skilled in the art can make various corresponding changes or deformations according to the present invention, but these corresponding changes or deformations should all belong to the protection scope of the claims of the present invention.

Claims (10)

1. A gate-commutated thyristor is characterized in that the vertical direction of the layered structure of the thyristor is sequentially P from bottom to top⁺Transparent emitting anode, N' buffer layer, N^-Base region, P⁺Base region and semi-buried in P⁺N at the top of the base region⁺An emitter region, wherein:

said N is⁺The emission area covers the P⁺A portion of the base tip;

gate G is located at P⁺The base region top is N⁺On the part not covered by the emitting area;

cathode K is positioned at the N⁺The top of the emitting region;

the anode is positioned at the P⁺The bottom of the transparent emitting anode;

the P is⁺The base region comprises P horizontally arranged side by side₁ ⁺Short base region and P₂ ⁺Short base region, wherein the P₁ ⁺The short base region is positioned right below the gate electrode G, and P₂ ⁺The short base region is positioned at the N⁺Directly below the emission area, P₁ ⁺The doping concentration of the short base region is lower than that of the P₂ ⁺The doping concentration of the short base region.

2. The thyristor according to claim 1, wherein the P is₁ ⁺The doping concentration of the short base region is 1E 15-1E 18cm^-3Said P is₂ ⁺The doping concentration of the short base region is 1E 15-8E 18cm^-3。

3. The thyristor according to claim 1, wherein the P is₁ ⁺Short base region and the P₂ ⁺The diffusion depth of the short base region is 40-80 μm.

4. The thyristor according to claim 1, wherein the P is₁ ⁺Short base region and the P₂ ⁺The doping concentration of the short base region is controlled by the injection dosage of the P-type impurity, and the P is₁ ⁺Short base region and the P₂ ⁺The short base region is formed by ion implantation and then high-temperature diffusion propulsion.

5. The thyristor according to claim 1, wherein the doping concentration of the P base region is 5E 14-2E 16cm^-3。

6. The thyristor according to claim 1, wherein the P is₁ ⁺Short base region and the P₂ ⁺The diffusion coefficient of the P-type impurity of the short base region is slower than that of the P-type impurity of the P base region.

7. The thyristor according to claim 6, wherein P is₁ ⁺Short base region and the P₂ ⁺The P-type impurity of the short base region is boron, and the P-type impurity of the P base region is aluminum or gallium.

8. A thyristor according to any one of claims 1 to 7, wherein the P is in a direction looking down the thyristor from directly above₂ ⁺The transverse range y of the coverage area of the short base region is more than or equal to 50 mu m and less than or equal to 6mm, and P₂ ⁺The longitudinal range x of the coverage area of the short base region is more than or equal to 10 mu m and less than or equal to 500 mu m.

9. The thyristor according to any one of claims 1-7, wherein a wafer of the thyristor comprises a plurality of N at different positions⁺Emitting areas of each N⁺One P is corresponding to the right lower part of the emission area₂ ⁺A short base region, wherein, in the direction of overlooking the thyristor from the right top, the P is arranged from the near to the far in sequence from the leading-out part of the gate pole of the thyristor₂ ⁺The coverage area of the short base region gradually increases.

10. A method of making a thyristor according to any one of claims 1-9, the method comprising:

preparation of N^-A type single crystal silicon substrate;

p formation by implantation diffusion fabrication⁺Base regions, wherein, respectivelyShould P₁ ⁺And P₂ ⁺Selectively implanting the doping concentration of the short base region on the front surface of the monocrystalline silicon substrate twice, or firstly, correspondingly implanting P on the front surface of the monocrystalline silicon substrate₁ ⁺The doping concentration of the short base region is subjected to whole-surface implantation, and then the front surface of the monocrystalline silicon substrate corresponds to P₂ ⁺The implantation window of the short base region corresponds to P₂ ⁺Short base region and P₁ ⁺Injecting the doping concentration difference of the short base region;

manufacturing and forming a P base region by adopting an aluminum injection diffusion or closed tube aluminum expansion process;

performing whole-surface injection manufacturing on the back surface of the monocrystalline silicon substrate to form an N' buffer layer;

forming N on the front surface of monocrystalline silicon substrate⁺An emission region;

forming P by performing whole-surface implantation on the back surface of the single crystal silicon substrate⁺A transparent emissive anode;

forming a metal electrode.

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