CN108242465B - Gate electrode current conversion thyristor and preparation method thereof - Google Patents
Gate electrode current conversion thyristor and preparation method thereof Download PDFInfo
- Publication number
- CN108242465B CN108242465B CN201611205266.5A CN201611205266A CN108242465B CN 108242465 B CN108242465 B CN 108242465B CN 201611205266 A CN201611205266 A CN 201611205266A CN 108242465 B CN108242465 B CN 108242465B
- Authority
- CN
- China
- Prior art keywords
- base region
- short base
- gct
- short
- doping concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 238000006243 chemical reaction Methods 0.000 title abstract description 4
- 238000009792 diffusion process Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 29
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 27
- 238000002513 implantation Methods 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 19
- 229910052782 aluminium Inorganic materials 0.000 claims description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 238000002347 injection Methods 0.000 claims description 15
- 239000007924 injection Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 9
- 230000000903 blocking effect Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- 239000000969 carrier Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- XUKUURHRXDUEBC-SXOMAYOGSA-N (3s,5r)-7-[2-(4-fluorophenyl)-3-phenyl-4-(phenylcarbamoyl)-5-propan-2-ylpyrrol-1-yl]-3,5-dihydroxyheptanoic acid Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-SXOMAYOGSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000004220 aggregation Methods 0.000 description 3
- 230000002776 aggregation Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 108091006149 Electron carriers Proteins 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical class [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 210000001520 comb Anatomy 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009024 positive feedback mechanism Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
Abstract
The invention discloses a gate electrode current conversion thyristor and a gate electrode current conversion thyristorA preparation method. The layered structure of the thyristor of the invention is sequentially P from bottom to top in the vertical direction+Transparent emission anode, N' buffer layer, N-base region, P+Base region and semi-buried in P+N at the top of the base region+An emitter region, wherein: said N is+The emission area covers the P+A portion of the base tip; gate G is located at P+The part which is not covered by the N + emitter region is arranged on the top of the base region; the P is+The base region comprises P horizontally arranged side by side1 +Short base region and P2 +Short base region, wherein the P1 +The short base region is positioned right below the gate electrode G, and P2 +The short base region is positioned at the N+Directly below the emission area, P1 +The doping concentration of the short base region is lower than that of the P2 +The doping concentration of the short base region. Compared with the prior art, the invention not only improves the GCT current turn-off capability, but also reduces the turn-off energy; and the GCT trigger current is reduced, and the advantage of low-pass voltage drop of the GCT is kept.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gate commutated thyristor and a preparation method thereof.
Background
A Gate Commutated Thyristor (GCT) is a semiconductor device with ultra-high power capacity in the field of power electronics. The longitudinal structure of the prior GCT chip is a P-type semiconductor layer P from an anode to a cathode in sequence1N-type semiconductor layer N1P-type semiconductor layer P2Andn-type semiconductor four-layer N 23 PN junctions exist in the device, and anode transparent junctions (J) are respectively arranged from the anode to the cathode1Junction), main blocking voltage junction (J)2Junction) and gate cathode junction (J)3A knot).
GCT is divided into four operating states: triggering (switching on), switching on, switching off and blocking, wherein the working process is as follows:
a blocking state: when a forward voltage V is applied between anode and cathodeDCThe device is in a forward blocking state, and the blocking voltage is mainly reversely biased by J2The junction is stressed. However, when GCT is blocked, a reverse bias voltage within-20V (or short circuit) must be applied to the gate-cathode of the device to avoid J3The forward bias injection effect of the junction makes the device withstand voltage significantly reduced.
Triggering (switching on) process: before triggering, the device is in the blocking state, i.e. J2、J3The junction is in a reverse biased blocking state. Gate-cathode to chip (J)3Junction) is applied with a forward bias voltage and gate forward pulse current amplitude (I)GT) And the rate of rise (di/dt) is sufficiently large, when J is present3The junction will uniformly inject electrons, and the PNP tube J will be finally extracted from the anode end by diffusion1When the sum of the current amplification factors of the two equivalent transistors is greater than 1 (i.e. α)PNP+PNPN>1) In time, the GCT is turned on and remains latched, which macroscopically represents that the GCT is changed from a high-resistance state to a low-resistance state.
An on state: after the GCT is turned on, the device enters a conducting state, and the device has the characteristic of a thyristor. Because of the "latch-up" effect, the GCT can maintain forward conduction even if the gate current is removed. At the same time, since N1Layer and P2The GCT has the advantages of low on-state voltage and strong current capacity due to the conductivity modulation effect generated by the bipolar carriers of the layer.
And (3) a turn-off process: biasing the gate-cathode of the GCT in conduction with-20V to make J3At junction cut-off, at J2Before the junction voltage rises, the cathode current is switched to the gate (this is called hard turn-off), and the GCT enters the PNP operation mode with open base. At this time, N1Excess electron carriers of the layer may traverseTransparent anode J1Pumping away, P2The surplus hole carrier of the layer is extracted and discharged through the gate pole, so that the anode current of the GCT is reliably cut off in a very short time, and J is simultaneously2The node regains the blocking capacity. Macroscopically it appears that the GCT switch transitions from a low resistance state to a high resistance state.
In the above process, the GCT may fail to turn off during practical application due to external circuits and/or internal structure of the GCT. The main reasons are as follows:
1) the hard-off condition cannot be satisfied, i.e., at J before the cathode current is not all switched to the gate2The junction voltage begins to rise. This failure mechanism occurs primarily at low pressures (< 2000V). The gate cathode junction is not fully depleted, meaning J3The junction also has reverse electron current injection P2Layer diffusion to J2A junction depletion layer, which acts as a base current for an open-base pnp transistor, activates the current gain positive feedback mechanism of the pnp transistor, and injects holes from the anode into the base region, thereby accelerating J2The junction depletion layer collapses, preventing the GCT from turning off. Under the condition of no buffer circuit, the GCT enters a GTO shutdown mode, and the GCT chip is easy to destroy.
2) Dynamic avalanche breakdown mechanism, i.e. dynamic avalanche generates excess carriers to be accumulated in N2Sufficient under the layer to promote J3Conducting, causing the device to fail to turn off. In the turn-off process of the large-size GCT chip, because the gate resistance of the region far away from the GCT gate contact is large, the turn-off is finished later, and the current aggregation is easily caused. On the other hand, N1The carriers generated by layer dynamic avalanche act as base current for pnp transistors included in the device, which is equivalent to a positive feedback current gain mechanism of an avalanche transistor, thus accelerating further current collection in this region, and therefore it may happen that when the current under one or more cathode combs is high enough, the thyristor can be triggered to start to turn back on, thereby causing turn-off failure.
Currently, in the prior art, the following method is generally adopted to improve the turn-off capability of the GCT and avoid the turn-off failure.
1) By increasing the device size, a 6 inch GCT was developed.
2) By raising the maximum off-state current density, as described below.
In the prior art, a method for increasing the maximum turn-off current density, namely a High Power Technology (HPT), is used for forming a ripple P base region to form a transverse electric field, so that a cavity below a cathode comb strip is drawn away, the current density below the comb strip is reduced, and the current density is prevented from being retriggered. The other characteristic is that the doping concentration of the P base region below the cathode comb strip is 2-5 times lower than that of the gate P base region. However, the formation of the structure requires 1 time of ion-implantation aluminum process and 1 time of selective ion-implantation aluminum formation, and the process is complex and the manufacturing process cost is high.
Another method for increasing the turn-off current of the GCT in the prior art is to insert a low conductive layer below the gate G in order to quickly extract the P-base region carrier concentration to reduce the accumulation of carriers below the cathode comb during turn-off. Simulation shows that the rising time of the anode voltage of the chip with the structure is slower than that of the standard GCT by comparing the turn-off waveforms under the same turn-off condition, which means that the storage time is longer, so that the P base region free carriers are not favorably extracted after the low conductive layer is inserted below the GCT gate G around the cathode comb strip.
Another GCT structure for improving the GCT turn-off current in the prior art is to surround a cathode comb strip at P+A low conductive layer is inserted between the base region and the cathode comb strip or is P+Forming a layer of P in the layer by high energy implantation+In the tape layer, it was found by simulation that although the off-current could be increased, the P-base minority carrier lifetime (P) could be greatly reduced by high-energy implantation from the cathode surface+The base region is highly doped, and the minority carrier lifetime of the base region is originally very short), so that the trigger current and the on-state voltage drop of the chip are improved, and the overall performance of the chip is not favorably improved. On the other hand, the use of high energy implantation results in higher chip manufacturing process costs.
In addition, the aim of consistent turn-off of the comb strips in the GCT chip is achieved by optimizing the width of the comb strips, and the aim of improving the turn-off current density is achieved by controlling a gate hole current path to reduce the current density below the comb strips.
The methods in the prior art have the problems of unsatisfactory lifting effect, complex implementation process and the like in different degrees.
Disclosure of Invention
The invention provides a gate-commutated thyristor, wherein the vertical direction of the layered structure of the thyristor is sequentially P from bottom to top+Transparent emitting anode, N' buffer layer, N-Base region, P+Base region and semi-buried in P+N at the top of the base region+An emitter region, wherein:
said N is+The emission area covers the P+A portion of the base tip;
gate G is located at P+The base region top is N+On the part not covered by the emitting area;
cathode K is positioned at the N+The top of the emitting region;
the anode is positioned at the P+The bottom of the transparent emitting anode;
the P is+The base region comprises P horizontally arranged side by side1 +Short base region and P2 +Short base region, wherein the P1 +The short base region is positioned right below the gate electrode G, and P2 +The short base region is positioned at the N+Directly below the emission area, P1 +The doping concentration of the short base region is lower than that of the P2 +The doping concentration of the short base region.
In one embodiment, the P1 +The doping concentration of the short base region is 1E 15-1E 18cm-3Said P is2 +The doping concentration of the short base region is 1E 15-8E 18cm-3。
In one embodiment, the P1 +Short base region and the P2 +The diffusion depth of the short base region is 40-80 μm.
In one embodiment, the P1 +Short base region and the P2 +The doping concentration of the short base region is controlled by injecting P-type impuritiesA preparation of said P1 +Short base region and the P2 +The short base region is formed by ion implantation and then high-temperature diffusion propulsion.
In one embodiment, the doping concentration of the P base region is 5E 14-2E 16cm-3。
In one embodiment, the P1 +Short base region and the P2 +The diffusion coefficient of the P-type impurity of the short base region is slower than that of the P-type impurity of the P base region.
In one embodiment, the P1 +Short base region and the P2 +The P-type impurity of the short base region is boron, and the P-type impurity of the P base region is aluminum or gallium.
In one embodiment, the P is in a direction looking down the thyristor from directly above2 +The transverse range y of the coverage area of the short base region is more than or equal to 50 mu m and less than or equal to 6mm, and P2 +The longitudinal range x of the coverage area of the short base region is more than or equal to 10 mu m and less than or equal to 500 mu m.
In one embodiment, the wafer of thyristors comprises a plurality of N at different positions+Emitting areas of each N+One P is corresponding to the right lower part of the emission area2 +A short base region, wherein, in the direction of overlooking the thyristor from the right top, the P is arranged from the near to the far in sequence from the leading-out part of the gate pole of the thyristor2 +The coverage area of the short base region gradually increases.
The invention also provides a method for preparing the thyristor, which comprises the following steps:
preparation of N-A type single crystal silicon substrate;
p formation by implantation diffusion fabrication+Base regions, wherein each corresponds to P1 +And P2 +Selectively implanting the doping concentration of the short base region on the front surface of the monocrystalline silicon substrate twice, or firstly, correspondingly implanting P on the front surface of the monocrystalline silicon substrate1 +The doping concentration of the short base region is subjected to whole-surface implantation, and then the front surface of the monocrystalline silicon substrate corresponds to P2 +Short base region implantationGo into window to correspond to P2 +Short base region and P1 +Injecting the doping concentration difference of the short base region;
manufacturing and forming a P base region by adopting an aluminum injection diffusion or closed tube aluminum expansion process;
performing whole-surface injection manufacturing on the back surface of the monocrystalline silicon substrate to form an N' buffer layer;
forming N on the front surface of monocrystalline silicon substrate+An emission region;
forming P by performing whole-surface implantation on the back surface of the single crystal silicon substrate+A transparent emissive anode;
forming a metal electrode.
Compared with the prior art, the invention not only improves the GCT current turn-off capability, but also reduces the turn-off energy; and the GCT trigger current is reduced, and the advantage of low-pass voltage drop of the GCT is kept. The manufacturing method of the gate pole commutating thyristor is simple and is compatible with the prior process platform.
Additional features and advantages of the invention will be set forth in the description which follows. And in part will be obvious from the description, or may be learned by practice of the invention. The objectives and some of the advantages of the invention may be realized and attained by the process particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a cross-sectional view of a conventional GCT;
FIGS. 2 and 3 are cross-sectional block diagrams of GCT according to embodiments of the present invention;
FIG. 4 is a diagram of P according to an embodiment of the present invention+Base region doping concentration distribution diagram;
FIG. 5 is a graph of current density comparison under a GCT structure sliver;
FIG. 6 is a graph comparing the turn-off waveforms of the GCT and a standard GCT according to an embodiment of the present invention;
FIG. 7 is a graph comparing the on-state pressure drop of a GCT of one embodiment of the present invention with that of a standard GCT;
FIGS. 8 and 9 are P according to an embodiment of the present invention2 +Schematic coverage of the short base region;
FIG. 10 is a schematic view of the arrangement of cathode bars of GCT chips;
FIG. 11 is a top view of a GCT chip according to one embodiment of the present invention;
FIG. 12 is a cross-sectional view of a GCT chip according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of cross-sectional parameters of a GCT chip according to one embodiment of the present invention;
fig. 14-26 are chip fabrication flow diagrams according to embodiments of the invention.
Detailed Description
The following detailed description will be provided for the embodiments of the present invention with reference to the accompanying drawings and examples, so that the practitioner of the present invention can fully understand how to apply the technical means to solve the technical problems, achieve the technical effects, and implement the present invention according to the implementation procedures. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
The main structure of the prior GCT chip in the longitudinal direction is a P-type semiconductor layer P from an anode to a cathode1N-type semiconductor layer N1P-type semiconductor layer P2And N-type semiconductor four-layer N2. 3 PN junctions exist in the device, and anode transparent junctions (J) are respectively arranged from the anode to the cathode1Junction), main blocking voltage junction (J)2Junction) and gate cathode junction (J)3A knot).
The GCT chip can be subdivided into six layers according to the degree of doping, wherein the main structure in the longitudinal direction of the GCT chip is 1 (P) from bottom to top as shown in FIG. 1+Transparent emitting anode), 2 (N' buffer layer), 3 (N)-Base region/substrate), 4(P base region), 5(P base region)+Base region) and 6 (N)+Emission region) of which 6 (N)+Emitter region) is also referred to as cathode sliver.
6(N+Emitter region) is semi-buried in 5 (P)+Base region) top, 7 (anode A) is connected to 1 (P)+Transparent emitting anode) bottom; 8 and 10 (gate G) are connected at 5 (P)+Base region) and not 6 (N)+Emitter region) top of coverage; 9 (cathode K) is connected to 6 (N)+Emitter region) top. 11 is J1Node 12 is J2Node 13 is J3And (6) knotting.
Typically, a GCT chip typically contains a plurality of basic GCT cells. In the top view of the GCT cathode plane, a plurality of strip cathodes (usually called cathode bars) are arranged in a radial manner, and each strip cathode corresponds to one basic GCT unit. Dividing the cathode surface into a plurality of equal parts on the GCT cathode surface by taking the circle center as an axis, wherein each equal part is a sector; drawing a plurality of concentric circles on the cathode surface according to the length and the number of the comb strips; the comb strips in the sector are distributed along an arc, and the directions of the comb strips are parallel to the central line of the sector; the sector boundary area is increased by a single sliver according to the area size.
The description herein is primarily directed to a single GCT cell structure to illustrate the GCT chip structure of embodiments of the present invention.
As shown in fig. 2 or fig. 3, in an embodiment of the present invention, the vertical direction of the layered structure of the thyristor is P sequentially from bottom to top+Transparent emitting anode, N' buffer layer, N-Base region, P+Base region and semi-buried in P+N at the top of the base region+An emitter region, wherein:
N+emission area coverage P+A portion of the base tip;
gate G at P+Base region top N+On the part not covered by the emitting area;
cathode K is located at N+The top of the emitting region;
anode is located at P+And the bottom of the transparent emitting anode.
P+The base region is divided into two parts including P arranged horizontally1 +Short base region and P2 +Short base region, wherein P1 +The short base region is located right below the gate electrode G, P2 +The short base region is located at N+Directly below the emission area. Further, P2 +The doping concentration of the short base region is higher than P1 +The doping concentration of the short base region. FIG. 4 is P+The base region doping concentration distribution diagram, the abscissa depth and the ordinate are doping concentrations. As shown in fig. 4, B-B (P) in fig. 2 or 32 +Short base region) has a higher doping concentration than C-C (P) in fig. 2 or 31 +Short base region).
The advantages of the GCT structure in one embodiment of the present invention are illustrated by comparing the related parameters of the standard GCT structure in the prior art with those of the GCT structure in one embodiment of the present invention under different states.
(a) Current density distribution under cathode sliver
Comparing the current density under the same condition under the comb of the standard GCT structure in the prior art and the GCT structure in one embodiment of the present invention at the position shown by the tangent line A-A in FIG. 1, as shown in FIG. 5, line ◇ represents the standard GCT structure, line × represents the GCT structure in one embodiment of the present invention, the abscissa is the position change in the transverse direction (tangent line A-A) and the ordinate is the current density2 +The doping concentration of the short base region is high, providing a large number of holes where electrons recombine with the holes reducing the amount of electron injection into the P and N base regions, which results in a lower current density under the cathode comb. This is advantageous for increasing the GCT off current, as is known from the GCT dynamic avalanche breakdown mechanism.
(b) Shutdown waveform
Comparing the turn-off waveform under the same condition under the comb of the standard GCT structure in the prior art and the GCT structure in the embodiment of the present invention, as shown in FIG. 6, line ◇ represents the standard GCT structure, line × represents the GCT structure in the embodiment of the present invention, the abscissa is time, and the ordinate is voltage/current2All excess carriers in the junction are extracted more efficiently, so that a depletion layer is formed earlier to establish the rising anode voltage. This is due to two reasons: firstly, the density of current carriers below the GCT cathode comb strip is less, and on the other hand, the density of current carriers is less due to P below the GCT cathode comb strip2 +The high doping concentration of the base region can also form a transverse electric field, so that hole carriers in the P base region can be extracted to the gate electrode.
(c) Trigger and on characteristics
The GCT trigger current is mainly determined by P according to the characteristics of the thyristor+Lateral resistance R of the base regionG. Lower part P of GCT gate electrode1 +Base region (resistance R)G1) The doping concentration is kept basically constant and P is arranged below the cathode comb strip2 +Base region (resistance R)G2) High concentration of doping, resulting in RG2Much less than RG1Therefore, the GCT trigger characteristics are not substantially deteriorated.
In general, P+The smaller base concentration is more favorable for reducing the GCT on-state voltage drop, which is caused by J3Injection efficiency of emitter junction with P+FIG. 7 is a comparison of the on-state pressure drop at 4000A @ ambient temperature for GCT of one embodiment of the present invention compared to a standard GCT, with line ◇ representing the standard GCT structure (line ◇ corresponds to P in open outline)+Base region concentration 1E17, solid ◇ lines corresponding to P+Base region concentration 1E18), line × represents a GCT structure (corresponding to P) in one embodiment of the present invention1 +Base region concentration 1E17, P2 +Base concentration 1E18) with on-state current on the abscissa and on-state voltage drop on the ordinate. As shown in fig. 7, the lower part P of the cathode sliver is increased2 +The base region doping concentration, the on-state voltage drop of which is slightly increased by about 0.1V, if increased, improves the whole P base region doping concentration, and the on-state anode amplification is larger than or equal to the region doping concentration (solid ◇ line)+The doping concentration of the base region is designed in a partitioning mode, and the turn-off capability, the on-state voltage drop and the trigger characteristic of the GCT can be considered.
In summary, for the standard GCT chip, the turn-off current capability of the GCT chip is improved along with the increase of the doping concentration of the P base region within a certain range, but the turn-off current capability is not beneficial to reducing the trigger current and the on-state voltage drop. On the other hand, according to a dynamic avalanche damage mechanism, the carrier concentration accumulation under the cathode comb strip is too much when the GCT is turned off, and according to the heat effect and the resistance negative temperature characteristic, the carrier aggregation is easily caused, and finally the breakdown is caused to cause the turn-off failure. According to the GCT structure and the electrical characteristic relation of the GCT structure in the prior art, the novel GCT chip structure provided by the invention can keep the advantages of low GCT on-state voltage drop and low trigger current, and can reduce the current density below the cathode comb strip, so that the GCT turn-off current is improved.
Furthermore, one of the key points of the thyristor structure of the invention is P2 +The doping concentration of the short base region is higher than P1 +The doping concentration of the short base region. Specifically, in one embodiment of the present invention, P1 +The doping concentration of the short base region is 1E 15-1E 18cm-3，P2 +The doping concentration of the short base region is 1E 15-8E 18cm-3。
Further, P1 +Short base region and the P2 +Diffusion depth of short base region (N in FIG. 2 or FIG. 3)+The distance from the emitter junction surface to the dotted line) is 40-80 μm.
Further, in order to control P2 +Short base region and P1 +The doping concentration of the short base region, in one embodiment, is controlled by the P-type impurity implantation dosage1 +Short base region and P2 +And the doping concentration of the short base region is large. In particular, P1 +Short base region and P2 +The short base region is formed by ion implantation and then high-temperature diffusion propulsion.
Further, in an embodiment of the present invention, P1 +Short base region and P2 +The diffusion coefficient of the P-type impurity of the short base region is slower than that of the P-type impurity of the P base region. In particular, P1 +Short base region and P2 +The P-type impurity of the short base region is boron (B) impurity, and the P-type impurity of the P base region is aluminum (Al) or gallium (Ga) impurity.
Furthermore, in an embodiment of the invention, the doping concentration of the P base region is 5E 14-2E 16cm-3The P base region junction depth is advanced to time control by ion aluminum injection or closed aluminum diffusionAnd (5) preparing.
In the GCT structure of the present invention, P2 +The short base region is located at N+Directly below the emission area. In one embodiment, P2 +The boundary of the short base region may exceed N+The boundary of the emission area, P as shown in FIG. 82 +The width of the short base region in the transverse direction is larger than N+The width of the emitting region in the lateral direction, i.e. P2 +The coverage of the short base region can exceed N+Coverage of the emission area, wherein the dotted part represents P2 +Coverage of the short base region, the solid line portion representing N+The coverage of the transmission area.
Further, in another embodiment, P2 +The boundary of the short base region can be located at N+Inside the boundary of the emission area, P as shown in FIG. 92 +The width of the short base region in the transverse direction is less than N+Width in the lateral direction of the emitting area. In a direction looking down on the thyristor from directly above, i.e. P2 +The coverage of the short base region can be positioned at N+Within the coverage of the emitter region, wherein the dotted part represents P2 +Coverage of the short base region, the solid line portion representing N+The coverage of the transmission area.
It should be noted that when P is used2 +When the boundary position of the short base region exceeds the cathode comb strip, e.g. P2 +Too wide a design of the short base region will affect the trigger and on-state characteristics. When P is present2 +When the boundary position of the short base region is located within the cathode comb, e.g. P2 +Too narrow a short base region design will reduce P2 +The short base region also acts to increase process difficulty. Thus, in one embodiment of the present invention, P is determined based on specific process constraints and GCT performance requirements2 +The width of the short base region. Specifically, in an embodiment of the present invention, P is a direction in which the thyristor is viewed from the top, in a plan view from the top2 +The transverse range y of the coverage area of the short base region is more than or equal to 50 mu m and less than or equal to 6mm, and P2 +The longitudinal extent x of the footprint of the short base region is 10μm≤x≤500μm。
Further, in the prior art, the cathode bars of the chips are uniformly arranged in a wafer (as shown in fig. 10) by sector arcs or circumferences when viewed from the transverse direction of the GCT chips. For GCT tube cores with different diameters, the cathode comb strips are generally radially arranged according to 2-16 circles.
The GCT gate pole leading-out position is mainly divided into three conditions according to the magnitude of the GCT turn-off current.
(a) A central gate: the gate pole is arranged at the center of the chip and is circular. The contact area is small (about 0.5 cm)2) The gate pole mechanical structure is simple and is more suitable for devices with low current capacity. Fig. 9 shows a central gate arrangement.
(b) A ring-shaped gate: the gate pole is arranged in the middle of the chip and is in a ring shape. The contact area is medium (about 2.5 cm)2) The gate mechanical structure is complex and is suitable for high-end devices in current capacity.
(c) Edge gate: the gate pole is arranged at the edge of the chip and is in a ring shape. The contact area is large (about 5 cm)2) The gate mechanical structure is complex, and the structure is commonly used in a large-size reverse-conducting GCT structure.
For the gate structure of the GCT, because the gate impedances of the GCT chip near the gate lead-out region and far from the gate lead-out region are slightly different, a slight time deviation exists between different GCT units in the turn-off signal of the GCT chip, so that the current redistribution is caused, the current aggregation phenomenon (the current distribution far from the gate lead-out region is dense) is generated in the far from gate lead-out region, and finally the GCT chip is frequently failed in the far from gate lead-out region.
In the GCT structure of the invention, P is introduced2 +The existence of the short base region and the width design thereof can adjust the turn-off current density of the cathode comb strip. Thus, in one embodiment, P is designed under the cathode bars at different positions in the GCT wafer2 +The short base region width avoids current crowding in the region leading away from the gate of the GCT during turn-off. In particular, P under the cathode sliver remote from the GCT gate lead-out2 +The short base region is designed to be wider in width to reduce on-state current density and increase turn-off speed, and P is arranged below the cathode comb strip near the GCT gate leading-out part2 +The short base region is designed to be narrower in width so as to increase the on-state current density and slow down the turn-off speed, so that the turn-off uniformity of the chip is achieved, and the turn-off current capability of the GCT chip is improved.
FIG. 11 shows a top view of a GCT comprising a plurality of N at different positions+Emitting areas (solid oval), each N+A P is arranged right below the emitting area2 +A short base region (dotted oval), wherein P is the distance from the gate leading-out portion of the thyristor in the order from the near to the far in the direction of looking down the thyristor from the right above2 +The footprint (area of the dashed ellipse) of the short base region gradually increases.
FIG. 12 is a cross-sectional view of the GCT, with the distance from left to right in the transverse direction to the gate lead-out portion of the thyristor gradually increasing, P2 +The width of the short base region also gradually increases.
The following describes in detail the detailed parameters of the GCT structured according to the embodiment of the present invention by specific application examples.
Taking the 4 inch 4500V GCT design as an example, according to one embodiment of the present invention, a standard 4 inch 4500VGCT P is used+The base region is divided into 2 parts, P is arranged below the cathode comb strip2 +The doping concentration of the base region is higher. In addition, P below cathode comb strips with different turns2 +The base region width is designed differently to achieve the purpose of uniform GCT turn-off. The 4-inch GCT cathode comb strip is marked as No.1, No.2, … and No.10 circles from the center to the outer circle of the tube core. The 4-inch asymmetric GCT structural design parameters are defined as shown in figure 13.
Doping concentration N of GCT P base regionPIs 1E15cm-3～5E15cm-3Depth of junction XjP110μm～130μm。
GCT P1 +Base region doping concentration NP1+Is 1E17cm-3～5E17cm-3，P2 +Base region doping concentration NP2+Is 1E18cm-3～5E18cm-3Depth of junction XjP+55μm～65μm。
When the middle ring gate position design of the 4-inch asymmetric GCT is positioned between the 5 th and the 6 th cathode comb strips, P in each cathode comb strip is2 +The base width x is designed as shown in table 1.
TABLE 1
| Number of cathode comb strips | P2 +Base region width X (mum) | Number of cathode comb strips | P2 +Base region width x (mum) |
| No.1 | 80 | No.6 | 40 |
| No.2 | 40 | No.7 | 40 |
| No.3 | 40 | No.8 | 80 |
| No.4 | 40 | No.9 | 120 |
| No.5 | 40 | No.10 | 120 |
When the middle ring-shaped gate position design of the 4-inch reverse-conducting GCT is positioned between the middle FRD and the 1 st cathode comb strip, P in each cathode comb strip is2 +The base width x is designed as shown in table 2 or table 3.
TABLE 2
| Number of cathode comb strips | P2 +Base region width x (mum) |
| No.1 | 40 |
| No.2 | 40 |
| No.3 | 40 |
| No.4 | 80 |
| No.5 | 120 |
TABLE 3
| Number of cathode comb strips | P2 +Base region width x (mum) |
| No.1 | 20 |
| No.2 | 40 |
| No.3 | 60 |
| No.4 | 80 |
| No.5 | 120 |
Furthermore, the invention also provides a method for preparing the thyristor structured according to the embodiment of the invention. Taking the forming process of a basic GCT unit of GCT as an example, in an embodiment of the present invention, the specific implementation steps are as follows:
1)N-type monocrystalline silicon substrate preparation
First, an N-type doped monocrystalline silicon substrate (as shown in fig. 14) is prepared, and the doping concentration and the sheet thickness of the substrate are selected according to the parameter requirements of GCT blocking voltage, on-state voltage drop, and the like.
2) Manufacture of formation P+Base region
P formation by implantation diffusion fabrication+Base regions, wherein each corresponds to P1 +And P2 +The doping concentration of the short base region is selectively implanted on the front surface of the monocrystalline silicon substrate for two times, or the doping concentration of the short base region is firstly selectively implanted on the front surface of the monocrystalline silicon substrate corresponding to P1 +The doping concentration of the short base region is subjected to whole-surface implantation, and then the front surface of the monocrystalline silicon substrate corresponds to P2 +The implantation window of the short base region corresponds to P2 +Short base region and P1 +And injecting the doping concentration difference of the short base region.
Specifically, in the present embodiment, P of GCT+The base region is formed by boron B implantation diffusion manufacturing, and comprises two schemes:
①P1 +and P2 +The short base region is formed by performing selective implantation diffusion on the front surface of the monocrystalline silicon substrate twice. First form P1 +Base region selective implantation of window, implantation of doped impurity B+Implant dose EB1According to P1 +The doping concentration of the base region depends (as shown in fig. 15). Then P per revolution according to GCT2 +Designing the width of the base region to form an injection window with corresponding size, and injecting the doping impurity B again+This implantation dose EB2According to P2 +The doping concentration of the base region depends (as shown in fig. 16). Finally, high-temperature diffusion is carried out simultaneously to lead P to+The base boron junction depth is controlled to be within the design range (as shown in fig. 17).
②P2 +Short base region is in P1 +And performing 1 selective implantation diffusion formation in the short base region. Firstly, the whole surface implantation is carried out on the front surface of a monocrystalline silicon substrate, the doping impurities are implanted into the monocrystalline silicon substrate to be B +, and the dosage is EB1According to P1 +The doping concentration of the short base region depends (as shown in fig. 18). Then P per revolution according to GCT2 +Designing the width of the short base region to form an injection window with corresponding size, and injecting the doping impurity B again+The dose of this implantation should be △ EB＝EB2-EB1Wherein the dose EB2According to P2 +The doping concentration of the short base region depends (as shown in fig. 19). Finally, high-temperature diffusion is carried out simultaneously to lead P to+The base boron junction depth is controlled to be within the design range (as shown in fig. 20).
3) P base region formation
As shown in fig. 21 and 22, the P base region is formed first (as shown in fig. 21), and then the back P-type doped layer is removed (as shown in fig. 22). Specifically, in this embodiment, the P-base region is formed by an aluminum injection diffusion or closed-tube aluminum diffusion process, and the two process schemes are as follows:
a) and (3) aluminum injection diffusion process: firstly, the whole surface of the front surface of a monocrystalline silicon substrate is injected, and the injected doping impurity is Al+Implant dose EAlDepending on the doping concentration of the P-base region. Depositing a layer of Si by LPCVD process3N4And (4) carrying out high-temperature propulsion on the film in a nitrogen atmosphere, and controlling the Al junction depth of the P base region within a design range. And then the P-type doped layer on the back side is removed by etching or single-side polishing.
b) Closed tube aluminum expansion: and (3) carrying out high-temperature propulsion for a certain time t in the saturated aluminum atmosphere of the vacuum furnace tube, controlling the time t according to the Al junction depth design value of the P base region, and then removing the P type doping layer on the back by corrosion or single-side grinding.
The two processes have advantages and disadvantages respectively: the chip formed by the aluminum injection diffusion process has better surface quality and utilizes the formation of a subsequent cathode comb strip structure. The closed pipe aluminum expanding process is simple, and the batch production cost is low.
4) Formation of N' buffer layer
The N' buffer layer is implanted into the back of the monocrystalline silicon substrate and doped with phosphorus (P)+) Implant dose EP+Depending on the doping concentration of the N 'buffer layer, then advanced in a high temperature diffusion furnace to control the N' buffer layer junction depth within the design range (as shown in fig. 23).
5)N+Formation of the emitter region (cathode sliver)
Performing N on the front surface of a monocrystalline silicon substrate+Diffusion of phosphorus according to N+The doping concentration and the junction depth of the sliver structure determine the flow rate and the diffusion time of a doping gas source in a phosphorus diffusion furnace, and N is converted into N+The structure of the cathode comb strip layer is controlled within a design range. Selective etching is then performed on the cathode comb strip layer to form a GCT cathode comb strip structure (as shown in fig. 24).
6) Transparent anode P+Form a
Transparent anode P+The layer is implanted into the back of the monocrystalline silicon substrate at the whole surface, the doping impurity is boron (B), and the implantation dosage is EAPAccording to the transparent anode P+The doping concentration of the layer is determined, and then the transparent anode P is pushed in a high-temperature diffusion furnace+The layer junction depth is controlled within the design range (as shown in fig. 25).
Forming P by performing whole-surface implantation on the back surface of the single crystal silicon substrate+A transparent emissive anode;
7) metal electrode formation
After the gate cathode passivation isolation is formed, metal electrode layers are deposited on all surfaces of the tube core, and after etching treatment, a GCT unit cell structure is formed (as shown in FIG. 26).
In summary, the invention provides a gate commutated thyristor. The invention independently designs the turn-off speed of the GCT unit and improves the turn-off uniformity. Compared with the prior art, the invention not only improves the GCT current turn-off capability, but also reduces the turn-off energy; and the GCT trigger current is reduced, and the advantage of low-pass voltage drop of the GCT is kept. Furthermore, the gate pole commutation thyristor structure is suitable for all types and sizes of GCT single cell designs, and particularly can adjust the turn-off uniformity on large-size GCT. The manufacturing method of the gate pole commutating thyristor is simple and is compatible with the prior process platform.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. There are various other embodiments of the method of the present invention. Various corresponding changes or modifications may be made by those skilled in the art without departing from the spirit of the invention, and these corresponding changes or modifications are intended to fall within the scope of the appended claims.
Claims (10)
1. A gate-commutated thyristor is characterized in that the vertical direction of the layered structure of the thyristor is sequentially P from bottom to top+Transparent emitting anode, N' buffer layer, N-Base region, P+Base region and semi-buried in P+N at the top of the base region+An emitter region, wherein:
said N is+The emission area covers the P+A portion of the base tip;
gate G is located at P+The base region top is N+On the part not covered by the emitting area;
cathode K is positioned at the N+The top of the emitting region;
the anode is positioned at the P+The bottom of the transparent emitting anode;
the P is+The base region comprises P horizontally arranged side by side1 +Short base region and P2 +Short base region, wherein the P1 +The short base region is positioned right below the gate electrode G, and P2 +The short base region is positioned at the N+Directly below the emission area, P1 +The doping concentration of the short base region is lower than that of the P2 +The doping concentration of the short base region.
2. The thyristor according to claim 1, wherein the P is1 +The doping concentration of the short base region is 1E 15-1E 18cm-3Said P is2 +The doping concentration of the short base region is 1E 15-8E 18cm-3。
3. The thyristor according to claim 1, wherein the P is1 +Short base region and the P2 +The diffusion depth of the short base region is 40-80 μm.
4. The thyristor according to claim 1, wherein the P is1 +Short base region and the P2 +The doping concentration of the short base region is controlled by the injection dosage of the P-type impurity, and the P is1 +Short base region and the P2 +The short base region is formed by ion implantation and then high-temperature diffusion propulsion.
5. The thyristor according to claim 1, wherein the doping concentration of the P base region is 5E 14-2E 16cm-3。
6. The thyristor according to claim 1, wherein the P is1 +Short base region and the P2 +The diffusion coefficient of the P-type impurity of the short base region is slower than that of the P-type impurity of the P base region.
7. The thyristor according to claim 6, wherein P is1 +Short base region and the P2 +The P-type impurity of the short base region is boron, and the P-type impurity of the P base region is aluminum or gallium.
8. A thyristor according to any one of claims 1 to 7, wherein the P is in a direction looking down the thyristor from directly above2 +The transverse range y of the coverage area of the short base region is more than or equal to 50 mu m and less than or equal to 6mm, and P2 +The longitudinal range x of the coverage area of the short base region is more than or equal to 10 mu m and less than or equal to 500 mu m.
9. The thyristor according to any one of claims 1-7, wherein a wafer of the thyristor comprises a plurality of N at different positions+Emitting areas of each N+One P is corresponding to the right lower part of the emission area2 +A short base region, wherein, in the direction of overlooking the thyristor from the right top, the P is arranged from the near to the far in sequence from the leading-out part of the gate pole of the thyristor2 +The coverage area of the short base region gradually increases.
10. A method of making a thyristor according to any one of claims 1-9, the method comprising:
preparation of N-A type single crystal silicon substrate;
p formation by implantation diffusion fabrication+Base regions, wherein, respectivelyShould P1 +And P2 +Selectively implanting the doping concentration of the short base region on the front surface of the monocrystalline silicon substrate twice, or firstly, correspondingly implanting P on the front surface of the monocrystalline silicon substrate1 +The doping concentration of the short base region is subjected to whole-surface implantation, and then the front surface of the monocrystalline silicon substrate corresponds to P2 +The implantation window of the short base region corresponds to P2 +Short base region and P1 +Injecting the doping concentration difference of the short base region;
manufacturing and forming a P base region by adopting an aluminum injection diffusion or closed tube aluminum expansion process;
performing whole-surface injection manufacturing on the back surface of the monocrystalline silicon substrate to form an N' buffer layer;
forming N on the front surface of monocrystalline silicon substrate+An emission region;
forming P by performing whole-surface implantation on the back surface of the single crystal silicon substrate+A transparent emissive anode;
forming a metal electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611205266.5A CN108242465B (en) | 2016-12-23 | 2016-12-23 | Gate electrode current conversion thyristor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611205266.5A CN108242465B (en) | 2016-12-23 | 2016-12-23 | Gate electrode current conversion thyristor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108242465A CN108242465A (en) | 2018-07-03 |
| CN108242465B true CN108242465B (en) | 2020-07-03 |
Family
ID=62704147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611205266.5A Active CN108242465B (en) | 2016-12-23 | 2016-12-23 | Gate electrode current conversion thyristor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108242465B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899358A (en) * | 2018-07-11 | 2018-11-27 | 北京优捷敏半导体技术有限公司 | A kind of gate level turn-off thyristor and its manufacturing method |
| CN109326640A (en) * | 2018-10-25 | 2019-02-12 | 深圳市鹏朗贸易有限责任公司 | A kind of door pole stream-exchanging thyristor and its manufacturing method |
| CN109449204B (en) * | 2018-10-30 | 2021-12-07 | 上海领矽半导体有限公司 | Thyristor and preparation method thereof |
| CN110364569B (en) * | 2019-06-10 | 2022-11-22 | 西安理工大学 | Trench gate MOS-GCT structure and preparation method thereof |
| CN111933704B (en) * | 2020-06-22 | 2022-09-09 | 株洲中车时代半导体有限公司 | Cell structure of gate commutated thyristor, preparation method and gate commutated thyristor |
| CN111739929B (en) * | 2020-06-30 | 2022-03-08 | 电子科技大学 | MOS grid-controlled thyristor reinforced by displacement radiation resistance |
| EP4053915B1 (en) * | 2021-03-02 | 2024-06-19 | Hitachi Energy Ltd | Gate-commuted thyristor cell with a base region having a varying thickness |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1045139C (en) * | 1996-04-23 | 1999-09-15 | 西安电子科技大学 | Grid-controlled transistor |
| CN105590959B (en) * | 2015-12-17 | 2018-05-29 | 清华大学 | Door pole stream-exchanging thyristor with double p bases door cathode constructions and preparation method thereof |
| US20190288096A1 (en) * | 2018-02-15 | 2019-09-19 | Silicon Power Corporation | 4-layer devices with improved reverse current action capability |
-
2016
- 2016-12-23 CN CN201611205266.5A patent/CN108242465B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN108242465A (en) | 2018-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108242465B (en) | Gate electrode current conversion thyristor and preparation method thereof | |
| US7932583B2 (en) | Reduced free-charge carrier lifetime device | |
| JP6139312B2 (en) | Semiconductor device | |
| CN113838916B (en) | Separation gate CSTBT with PMOS current clamping function and manufacturing method thereof | |
| CN113571415B (en) | IGBT device and manufacturing method thereof | |
| CN110504307B (en) | SA-LIGBT device with grid-controlled collector | |
| CN111933705B (en) | Manufacturing method of power semiconductor device and power semiconductor device | |
| CN110137250B (en) | High-speed IGBT device with ultralow conduction voltage drop | |
| CN111834451B (en) | Reverse-resistance type gate pole commutation thyristor and manufacturing method thereof | |
| CN110610858B (en) | Gate electrode current conversion thyristor and manufacturing method thereof | |
| CN110610986A (en) | RC-IGBT device integrating transverse freewheeling diode by using junction terminal | |
| CN108155230B (en) | Transverse RC-IGBT device and preparation method thereof | |
| CN113964180A (en) | Super-junction IGBT device with low loss performance and preparation method thereof | |
| CN116435353A (en) | Reverse conducting insulated gate bipolar transistor structure and preparation method thereof | |
| CN117219665A (en) | Gate commutated thyristor chip and thyristor | |
| CN116759424A (en) | Self-aligned trench type silicon carbide hybrid diode structure and preparation method thereof | |
| WO2014086075A1 (en) | Igbt structure and manufacturing method thereof | |
| CN113097287A (en) | IGBT chip terminal structure and manufacturing method thereof | |
| CN107564959B (en) | MOS grid-controlled thyristor and manufacturing method thereof | |
| US20150102361A1 (en) | Semiconductor devices in sic using vias through n-type substrate for backside contact to p-type layer | |
| JP3885616B2 (en) | Semiconductor device | |
| WO2013179761A1 (en) | Semiconductor device | |
| CN113643968A (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN112736134A (en) | Silicon carbide PNPN thyristor injection type IGBT device | |
| CN113809167B (en) | BRT with buried layer and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200930 Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee after: Zhuzhou CRRC times Semiconductor Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. |
|
| TR01 | Transfer of patent right |