CN111933704B - Cell structure of gate commutated thyristor, preparation method and gate commutated thyristor - Google Patents
Cell structure of gate commutated thyristor, preparation method and gate commutated thyristor Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7424—Thyristor-type devices, e.g. having four-zone regenerative action having a built-in localised breakdown/breakover region, e.g. self-protected against destructive spontaneous, e.g. voltage breakover, firing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
- H01L29/66393—Lateral or planar thyristors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7436—Lateral thyristors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
Abstract
The invention provides a cell structure of a gate commutated thyristor, a preparation method and the gate commutated thyristor, wherein the cell structure comprises two sides of the cell structure, and a lateral groove is arranged downwards on the surface of a substrate so as to form a boss at the center of the cell structure on the surface of the substrate; the second conductive type short base region is positioned below the side groove and the boss; the bottom of the short base region is provided with a bulge at a position corresponding to the boss; the first base region of the second conduction type is positioned above the short base region; a second conductive type second base region positioned below the short base region; the bottom of the second base region is provided with a bulge at a position corresponding to the boss; a first conductive type emitter region located within the first base region surface; and the doping concentration of the short base region is higher than that of the first base region and that of the second base region. The driving control voltage value can be improved, so that the commutation speed is improved, and the turn-off capability of the GCT chip is improved.
Description
Technical Field
The disclosure relates to the technical field of semiconductor devices, in particular to a cell structure of a gate commutated thyristor, a preparation method of the cell structure and the gate commutated thyristor.
Background
A Gate Commutated Thyristor (GCT) is a semiconductor device with a fully-controlled current and high power capacity in the field of power electronics, and has the characteristics of low on-state loss and turn-off characteristics like a thyristor, thus having the characteristics of low on-state loss, large surge current, high turn-off speed, large power capacity and the like. The GCT is generally used in some electric power devices with ultra-large power capacity, such as a metallurgical rolling mill transmission system, a ship driving system, a power grid energy quality control device and other heavy work core equipment.
The main structure of the conventional GCT chip in the longitudinal direction comprises four PNPN layers, as shown in FIG. 1, 3 PN junctions exist in the device, and J is respectively arranged from an anode 107 to a cathode 109 1 Junction (anode transparent junction), J 2 Junction (main junction of blocking voltage) and J 3 Junction (gate cathode junction). The emission areas 104 (cathode bars) of the chip cathodes are uniformly arranged in a wafer in sector arcs or circles when viewed from the transverse direction of the GCT chip. For GCT die of different diameters, the cathode combs are typically arranged in concentric circles. Depending on the magnitude of the GCT off current, the GCT gate 108 exit is arranged at the center of the wafer, referred to as the center gate, or at the center or periphery of the wafer, referred to as the middle ring gate or the edge ring gate. For the conventional GCT chip, the speed of extracting the current carrier below the cathode comb strip to the gate pole is slow in the turn-off process, and particularly, the current filament phenomenon is easily generated at the cathode comb strip far away from the gate pole, so that the turn-off failure of the GCT comb strip due to re-triggering is caused, the GCT turn-off current density is low, and the turn-off capability is poor.
Disclosure of Invention
In view of the above problems, the present disclosure provides a cell structure of a gate commutated thyristor, a method for manufacturing the cell structure, and a gate commutated thyristor, which solve the technical problems of low turn-off current density and poor turn-off capability of the gate commutated thyristor in the prior art.
In a first aspect, the present disclosure provides a cell structure of a gate-commutated thyristor, including:
a first conductive type substrate; side grooves are arranged on two sides of the cellular structure and downwards on the surface of the substrate, so that bosses are formed on the surface of the substrate at the center of the cellular structure;
a second conductivity type short base region disposed in the substrate and located below the side trench and the boss; the bottom of the short base region is provided with a bulge at a position corresponding to the boss;
the second conductive type first base region is arranged in the boss and is positioned above the short base region;
a second conductive type second base region which is arranged in the substrate and is positioned below the short base region; the bottom of the second base region is provided with a bulge at a position corresponding to the boss;
a first conductive type emitter region located in the first base region surface and covering the mesa surface;
and the doping concentration of the short base region is higher than that of the first base region and that of the second base region.
According to an embodiment of the present disclosure, preferably, the depth of the side groove is 30 to 50 μm.
According to an embodiment of the present disclosure, preferably,
the doping concentration of the first base region is 1E 15-1E 16cm -3 ；
The doping concentration of the short base region is 1E 15-5E 18cm -3 ；
The doping concentration of the second base region is 1E 13-1E 16cm -3 。
According to an embodiment of the present disclosure, preferably, the cellular structure further includes:
a first conductive type buffer layer under the substrate;
a second conductive type anode region located under the buffer layer;
the anode metal layer is positioned below the anode region and is electrically connected with the anode region;
the gate metal layer is positioned at the bottom of the side groove and electrically connected with the short base region;
and a cathode metal layer located over the boss and electrically connected to the emitter region.
In a second aspect, the present disclosure provides a method for preparing a cell structure of a gate-commutated thyristor, including:
providing a first conductive type substrate;
forming lateral grooves on the two sides of the cellular structure on the surface of the substrate so as to form bosses on the central position of the cellular structure on the surface of the substrate;
injecting first high-energy ions of a second conduction type into the substrate below the side grooves in an oblique ion injection mode, and performing a high-temperature diffusion process to form short base regions of the second conduction type below the side grooves and the bosses in the substrate; the bottom of the short base region is provided with a bulge at a position corresponding to the boss;
injecting second high-energy ions of a second conductive type above the substrate and performing a high-temperature diffusion process to form a first base region of the second conductive type above the short base region in the boss and diffuse the second high-energy ions to the lower part of the short base region to form a second base region of the second conductive type below the short base region; the bottom of the second base region is provided with a bulge at a position corresponding to the boss, and the doping concentration of the short base region is higher than that of the first base region and that of the second base region;
and selectively performing high-temperature diffusion of first conductive type ions in the first base region to form a first conductive type emitter region covering the surface of the boss in the surface of the first base region.
According to an embodiment of the present disclosure, preferably, a diffusion coefficient of the first energetic ion is smaller than a diffusion coefficient of the second energetic ion.
According to the embodiment of the present disclosure, preferably, before the step of selectively performing high-temperature diffusion of the first conductivity type ions in the first base region to form the first conductivity type emitter region covering the surface of the boss in the surface of the first base region, the method further includes the following steps:
and implanting first conductivity type high-energy ions below the substrate to form a first conductivity type buffer layer below the substrate.
According to the embodiment of the present disclosure, preferably, after the step of selectively performing high-temperature diffusion of the first conductivity type ions in the first base region to form the first conductivity type emitter region covering the surface of the boss in the surface of the first base region, the method further includes the following steps:
implanting the first or second high energy ions under the buffer layer to form a second conductivity type anode region under the buffer layer;
forming an anode metal layer electrically connected with the anode region below the anode region;
forming a cathode metal layer electrically connected with the emission region over the boss;
and forming a gate metal layer electrically connected with the short base region at the bottom of the side groove.
In a third aspect, the present disclosure provides a gate commutated thyristor comprising a plurality of cell structures of the gate commutated thyristor according to any one of the first aspects.
By adopting the technical scheme, the following technical effects can be at least achieved:
(1) the first base region is introduced below the emitter region (cathode comb strip) in the substrate boss, so that the voltage between the gate and the cathode is increased by more than 50%, and further the drive control voltage value can be improved, thereby improving the commutation speed and increasing the turn-off capability of the GCT.
(2) A lateral groove structure is adopted, and protrusions are formed at the bottoms of the short base region and the second base region to form a transverse PN junction, so that the longitudinal commutation path of the GCT is shortened, and the turn-off speed and the turn-off capability of the GCT are improved.
(3) A short base region with high doping concentration is formed between the first base region and the second base region, so that GCT false triggering is prevented, and the turn-off current density and turn-off capability of the GCT are improved.
(4) The preparation process flow is optimized, and the second base region with the bulge at the bottom is formed in the cellular structure at one time by combining the lateral groove structure, so that the second base region is corrugated in the overall structure of the GCT, the preparation process of the GCT with high turn-off current density is simplified, and the production cost of a chip is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 is a schematic cross-sectional view of a cell structure of a conventional gate commutated thyristor;
fig. 2 is a schematic cross-sectional structure diagram illustrating a cell structure of a gate commutated thyristor according to an exemplary embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating a longitudinal (a to a') distribution of doping concentrations of regions in a cell structure of a gate commutated thyristor according to an exemplary embodiment of the present disclosure;
fig. 4 is a flowchart illustrating a method for manufacturing a cell structure of a gate-commutated thyristor according to an exemplary embodiment of the present disclosure;
fig. 5 to 12 are schematic cross-sectional structures formed by relevant steps of a method for manufacturing a cell structure of a gate-commutated thyristor according to an exemplary embodiment of the present disclosure.
Detailed Description
The following detailed description will be given with reference to the accompanying drawings and examples to explain how to apply technical means to solve the technical problems and to achieve the technical effects. The embodiments and various features in the embodiments of the present disclosure may be combined with each other on the premise of no conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The following detailed description of the preferred embodiments of the disclosure, however, the disclosure can be practiced otherwise than as specifically described.
Example one
As shown in fig. 2, a cell structure 200 of a gate commutated thyristor according to an embodiment of the present disclosure includes a substrate 201, a short base region 202, a first base region 203, a second base region 204, a buffer layer 205, an emitter region 206, an anode region 207, an anode metal layer 208, a gate metal layer 209, and a cathode metal layer 210.
Illustratively, the substrate 201 is a single crystal silicon substrate of the first conductivity type, and the doping concentration and the sheet thickness of the substrate 201 are selected according to the parameter requirements of the GCT blocking voltage, the on-state voltage drop, and the like. Side grooves (not shown) are formed on both sides of the cell structure 200 and downward on the surface of the substrate 201, so as to form a boss (not shown) on the surface of the substrate 201 at the center of the cell structure 200. The depth of the side grooves is 30 to 50 μm. The formation of the side groove enables the height difference between the gate and the cathode to be higher than that of the conventional one by more than 60%, shortens the longitudinal commutation path of the GCT and is also beneficial to improving the turn-off speed and the turn-off capability.
The short base region 202 is a heavily doped base region of the second conductivity type, and the short base region 202 is disposed in the substrate 201 and below the side trench and the boss. And the bottom of the short base region 202 is provided with a bulge at the position corresponding to the boss. The doping concentration of the short base region 202 is higher than that of the first base region 203 and the second base region 204, and the doping concentration of the short base region 202 is higher than that of the first base region 203 and the second base region 204The impurity concentration is 1E 15-5E 18cm -3 The diffusion depth is determined by the device characteristics trade-off and is usually controlled to 50 to 100 μm. The formation of the heavily doped short base region 202 improves the turn-off capability of the chip.
The first base region 203 is a lightly doped base region of the second conductivity type, and the first base region 203 is disposed in the boss and above the short base region 202. The doping concentration of the first base region 203 is 1E15 to 1E16cm -3 。
The second base region 204 is a lightly doped base region of a second conductivity type, the second base region 204 is arranged in the substrate 201 and is located below the short base region 202, and a protrusion is arranged at a position, corresponding to the boss, at the bottom of the second base region 204, so that the second base region 204 in the overall structure of the GCT device formed by the cell structure 200 is corrugated, a transverse PN junction is formed to generate a transverse electric field, a longitudinal commutation path of the GCT is shortened, and the turn-off speed and the turn-off capability of the GCT are improved. The combination of the transverse electric field and the heavily doped short base region 202 enables the GCT to accelerate the extraction of carriers below the cathode comb strip in the turn-off process, prevents the GCT from being triggered by mistake, and improves the turn-off current density of the GCT. The advantages of low GCT on-state voltage drop and trigger current can be kept, and the GCT current turn-off capability can be improved. The doping concentration of the second base region 204 is 1E 13-1E 16cm -3 The depth is determined by the blocking voltage of the chip design, and is 110 to 200 μm.
The short base region 202 is formed by laterally diffusing impurity ions of a second conductive type with a small diffusion coefficient (slow diffusion), the first base region 203 and the second base region 204 are formed by diffusing impurity ions of the second conductive type with a large diffusion coefficient (fast diffusion), when the second conductive type is a P type, the impurity ions of the short base region 202 can be boron (B) impurities, the doping concentration is controlled by the injection dosage of the P type impurities, and the diffusion depth is controlled by the propulsion of a high-temperature diffusion process; the impurity ions of the first base region 203 and the second base region 204 may be aluminum (Al) impurities, and the junction depth is controlled by ion implantation of aluminum or aluminum diffusion and then high-temperature diffusion propulsion.
The buffer layer 205 is a buffer layer 205 of the first conductivity type and is disposed under the substrate 201, and the buffer layer 205 has a doping concentration of 1E 16-5E 16cm -3 Depth of view ofIs 30 to 60 μm. The buffer layer 205 is formed by diffusing impurity ions of a first conductivity type with a small diffusion coefficient (slow diffusion), when the first conductivity type is an N type, the impurity ions of the buffer layer 205 may be phosphorus (P) or arsenic (As) impurities, the doping concentration of the buffer layer 205 is controlled by the implantation dose of the N type impurities, and the diffusion depth is advanced and controlled by a high temperature diffusion process.
The emitter region 206 is an emitter region 206 of the first conductivity type, and is located in the surface of the first base region 203 and covers the surface of the mesa, i.e., the surface of the emitter region 206 is flush with the surface of the mesa. The doping concentration of the emitter region 206 is about 1E19 to 1E21cm -3 And the depth is 15 to 25 μm. That is, the emitter region 206 and the first base region 203 are formed in the mesa, so that the voltage between the gate and the cathode can be increased by more than about 50%, and further, the driving control voltage value can be increased, thereby increasing the commutation speed and increasing the turn-off capability of the GCT.
An anode region 207 is an emitter region 206 of the second conductivity type, and is disposed under the buffer layer 205, wherein the doping concentration of the anode region 207 is 1E 19-1E 21cm -3 And a depth of 15 to 25 μm.
An anode metal layer 208 is located under the anode region 207 and forms an electrical connection with the anode region 207.
A cathode metal layer 210 is located over the mesa and makes electrical connection with emitter region 206.
The longitudinal distribution (a to a') of the doping concentrations of the emitter region 206, the first base region 203, the short base region 202, the second base region 204, and the substrate 201, as shown in fig. 3, it can be seen that the ion doping concentration of the emitter region 206 is the highest, and the doping concentration of the short base region 202 is higher than those of the upper and lower regions (the first base region 203 and the second base region 204) thereof.
In the present embodiment, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type. Specifically, the type of the device to be manufactured may be selected appropriately according to actual needs.
The present disclosure provides a cell structure 200 of a gate commutated thyristor, the cell structure 200 comprising a first conductivity type substrate 201; wherein, on both sides of the cellular structure 200, lateral grooves are arranged on the surface of the substrate 201 downwards to form a boss on the surface of the substrate 201 at the center of the cellular structure 200; a second conductivity type short base region 202 disposed in the substrate 201 and located below the side trench and the boss; wherein, the bottom of the short base region 202 is provided with a bulge at the position corresponding to the boss; a second conductive type first base region 203 arranged in the boss and positioned above the short base region 202; a second conductivity type second base region 204 disposed in the substrate 201 and located below the short base region 202; wherein, the bottom of the second base region 204 is provided with a bulge at the position corresponding to the boss; a first conductive type emitter region 206 located in the surface of the first base region 203 and covering the surface of the mesa; wherein the doping concentration of the short base region 202 is higher than that of the first base region 203 and the second base region 204. The driving control voltage value can be improved, so that the commutation speed is improved, the turn-off speed is improved, and the turn-off capability of a GCT chip is improved.
Example two
On the basis of the first embodiment, the present embodiment provides a method for manufacturing a cell structure 200 of a gate-commutated thyristor. Fig. 4 is a schematic flow chart of a method for manufacturing a cell structure 200 of a gate-commutated thyristor according to an embodiment of the present disclosure. Fig. 5-12 are schematic cross-sectional structure diagrams formed by relevant steps of a method for manufacturing a cell structure 200 of a gate-commutated thyristor according to an embodiment of the present disclosure. The detailed steps of an exemplary method for manufacturing the cell structure 200 of the gate-commutated thyristor according to the embodiment of the present disclosure will be described with reference to fig. 4 and fig. 5 to fig. 12.
As shown in fig. 4, the method for manufacturing the cell structure 200 of the gate commutated thyristor of the present embodiment includes the following steps:
step S101: as shown in fig. 5, a first conductive type substrate 201 is provided.
The substrate 201 is typically a Neutron Transmutation Dopin (NTD) single crystal silicon wafer.
Step S102: as shown in fig. 6, lateral grooves (not shown) are formed on both sides of the cell structure 200 on the surface of the substrate 201, so as to form a convex platform (not shown) on the surface of the substrate 201 at the center of the cell structure 200.
Specifically, an oxide layer shielding layer is formed by adopting a high-temperature oxidation process, and a selective etching pattern is formed by adopting a photoetching process. Then, a wet etching or dry etching process is used to selectively dig grooves to form lateral grooves on the surface of the substrate 201 at two sides of the cell structure 200, so as to form a boss on the surface of the substrate 201 at the center of the cell structure 200. The depth of the side grooves is 30 to 50 μm. The formation of the side groove enables the height difference between the gate and the cathode to be higher than that of the conventional one by more than 60%, shortens the longitudinal commutation path of the GCT and is also beneficial to improving the turn-off speed and the turn-off capability.
Step S103: as shown in fig. 7, by means of oblique ion implantation, second conductivity type first high-energy ions are implanted into the substrate 201 below the side trench, and a high-temperature diffusion process is performed to form a second conductivity type short base region 202 in the substrate 201 below the side trench and the boss; wherein, the bottom of the short base region 202 is provided with a bulge at the position corresponding to the lug boss.
Specifically, a photoetching process is adopted, photoresist is used for selectively shielding the upper part and the side wall of a boss, then ion implantation is adopted, first high-energy ions of a second conduction type are implanted obliquely, then high-temperature diffusion is carried out to form a high-concentration base region at the bottom of a side groove, and meanwhile, a local high-concentration base region is formed below the boss through transverse diffusion, so that a short base region 202 with a bulge at the bottom at a position corresponding to the boss is formed. The formation of the heavily doped short base region 202 improves the turn-off capability of the chip.
Step S104: as shown in fig. 8, second high-energy ions of a second conductivity type are implanted above the substrate 201 and a high-temperature diffusion process is performed to form a first base region 203 of the second conductivity type above the short base region 202 in the boss, and the second high-energy ions are diffused below the short base region 202 to form a second base region 204 of the second conductivity type below the short base region 202; the bottom of the second base region 204 is provided with a protrusion at a position corresponding to the boss, and the doping concentration of the short base region 202 is higher than that of the first base region 203 and the second base region 204.
Wherein the diffusion coefficient of the first energetic ions is smaller than the diffusion coefficient of the second energetic ions. When the second conductive type is a P-type, the first high energy ions may be boron (B) impurities, and the second high energy ions may be aluminum (Al) impurities. The first base region 203 and the second base region 204 are formed at the same time, when the second high-energy ions are aluminum ions, the first base region 203 and the second base region 204 can be formed by an aluminum injection diffusion or aluminum diffusion process, and the specific steps of the two schemes are as follows:
(a) and (3) aluminum injection diffusion process: first, the whole surface is implanted above the substrate 201, the implanted doping impurities are aluminum ions, and the implantation dosage is determined according to the required doping concentration. Depositing a layer of Si by Low Pressure Chemical Vapor Deposition (LPCVD) 3 N 4 And (3) performing high-temperature propulsion in a nitrogen atmosphere to control the junction depth (depth) of the second base region 204 within a design range, and simultaneously performing diffusion to form the first base region 203.
(b) Aluminum diffusion: and (3) performing high-temperature pre-deposition for a certain time in the aluminum saturated atmosphere of the vacuum furnace tube, and performing high-temperature propulsion according to the design value of the junction depth (depth) of the second base region 204 to simultaneously form the diffusion layers of the first base region 203 and the second base region 204.
The bottom of the second base region 204 is provided with a bulge at a position corresponding to the boss, so that the second base region 204 in the overall structure of the GCT device formed by the cell structure 200 is corrugated to form a transverse PN junction to generate a transverse electric field, the longitudinal commutation path of the GCT is shortened, and the GCT turn-off speed and turn-off capability are improved. The combination of the transverse electric field and the heavily doped short base region 202 enables the GCT to accelerate the extraction of current carriers below the cathode comb strip in the turn-off process, prevents the GCT from being triggered by mistake and improves the turn-off current density of the GCT. The advantages of low GCT on-state voltage drop and trigger current can be kept, and the GCT turn-off current capability can be improved.
In the embodiment, the second base region with the bulge at the bottom is formed in the cell structure once by combining the side groove structure, so that the second base region is corrugated in the overall structure of the GCT, the preparation process flow is optimized, the preparation process of the GCT with high turn-off current density is simplified, and the production cost of a chip is reduced.
After step S104, the method includes the following steps:
as shown in fig. 9, first conductive type high energy ions are implanted under the substrate 201 to form a first conductive type buffer layer 205 under the substrate 201.
Specifically, the entire surface of the lower side (back side) of the substrate 201 is implanted with first conductivity type high-energy ions, the implantation dose is determined according to the doping concentration of the buffer layer 205, and then the process is carried out in a high-temperature diffusion furnace to control the junction depth (depth) of the buffer layer 205 within a design range.
Step S105: as shown in fig. 10, high-temperature diffusion of first conductivity type ions is selectively performed in the first base region 203 to form a first conductivity type emitter region 206 covering the mesa surface in the surface of the first base region 203.
Specifically, a photoetching process is adopted, the bottom of the side groove is selectively shielded by photoresist, local first conduction type impurity diffusion is carried out on the surface of the boss, the flow rate of a doping gas source and diffusion time in a diffusion furnace are determined according to the doping concentration and the junction depth (depth) of the emission region 206 (cathode comb strip layer), the structure of the emission region 206 (cathode comb strip layer) is controlled within a design range, and then high-temperature diffusion is carried out to form the GCT cathode comb strip structure.
The emitter region 206 and the first base region 203 are formed in the boss, so that the voltage between the gate and the cathode can be increased by more than 50%, the drive control voltage value can be further improved, the commutation speed is improved, and the turn-off capability of the GCT is improved.
Step S106: as shown in fig. 11, first or second high-energy ions are implanted under the buffer layer 205 to form a second conductive type anode region 207 under the buffer layer 205.
The whole surface implantation is performed below (back surface of) the substrate 201, the second conductive type first high energy ion or the second conductive type second high energy ion is implanted, the implantation dosage is determined according to the doping concentration of the anode region 207, and then the implantation is advanced in a high temperature diffusion furnace to control the junction depth (depth) of the anode region 207 within the design range.
Step S107: as shown in fig. 12, an anode metal layer 208 electrically connected to the anode region 207 is formed under the anode region 207.
Specifically, an anode metal layer 208 electrically connected to the anode region 207 is formed below the anode region 207 by an evaporation process.
Step S108: a cathode metal layer 210 electrically connected to the emitter region 206 is formed over the lands.
Specifically, an electrode metal layer is formed by an evaporation process, and after etching, a cathode metal layer 210 electrically connected to the emitter region 206 is formed above the mesa.
Step S109: a gate metal layer 209 is formed at the bottom of the side trench electrically connected to the short base region 202.
Specifically, an electrode metal layer is formed by an evaporation process, and after etching, a gate metal layer 209 electrically connected to the short base region 202 is formed at the bottom of the side trench.
In the present embodiment, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type. Specifically, the type of the device to be manufactured may be selected appropriately according to actual needs.
In the present embodiment, a method for manufacturing a cell structure 200 of a gate commutated thyristor is provided, which includes forming lateral trenches on two sides of the cell structure 200 on a surface of a substrate 201, so as to form a boss on the central position of the cell structure 200 on the surface of the substrate 201; forming a second conductivity type short base region 202 in the substrate 201 below the side trench and the mesa; wherein, the bottom of the short base region 202 is provided with a bulge at the position corresponding to the boss; forming a second conductive type first base region 203 above the short base region 202 in the boss, and forming a second conductive type second base region 204 below the short base region 202; wherein, the bottom of the second base region 204 is provided with a bulge at the position corresponding to the boss; forming a first conductive type emitter region 206 covering the surface of the mesa in the surface of the first base region 203; wherein the doping concentration of the short base region 202 is higher than that of the first base region 203 and the second base region 204. The driving control voltage value can be improved, so that the commutation speed is improved, the turn-off speed is improved, and the turn-off capability of the GCT chip is improved.
The above is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, which may be variously modified and varied by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. Although the embodiments disclosed in the present disclosure are described above, the embodiments are merely used for understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the appended claims.
Claims (9)
1. A cell structure of a gate commutated thyristor, comprising:
a first conductive type substrate; side grooves are arranged on two sides of the cellular structure and downwards on the surface of the substrate, so that bosses are formed on the surface of the substrate at the center of the cellular structure;
the second conductive type short base region is arranged in the substrate and is positioned below the side groove and the boss; the bottom of the short base region is provided with a bulge at a position corresponding to the boss;
the second conductive type first base region is arranged in the boss and is positioned above the short base region;
a second conductive type second base region which is arranged in the substrate and is positioned below the short base region; the bottom of the second base region is provided with a bulge at a position corresponding to the boss;
a first conductive type emitter region located in the first base region surface and covering the mesa surface;
and the doping concentration of the short base region is higher than that of the first base region and that of the second base region.
2. The cell structure of the gate commutated thyristor of claim 1, wherein the lateral trench has a depth of 30 to 50 μm.
3. The cell structure of a gate commutated thyristor according to claim 1,
the doping concentration of the first base region is 1E 15-1E 16cm -3 ；
The doping concentration of the short base region is 1E 15-5E 18cm -3 ；
The doping concentration of the second base region is 1E 13-1E 16cm -3 。
4. The cell structure of a gate commutated thyristor according to claim 1, further comprising:
a first conductive type buffer layer under the substrate;
a second conductive type anode region located under the buffer layer;
an anode metal layer located below the anode region and electrically connected to the anode region;
the gate metal layer is positioned at the bottom of the side groove and electrically connected with the short base region;
and a cathode metal layer located over the boss and electrically connected to the emitter region.
5. A method for fabricating a cell structure of a gate commutated thyristor according to any one of claims 1 to 4, comprising:
providing a first conductive type substrate;
forming lateral grooves on the two sides of the cellular structure on the surface of the substrate so as to form bosses on the central position of the cellular structure on the surface of the substrate;
injecting first high-energy ions of a second conduction type into the substrate below the side grooves in an oblique ion injection mode, and performing a high-temperature diffusion process to form short base regions of the second conduction type below the side grooves and the bosses in the substrate; the bottom of the short base region is provided with a bulge at a position corresponding to the boss;
injecting second high-energy ions of a second conductive type above the substrate and performing a high-temperature diffusion process to form a first base region of the second conductive type above the short base region in the boss and diffuse the second high-energy ions below the short base region to form a second base region of the second conductive type below the short base region; the bottom of the second base region is provided with a bulge at a position corresponding to the boss, and the doping concentration of the short base region is higher than that of the first base region and that of the second base region;
and selectively performing high-temperature diffusion of first conductive type ions in the first base region to form a first conductive type emitter region covering the surface of the boss in the surface of the first base region.
6. The method of claim 5, wherein the first energetic ion has a smaller diffusion coefficient than the second energetic ion.
7. The method for manufacturing a cell structure of a gate commutated thyristor according to claim 5, wherein before the step of selectively performing high-temperature diffusion of the first conductivity type ions in the first base region to form the first conductivity type emitter region covering the mesa surface in the surface of the first base region, the method further comprises the steps of:
and implanting first conductivity type high-energy ions below the substrate to form a first conductivity type buffer layer below the substrate.
8. The method for manufacturing a cell structure of a gate commutated thyristor according to claim 7, wherein after the step of selectively performing high-temperature diffusion of the first conductivity type ions in the first base region to form the first conductivity type emitter region covering the mesa surface in the surface of the first base region, the method further comprises the steps of:
implanting the first or second high energy ions under the buffer layer to form a second conductivity type anode region under the buffer layer;
forming an anode metal layer electrically connected with the anode region below the anode region;
forming a cathode metal layer electrically connected with the emission region over the boss;
and forming a gate metal layer electrically connected with the short base region at the bottom of the side groove.
9. A gate-commutated thyristor, comprising a plurality of cell structures of the gate-commutated thyristor according to any one of claims 1 to 4.
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