WO2023178866A1 - Silicon carbide device and fabrication method therefor - Google Patents

Silicon carbide device and fabrication method therefor Download PDF

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WO2023178866A1
WO2023178866A1 PCT/CN2022/101594 CN2022101594W WO2023178866A1 WO 2023178866 A1 WO2023178866 A1 WO 2023178866A1 CN 2022101594 W CN2022101594 W CN 2022101594W WO 2023178866 A1 WO2023178866 A1 WO 2023178866A1
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silicon carbide
gate
layer
type
type silicon
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PCT/CN2022/101594
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French (fr)
Chinese (zh)
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范让萱
缪进征
王鹏飞
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苏州东微半导体股份有限公司
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Publication of WO2023178866A1 publication Critical patent/WO2023178866A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • the present application relates to the technical field of silicon carbide devices, for example, to a silicon carbide device and a manufacturing method thereof.
  • silicon carbide material has the characteristics of large bandgap width, high critical breakdown electric field, high thermal conductivity and high electron saturation drift speed. It is widely used in high power, high temperature and high frequency power applications.
  • the electronic field has broad application prospects.
  • Trench silicon carbide devices eliminate the parasitic Junction Field-Effect Transistor (JFET) resistance in planar silicon carbide devices, reduce the cell size, increase the current density, and also reduce the conduction resistance, so trench silicon carbide devices gradually replace planar silicon carbide devices and become the mainstream.
  • Silicon carbide devices usually use silicon dioxide as the gate dielectric layer material.
  • the gate dielectric layer Since the dielectric constant of silicon carbide is about 2.5 times that of silicon dioxide, the gate dielectric layer withstands about 2.5 times the drift layer when the silicon carbide device is in the blocking state. electric field. In trench-type silicon carbide devices, the electric field distribution at the bottom corner of the gate trench is concentrated, making it easier for the gate dielectric layer at the bottom corner of the gate trench to be broken down before avalanche breakdown occurs in the silicon carbide device, making the silicon carbide device reliability is reduced.
  • This application provides a silicon carbide device and a manufacturing method thereof to improve the reliability of the silicon carbide device.
  • a first gate located on one side of the gate trench, and a second gate located on the other side of the gate trench.
  • the first gate and the second gate pass through a gate dielectric layer. Isolated from the n-type silicon carbide layer;
  • a p-type body region located within the n-type silicon carbide layer and between adjacent gate trenches;
  • An n-type source region located within the p-type body region
  • a p+ region located in the n-type silicon carbide layer and close to one side of the second gate and connected to the p-type body region.
  • the p+ region extends from the sidewall position of the gate trench to the bottom of the gate trench.
  • An embodiment of the present application provides a method for manufacturing a silicon carbide device, including:
  • Form a hard mask layer on the n-type silicon carbide layer define the position of the gate trench through a photolithography process, and etch the hard mask layer to expose the n-type silicon carbide layer;
  • the n-type silicon carbide layer is etched using a combined anisotropic and isotropic etching method to form a gate trench in the n-type silicon carbide layer.
  • the depth of the gate trench is greater than the depth of the p-type body region;
  • p-type ion implantation to form a p+ region in the n-type silicon carbide layer.
  • the p+ region is located on one side of the gate trench and extends from the edge of the gate trench.
  • the sidewall position extends to the bottom of the gate trench;
  • a first conductive layer is formed on the gate dielectric layer and the first conductive layer is etched to form a first gate electrode and a second gate electrode in the gate trench.
  • the second gate electrode is located close to one side of the p+ region.
  • Figure 1 is a schematic cross-sectional structural diagram of a silicon carbide device provided by an embodiment of the present application
  • Figure 2 is a schematic cross-sectional structural diagram of a process node of a manufacturing method for silicon carbide devices provided by an embodiment of the present application;
  • Figure 3 is a schematic cross-sectional structural diagram of a process node of another method of manufacturing a silicon carbide device provided by an embodiment of the present application;
  • Figure 4 is a schematic cross-sectional structural diagram of a process node of another method for manufacturing a silicon carbide device provided by an embodiment of the present application;
  • FIG. 5 is a schematic cross-sectional structural diagram of a process node of another method for manufacturing a silicon carbide device provided by an embodiment of the present application.
  • Figure 1 is a schematic cross-sectional structural diagram of a silicon carbide device provided by an embodiment of the present application.
  • the silicon carbide device of the present application includes an n-type silicon carbide layer 20, and a plurality of Gate trench 32.
  • the first gate electrode 25a is located on one side of the gate trench 32
  • the second gate electrode 25b is located on the other side of the gate trench 32.
  • the first gate electrode 25a and the second gate electrode 25b are connected to each other through the gate dielectric layer 24.
  • An n-type silicon carbide layer 20 isolates.
  • the first gate electrode 25a and the second gate electrode 25b both extend from the sidewall position of the gate trench 32 to the surface of the n-type silicon carbide layer 20, which can increase the size of the first gate electrode 25a and the second gate electrode 25b.
  • the lateral size of the second gate 25b makes it easier for the first gate 25a and the second gate 25b to be led out by external electrodes.
  • the first gate 25a and the second gate 25b are usually connected to an external gate voltage to control the opening and closing of the current channel.
  • the p-type body region 21 is located in the n-type silicon carbide layer 20 and between adjacent gate trenches 32 , and the n-type source region 22 is located in the p-type body region 21 .
  • both the p-type body region 21 and the n-type source region 22 are externally connected to the source metal layer 27, and the passivation layer 26 is provided as an insulating isolation between the metal layers.
  • the p+ region 23 is located in the n-type silicon carbide layer 20 and close to the second gate electrode 25b side and connected to the p-type body region 21.
  • the p+ region 23 extends from the sidewall position of the gate trench 32 to the gate trench 32. bottom.
  • FIG. 1 only takes the formation of the p+ region at the right sidewall of the gate trench 32 as an example.
  • the p+ region may also be formed at the left sidewall of the gate trench. This is not limited in the embodiment of the present application. .
  • Figure 2 is a schematic cross-sectional structural diagram of a process node of a manufacturing method of a silicon carbide device provided by an embodiment of the present application
  • Figure 3 is a schematic cross-sectional structural diagram of a process node of another method of manufacturing a silicon carbide device provided by an embodiment of the present application.
  • Figure 4 is a cross-sectional structural diagram of a process node of another method of manufacturing a silicon carbide device provided by an embodiment of the present application
  • Figure 5 is a cross-sectional view of a process node of another method of manufacturing a silicon carbide device provided by an embodiment of the present application.
  • Schematic. As shown in Figures 2 to 5, a method for manufacturing a silicon carbide device in this application includes:
  • p-type ion implantation is performed to form a p-type body region 21 in the provided n-type silicon carbide layer 20, and then n-type ion implantation is performed to form an n-type source region in the p-type body region 21. twenty two.
  • a hard mask layer 31 is formed on the n-type silicon carbide layer 20 , and then a layer of photoresist is deposited.
  • the position of the gate trench 32 is defined through a photolithography process, and then the hard mask layer 31 is formed on the n-type silicon carbide layer 20 .
  • the film layer 31 is etched to expose the n-type silicon carbide layer 20.
  • the remaining hard mask layer 31 is used as a mask to etch the film layer 31 through anisotropic and isotropic etching methods.
  • the n-type silicon carbide layer 20 is etched to form a gate trench 32 in the n-type silicon carbide layer 20 .
  • the depth of the gate trench 32 is greater than the depth of the p-type body region 21 .
  • the remaining hard mask layer 31 is used as a mask to etch the n-type silicon carbide layer 20 through a combined anisotropic and isotropic etching method.
  • Forming the gate trench 32 may include: using the remaining hard mask layer 31 as a mask, anisotropically etching the n-type silicon carbide layer 20 to form a shallow trench in the n-type silicon carbide layer 20; The n-type silicon carbide layer 20 is isotropically etched in the trench to form the gate trench 32 in the n-type silicon carbide layer 20. That is, when the gate trench 32 is formed by etching, the n-type silicon carbide layer 20 can be etched through anisotropic etching first. A shallow trench is formed in the silicon layer 20 , and the depth and width of the shallow trench are increased through isotropic etching to form the gate trench 32 , which can improve the topography of the bottom corner of the gate trench 32 .
  • a layer of photoresist is deposited, the position of the p+ region is defined through the photolithography process, and then the exposed hard mask layer 31 is etched away. After the photoresist is removed, the remaining The hard mask layer 31 is a mask, and p-type ions are implanted to form a p+ region 23 in the n-type silicon carbide layer 20.
  • the p+ region 23 is located on one side of the gate trench 32 and extends from the sidewall position of the gate trench 32. to the bottom of gate trench 32 .
  • the remaining hard mask layer 31 is removed, a gate dielectric layer 24 is formed on the surface of the formed structure, and then a first conductive layer is formed on the gate dielectric layer 24 and conductive to the first conductive layer.
  • the first gate electrode 25 a and the second gate electrode 25 b are formed in the gate trench 32 , and the second gate electrode 25 b is located on the side close to the p + region 23 .
  • the first gate electrode 25a and the second gate electrode 25b both extend from the sidewall position of the gate trench 32 to the surface of the n-type silicon carbide layer 20, which can increase the size of the first gate electrode 25a and the second gate electrode 25b.
  • the lateral size of the second gate 25b makes it easier for the first gate 25a and the second gate 25b to be led out by external electrodes.
  • a passivation layer 26 is formed on the surface of the structure formed by the above operations, and the passivation layer 26 is etched to form a contact hole, and then the source metal layer 27 is formed, and then the n-type silicon nitride layer is formed. The bottom of the drain metal layer is formed. This process is a common process in the industry and will not be shown in the embodiments of this application.
  • This application optimizes the gate trench morphology through self-alignment, which can effectively reduce the electric field intensity at the bottom corner of the gate trench, making the gate dielectric layer at the bottom corner of the gate trench less likely to be broken down, thereby improving the performance of silicon carbide devices. reliability.
  • this application uses a hard mask layer etched by the gate trench to realize self-aligned ion implantation in the p+ region, which can greatly streamline the manufacturing process and reduce manufacturing costs.

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Abstract

Disclosed herein are a silicon carbide device and a fabrication method therefor. The silicon carbide device comprises: an n-type silicon carbide layer; a plurality of gate trenches located in the n-type silicon carbide layer; a first gate located on one side in the gate trenches, and a second gate located on another side in the gate trenches, the first gate and the second gate being isolated from the n-type silicon carbide layer by means of a gate dielectric layer; a p-type body region located in the n-type silicon carbide layer and between adjacent gate trenches; an n-type source region located in the p-type body region; and a p+ region which is located in the n-type silicon carbide layer near one side of the second gate and connected to the p-type body region, the p+ region extending from a sidewall position of the gate trenches to a bottom part of the gate trenches.

Description

碳化硅器件及其制造方法Silicon carbide device and manufacturing method
本申请要求在2022年03月21日提交中国专利局、申请号为202210280761.1的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。This application claims priority to the Chinese patent application with application number 202210280761.1, which was submitted to the China Patent Office on March 21, 2022. The entire content of this application is incorporated into this application by reference.
技术领域Technical field
本申请涉及碳化硅器件技术领域，例如涉及一种碳化硅器件及其制造方法。The present application relates to the technical field of silicon carbide devices, for example, to a silicon carbide device and a manufacturing method thereof.
背景技术Background technique
碳化硅材料作为第三代宽禁带半导体材料的代表之一，具有禁带宽度大、临界击穿电场高、热导率高和电子饱和漂移速度高等特点，在大功率、高温及高频电力电子领域具有广阔的应用前景。沟槽型碳化硅器件消除了平面型碳化硅器件中寄生的结型场效应晶体管(Junction Field-Effect Transistor，JFET)电阻，减小了元胞尺寸，使得电流密度提高，同时也降低了导通电阻，因此沟槽型碳化硅器件逐步取代平面型碳化硅器件成为主流。碳化硅器件通常采用二氧化硅作为栅介质层材料，由于碳化硅的介电常数约是二氧化硅的2.5倍，在碳化硅器件处于阻断状态时栅介质层承受了约2.5倍的漂移层电场。在沟槽型碳化硅器件中，栅沟槽底部拐角处的电场分布集中，使得栅沟槽底部拐角处的栅介质层更容易在碳化硅器件发生雪崩击穿前被击穿，使得碳化硅器件的可靠性降低。As one of the representatives of the third generation of wide bandgap semiconductor materials, silicon carbide material has the characteristics of large bandgap width, high critical breakdown electric field, high thermal conductivity and high electron saturation drift speed. It is widely used in high power, high temperature and high frequency power applications. The electronic field has broad application prospects. Trench silicon carbide devices eliminate the parasitic Junction Field-Effect Transistor (JFET) resistance in planar silicon carbide devices, reduce the cell size, increase the current density, and also reduce the conduction resistance, so trench silicon carbide devices gradually replace planar silicon carbide devices and become the mainstream. Silicon carbide devices usually use silicon dioxide as the gate dielectric layer material. Since the dielectric constant of silicon carbide is about 2.5 times that of silicon dioxide, the gate dielectric layer withstands about 2.5 times the drift layer when the silicon carbide device is in the blocking state. electric field. In trench-type silicon carbide devices, the electric field distribution at the bottom corner of the gate trench is concentrated, making it easier for the gate dielectric layer at the bottom corner of the gate trench to be broken down before avalanche breakdown occurs in the silicon carbide device, making the silicon carbide device reliability is reduced.
发明内容Contents of the invention
本申请提供一种碳化硅器件及其制造方法，以提高碳化硅器件的可靠性。This application provides a silicon carbide device and a manufacturing method thereof to improve the reliability of the silicon carbide device.
本申请实施例提供的一种碳化硅器件，包括：A silicon carbide device provided by an embodiment of the present application includes:
n型碳化硅层；n-type silicon carbide layer;
位于所述n型碳化硅层内的多个栅沟槽；A plurality of gate trenches located in the n-type silicon carbide layer;
位于所述栅沟槽内的一侧的第一栅极，位于所述栅沟槽内的另一侧的第二栅极，所述第一栅极和所述第二栅极通过栅介质层与所述n型碳化硅层隔离；A first gate located on one side of the gate trench, and a second gate located on the other side of the gate trench. The first gate and the second gate pass through a gate dielectric layer. Isolated from the n-type silicon carbide layer;
位于所述n型碳化硅层内且介于相邻的栅沟槽之间的p型体区；A p-type body region located within the n-type silicon carbide layer and between adjacent gate trenches;
位于所述p型体区内的n型源区；An n-type source region located within the p-type body region;
位于所述n型碳化硅层内且靠近所述第二栅极一侧并与所述p型体区连接的p+区域，所述p+区域从所述栅沟槽的侧壁位置处延伸至所述栅沟槽的底部。A p+ region located in the n-type silicon carbide layer and close to one side of the second gate and connected to the p-type body region. The p+ region extends from the sidewall position of the gate trench to the bottom of the gate trench.
本申请实施例提供的一种碳化硅器件的制造方法，包括：An embodiment of the present application provides a method for manufacturing a silicon carbide device, including:
进行p型离子注入，在提供的n型碳化硅层内形成p型体区；Perform p-type ion implantation to form a p-type body region in the provided n-type silicon carbide layer;
进行n型离子注入，在所述p型体区内形成n型源区；Perform n-type ion implantation to form an n-type source region in the p-type body region;
在所述n型碳化硅层上形成硬掩膜层，通过光刻工艺定义出栅沟槽的位置，对所述硬掩膜层进行刻蚀将所述n型碳化硅层暴露出来；Form a hard mask layer on the n-type silicon carbide layer, define the position of the gate trench through a photolithography process, and etch the hard mask layer to expose the n-type silicon carbide layer;
以剩余的硬掩膜层为掩膜，通过各向异性和各向同性相结合的刻蚀方法对所述n型碳化硅层进行刻蚀，在所述n型碳化硅层内形成栅沟槽，所述栅沟槽深度大于所述p型体区的深度；Using the remaining hard mask layer as a mask, the n-type silicon carbide layer is etched using a combined anisotropic and isotropic etching method to form a gate trench in the n-type silicon carbide layer. , the depth of the gate trench is greater than the depth of the p-type body region;
通过光刻工艺定义p+区域的位置，刻蚀掉暴露出的硬掩膜层；Define the position of the p+ region through the photolithography process, and etch away the exposed hard mask layer;
以剩余的硬掩膜层为掩膜，进行p型离子注入在所述n型碳化硅层内形成p+区域，所述p+区域位于所述栅沟槽的一侧并从所述栅沟槽的侧壁位置处延伸至所述栅沟槽的底部；Using the remaining hard mask layer as a mask, perform p-type ion implantation to form a p+ region in the n-type silicon carbide layer. The p+ region is located on one side of the gate trench and extends from the edge of the gate trench. The sidewall position extends to the bottom of the gate trench;
去除剩余的硬掩膜层，在所形成结构的表面形成栅介质层；Remove the remaining hard mask layer and form a gate dielectric layer on the surface of the formed structure;
在所述栅介质层上形成第一导电层并对所述第一导电层进行刻蚀，在所述栅沟槽内形成第一栅极和第二栅极，所述第二栅极位于靠近所述p+区域的一侧。A first conductive layer is formed on the gate dielectric layer and the first conductive layer is etched to form a first gate electrode and a second gate electrode in the gate trench. The second gate electrode is located close to one side of the p+ region.
附图说明Description of the drawings
图1是本申请实施例提供的一种碳化硅器件的剖面结构示意图；Figure 1 is a schematic cross-sectional structural diagram of a silicon carbide device provided by an embodiment of the present application;
图2是本申请实施例提供的一种碳化硅器件的制造方法的工艺节点的剖面结构示意图；Figure 2 is a schematic cross-sectional structural diagram of a process node of a manufacturing method for silicon carbide devices provided by an embodiment of the present application;
图3是本申请实施例提供的另一种碳化硅器件的制造方法的工艺节点的剖面结构示意图；Figure 3 is a schematic cross-sectional structural diagram of a process node of another method of manufacturing a silicon carbide device provided by an embodiment of the present application;
图4是本申请实施例提供的另一种碳化硅器件的制造方法的工艺节点的剖面结构示意图；Figure 4 is a schematic cross-sectional structural diagram of a process node of another method for manufacturing a silicon carbide device provided by an embodiment of the present application;
图5是本申请实施例提供的另一种碳化硅器件的制造方法的工艺节点的剖面结构示意图。FIG. 5 is a schematic cross-sectional structural diagram of a process node of another method for manufacturing a silicon carbide device provided by an embodiment of the present application.
具体实施方式Detailed ways
以下将结合本申请实施例中的附图，通过具体方式，描述本申请的技术方案。The technical solution of the present application will be described in a specific manner with reference to the drawings in the embodiments of the present application.
图1是本申请实施例提供的一种碳化硅器件的剖面结构示意图，如图1所示，本申请的碳化硅器件包括n型碳化硅层20，位于n型碳化硅层20内的多个栅沟槽32，本申请实施例中仅示例性的示出了两个栅沟槽32结构。位于栅沟槽 32内的一侧的第一栅极25a，位于栅沟槽32内的另一侧的第二栅极25b，第一栅极25a和第二栅极25b通过栅介质层24与n型碳化硅层20隔离。一实施例中，第一栅极25a和第二栅极25b均从栅沟槽32的侧壁位置处延伸至n型碳化硅层20的表面之上，这样可以增大第一栅极25a和第二栅极25b的横向尺寸，使得第一栅极25a和第二栅极25b更容易被外部电极引出。第一栅极25a和第二栅极25b通常外接栅极电压来控制电流沟道的开启和关断。Figure 1 is a schematic cross-sectional structural diagram of a silicon carbide device provided by an embodiment of the present application. As shown in Figure 1, the silicon carbide device of the present application includes an n-type silicon carbide layer 20, and a plurality of Gate trench 32. In the embodiment of this application, only two gate trench 32 structures are shown as examples. The first gate electrode 25a is located on one side of the gate trench 32, and the second gate electrode 25b is located on the other side of the gate trench 32. The first gate electrode 25a and the second gate electrode 25b are connected to each other through the gate dielectric layer 24. An n-type silicon carbide layer 20 isolates. In one embodiment, the first gate electrode 25a and the second gate electrode 25b both extend from the sidewall position of the gate trench 32 to the surface of the n-type silicon carbide layer 20, which can increase the size of the first gate electrode 25a and the second gate electrode 25b. The lateral size of the second gate 25b makes it easier for the first gate 25a and the second gate 25b to be led out by external electrodes. The first gate 25a and the second gate 25b are usually connected to an external gate voltage to control the opening and closing of the current channel.
位于n型碳化硅层20内且介于相邻的栅沟槽32之间的p型体区21，位于p型体区21内的n型源区22。一实施例中，p型体区21和n型源区22均外接源极金属层27，钝化层26设置为金属层之间的绝缘隔离。The p-type body region 21 is located in the n-type silicon carbide layer 20 and between adjacent gate trenches 32 , and the n-type source region 22 is located in the p-type body region 21 . In one embodiment, both the p-type body region 21 and the n-type source region 22 are externally connected to the source metal layer 27, and the passivation layer 26 is provided as an insulating isolation between the metal layers.
位于n型碳化硅层20内且靠近第二栅极25b一侧并与p型体区21连接的p+区域23，p+区域23从栅沟槽32的侧壁位置处延伸至栅沟槽32的底部。图1仅以在栅沟槽32的右侧侧壁处形成p+区域为例进行说明，或者，还可以在栅沟槽的左侧侧壁处形成p+区域，本申请实施例对此不进行限定。The p+ region 23 is located in the n-type silicon carbide layer 20 and close to the second gate electrode 25b side and connected to the p-type body region 21. The p+ region 23 extends from the sidewall position of the gate trench 32 to the gate trench 32. bottom. FIG. 1 only takes the formation of the p+ region at the right sidewall of the gate trench 32 as an example. Alternatively, the p+ region may also be formed at the left sidewall of the gate trench. This is not limited in the embodiment of the present application. .
图2是本申请实施例提供的一种碳化硅器件的制造方法的工艺节点的剖面结构示意图；图3是本申请实施例提供的另一种碳化硅器件的制造方法的工艺节点的剖面结构示意图；图4是本申请实施例提供的另一种碳化硅器件的制造方法的工艺节点的剖面结构示意图；图5是本申请实施例提供的另一种碳化硅器件的制造方法的工艺节点的剖面结构示意图。如图2至图5所示，本申请的一种碳化硅器件的制造方法，包括：Figure 2 is a schematic cross-sectional structural diagram of a process node of a manufacturing method of a silicon carbide device provided by an embodiment of the present application; Figure 3 is a schematic cross-sectional structural diagram of a process node of another method of manufacturing a silicon carbide device provided by an embodiment of the present application. ; Figure 4 is a cross-sectional structural diagram of a process node of another method of manufacturing a silicon carbide device provided by an embodiment of the present application; Figure 5 is a cross-sectional view of a process node of another method of manufacturing a silicon carbide device provided by an embodiment of the present application. Schematic. As shown in Figures 2 to 5, a method for manufacturing a silicon carbide device in this application includes:
首先，如图2所示，进行p型离子注入，在提供的n型碳化硅层20内形成p型体区21，然后进行n型离子注入，在p型体区21内形成n型源区22。First, as shown in Figure 2, p-type ion implantation is performed to form a p-type body region 21 in the provided n-type silicon carbide layer 20, and then n-type ion implantation is performed to form an n-type source region in the p-type body region 21. twenty two.
接下来，如图3所示，在n型碳化硅层20上形成硬掩膜层31，然后淀积一层光刻胶，通过光刻工艺定义出栅沟槽32的位置，然后对硬掩膜层31进行刻蚀将n型碳化硅层20暴露出来，去除掉光刻胶后，以剩余的硬掩膜层31为掩膜，通过各向异性和各向同性相结合的刻蚀方法对n型碳化硅层20进行刻蚀，在n型碳化硅层20内形成栅沟槽32，栅沟槽32的深度大于p型体区21的深度。Next, as shown in FIG. 3 , a hard mask layer 31 is formed on the n-type silicon carbide layer 20 , and then a layer of photoresist is deposited. The position of the gate trench 32 is defined through a photolithography process, and then the hard mask layer 31 is formed on the n-type silicon carbide layer 20 . The film layer 31 is etched to expose the n-type silicon carbide layer 20. After the photoresist is removed, the remaining hard mask layer 31 is used as a mask to etch the film layer 31 through anisotropic and isotropic etching methods. The n-type silicon carbide layer 20 is etched to form a gate trench 32 in the n-type silicon carbide layer 20 . The depth of the gate trench 32 is greater than the depth of the p-type body region 21 .
一实施例中，以剩余的硬掩膜层31为掩膜，通过各向异性和各向同性相结合的刻蚀方法对n型碳化硅层20进行刻蚀，在n型碳化硅层20内形成栅沟槽32，可以包括：以剩余的硬掩膜层31为掩膜，对n型碳化硅层20进行各向异性刻蚀在n型碳化硅层20内形成浅沟槽；在浅沟槽内对n型碳化硅层20进行各向同性刻蚀在n型碳化硅层20内形成栅沟槽32，即刻蚀形成栅沟槽32时，可以先通过各向异性刻蚀在n型碳化硅层20形成浅沟槽，再通过各向同性刻蚀增加浅沟槽的深度和宽度以形成栅沟槽32，这样可以改善栅沟槽32底部拐角处的形貌。In one embodiment, the remaining hard mask layer 31 is used as a mask to etch the n-type silicon carbide layer 20 through a combined anisotropic and isotropic etching method. Forming the gate trench 32 may include: using the remaining hard mask layer 31 as a mask, anisotropically etching the n-type silicon carbide layer 20 to form a shallow trench in the n-type silicon carbide layer 20; The n-type silicon carbide layer 20 is isotropically etched in the trench to form the gate trench 32 in the n-type silicon carbide layer 20. That is, when the gate trench 32 is formed by etching, the n-type silicon carbide layer 20 can be etched through anisotropic etching first. A shallow trench is formed in the silicon layer 20 , and the depth and width of the shallow trench are increased through isotropic etching to form the gate trench 32 , which can improve the topography of the bottom corner of the gate trench 32 .
接下来，如图4所示，淀积一层光刻胶，通过光刻工艺定义p+区域的位置，然后刻蚀掉暴露出的硬掩膜层31，去除掉光刻胶后，以剩余的硬掩膜层31为掩膜，进行p型离子注入在n型碳化硅层20内形成p+区域23，p+区域23位于栅沟槽32的一侧并从栅沟槽32的侧壁位置处延伸至栅沟槽32的底部。Next, as shown in Figure 4, a layer of photoresist is deposited, the position of the p+ region is defined through the photolithography process, and then the exposed hard mask layer 31 is etched away. After the photoresist is removed, the remaining The hard mask layer 31 is a mask, and p-type ions are implanted to form a p+ region 23 in the n-type silicon carbide layer 20. The p+ region 23 is located on one side of the gate trench 32 and extends from the sidewall position of the gate trench 32. to the bottom of gate trench 32 .
接下来，如图5所示，去除掉剩余的硬掩膜层31，在所形成结构的表面形成栅介质层24，之后在栅介质层24上形成第一导电层并对所述第一导电层进行刻蚀，在栅沟槽32内形成第一栅极25a和第二栅极25b，第二栅极25b位于靠近p+区域23的一侧。Next, as shown in FIG. 5 , the remaining hard mask layer 31 is removed, a gate dielectric layer 24 is formed on the surface of the formed structure, and then a first conductive layer is formed on the gate dielectric layer 24 and conductive to the first conductive layer. The first gate electrode 25 a and the second gate electrode 25 b are formed in the gate trench 32 , and the second gate electrode 25 b is located on the side close to the p + region 23 .
一实施例中，第一栅极25a和第二栅极25b均从栅沟槽32的侧壁位置处延伸至n型碳化硅层20的表面之上，这样可以增大第一栅极25a和第二栅极25b的横向尺寸，使得第一栅极25a和第二栅极25b更容易被外部电极引出。In one embodiment, the first gate electrode 25a and the second gate electrode 25b both extend from the sidewall position of the gate trench 32 to the surface of the n-type silicon carbide layer 20, which can increase the size of the first gate electrode 25a and the second gate electrode 25b. The lateral size of the second gate 25b makes it easier for the first gate 25a and the second gate 25b to be led out by external electrodes.
一实施例中在通过以上操作所形成结构的表面形成钝化层26，并对所述钝化层26进行刻蚀形成接触孔，然后形成源极金属层27，之后在n型氮化硅层的底部形成漏极金属层。该工艺为业界的常规工艺，本申请实施例中不再展示。In one embodiment, a passivation layer 26 is formed on the surface of the structure formed by the above operations, and the passivation layer 26 is etched to form a contact hole, and then the source metal layer 27 is formed, and then the n-type silicon nitride layer is formed. The bottom of the drain metal layer is formed. This process is a common process in the industry and will not be shown in the embodiments of this application.
本申请通过自对准方式优化栅沟槽形貌，可以有效降低栅沟槽底部拐角处的电场强度，使得栅沟槽底部拐角处的栅介质层不容易被击穿，从而提高碳化硅器件的可靠性。同时，本申请使用栅沟槽刻蚀的硬掩膜层来实现p+区域自对准离子注入，可大幅精简制造工艺，降低制造成本。This application optimizes the gate trench morphology through self-alignment, which can effectively reduce the electric field intensity at the bottom corner of the gate trench, making the gate dielectric layer at the bottom corner of the gate trench less likely to be broken down, thereby improving the performance of silicon carbide devices. reliability. At the same time, this application uses a hard mask layer etched by the gate trench to realize self-aligned ion implantation in the p+ region, which can greatly streamline the manufacturing process and reduce manufacturing costs.

Claims (7)

  1. 一种碳化硅器件，包括：A silicon carbide device including:
    n型碳化硅层；n-type silicon carbide layer;
    位于所述n型碳化硅层内的多个栅沟槽；A plurality of gate trenches located in the n-type silicon carbide layer;
    位于所述栅沟槽内的一侧的第一栅极，位于所述栅沟槽内的另一侧的第二栅极，所述第一栅极和所述第二栅极通过栅介质层与所述n型碳化硅层隔离；A first gate located on one side of the gate trench, and a second gate located on the other side of the gate trench. The first gate and the second gate pass through a gate dielectric layer. Isolated from the n-type silicon carbide layer;
    位于所述n型碳化硅层内且介于相邻的栅沟槽之间的p型体区；A p-type body region located within the n-type silicon carbide layer and between adjacent gate trenches;
    位于所述p型体区内的n型源区；An n-type source region located within the p-type body region;
    位于所述n型碳化硅层内且靠近所述第二栅极一侧并与所述p型体区连接的p+区域，所述p+区域从所述栅沟槽的侧壁位置处延伸至所述栅沟槽的底部。A p+ region located in the n-type silicon carbide layer and close to one side of the second gate and connected to the p-type body region. The p+ region extends from the sidewall position of the gate trench to the bottom of the gate trench.
  2. 如权利要求1所述的碳化硅器件，其中，所述第一栅极和所述第二栅极均从所述栅沟槽的侧壁位置处延伸至所述n型碳化硅层的表面之上。The silicon carbide device of claim 1, wherein the first gate electrode and the second gate electrode both extend from a sidewall position of the gate trench to a surface of the n-type silicon carbide layer. superior.
  3. 如权利要求1所述的碳化硅器件，其中，所述n型源区和所述p型体区均外接源极金属层。The silicon carbide device of claim 1, wherein the n-type source region and the p-type body region are both externally connected to a source metal layer.
  4. 一种碳化硅器件的制造方法，包括：A method for manufacturing silicon carbide devices, including:
    进行p型离子注入，在提供的n型碳化硅层内形成p型体区；Perform p-type ion implantation to form a p-type body region in the provided n-type silicon carbide layer;
    进行n型离子注入，在所述p型体区内形成n型源区；Perform n-type ion implantation to form an n-type source region in the p-type body region;
    在所述n型碳化硅层上形成硬掩膜层，通过光刻工艺定义出栅沟槽的位置，对所述硬掩膜层进行刻蚀将所述n型碳化硅层暴露出来；Form a hard mask layer on the n-type silicon carbide layer, define the position of the gate trench through a photolithography process, and etch the hard mask layer to expose the n-type silicon carbide layer;
    以剩余的硬掩膜层为掩膜，通过各向异性和各向同性相结合的刻蚀方法对所述n型碳化硅层进行刻蚀，在所述n型碳化硅层内形成栅沟槽，所述栅沟槽深度大于所述p型体区的深度；Using the remaining hard mask layer as a mask, the n-type silicon carbide layer is etched using a combined anisotropic and isotropic etching method to form a gate trench in the n-type silicon carbide layer. , the depth of the gate trench is greater than the depth of the p-type body region;
    通过光刻工艺定义p+区域的位置，刻蚀掉暴露出的硬掩膜层；Define the position of the p+ region through the photolithography process, and etch away the exposed hard mask layer;
    以剩余的硬掩膜层为掩膜，进行p型离子注入在所述n型碳化硅层内形成p+区域，所述p+区域位于所述栅沟槽的一侧并从所述栅沟槽的侧壁位置处延伸至所述栅沟槽的底部；Using the remaining hard mask layer as a mask, perform p-type ion implantation to form a p+ region in the n-type silicon carbide layer. The p+ region is located on one side of the gate trench and extends from the edge of the gate trench. The sidewall position extends to the bottom of the gate trench;
    去除剩余的硬掩膜层，在所形成结构的表面形成栅介质层；Remove the remaining hard mask layer and form a gate dielectric layer on the surface of the formed structure;
    在所述栅介质层上形成第一导电层并对所述第一导电层进行刻蚀，在所述栅沟槽内形成第一栅极和第二栅极，所述第二栅极位于靠近所述p+区域的一侧。A first conductive layer is formed on the gate dielectric layer and the first conductive layer is etched to form a first gate electrode and a second gate electrode in the gate trench. The second gate electrode is located close to one side of the p+ region.
  5. 如权利要求4所述的碳化硅器件的制造方法，在所述形成第一栅极和第二栅极之后，还包括：在所形成结构的表面形成钝化层，并对所述钝化层进行 刻蚀形成接触孔，形成源极金属层。The method of manufacturing a silicon carbide device according to claim 4, after forming the first gate electrode and the second gate electrode, further comprising: forming a passivation layer on the surface of the formed structure, and applying the passivation layer to the surface of the formed structure. Etch to form contact holes and form a source metal layer.
  6. 如权利要求4所述的碳化硅器件的制造方法，其中，所述第一栅极和所述第二栅极均从所述栅沟槽的侧壁位置处延伸至所述n型碳化硅层的表面之上。The method of manufacturing a silicon carbide device according to claim 4, wherein the first gate electrode and the second gate electrode both extend from a sidewall position of the gate trench to the n-type silicon carbide layer. above the surface.
  7. 如权利要求4所述的碳化硅器件的制造方法，其中，以剩余的硬掩膜层为掩膜，通过各向异性和各向同性相结合的刻蚀方法对所述n型碳化硅层进行刻蚀，在所述n型碳化硅层内形成栅沟槽，包括：The method for manufacturing a silicon carbide device as claimed in claim 4, wherein the n-type silicon carbide layer is etched using a remaining hard mask layer as a mask using an anisotropic and isotropic etching method. Etching to form a gate trench in the n-type silicon carbide layer includes:
    以剩余的硬掩膜层为掩膜，对所述n型碳化硅层进行各向异性刻蚀在所述n型碳化硅层内形成浅沟槽；Using the remaining hard mask layer as a mask, perform anisotropic etching on the n-type silicon carbide layer to form shallow trenches in the n-type silicon carbide layer;
    在所述浅沟槽内对所述n型碳化硅层进行各向同性刻蚀在所述n型碳化硅层内形成栅沟槽。The n-type silicon carbide layer is isotropically etched in the shallow trench to form a gate trench in the n-type silicon carbide layer.
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