JP3463554B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates also relates to semiconductor equipment,
Insulated gate bipolar transistor (IGBT)
Targeting power devices such as a semiconductor chip having a first main electrode (emitter electrode) and a control electrode (gate electrode) on one main surface of a substrate and a second main electrode (collector electrode) on another main surface. It relates <br/> the semiconductor equipment incorporating the outside air and the flat ceramic package of fully airtight is maintained structure.

[0002]

2. Description of the Related Art An IGBT is an element having the characteristics of both a MOS (metal oxide semiconductor) type FET (field effect transistor) and a bipolar transistor, and is widely used as a power switching device for applications such as an inverter for controlling a motor. It is being appreciated. In addition, recently, since it is a voltage-driven type, it is easy to use, and its safe operation area is wide and it is not easily broken, it is possible to use the IG range from the conventional GTO (gate turn-off) thyristor area to the large capacity area.
The use of BT is expanding.

Unlike the GTO thyristor and the like, the MOS control device such as the IGBT requires an accuracy of several microns to submicron, so that the process of using a large wafer as a device is a good product rate. Can not be adopted due to the relationship of 10mm
It is necessary to mount a plurality of chips of about 28 mm square in parallel.

Further, a MOS such as the IGBT as described above.
In the control device, an emitter electrode and a gate electrode are formed side by side on one main surface of a semiconductor chip. For this reason, in a general module structure, when an IGBT chip is incorporated into a package container, the collector formed on the lower surface side mounts the IGBT on a metal base that also serves as a radiator and draws it out to the outside, and thus the emitter electrode and the gate electrode. Separately from and, it is mounted inside the package by pulling it out through the external lead terminal. After that, a plastic package is provided outside, and a silicone resin such as gel is sealed in it to prevent discharge.

However, in a flat IGBT in which the IGBT is incorporated in a flat ceramic package such as a GTO thyristor, a ceramic package is used and nitrogen is sealed to keep airtightness completely. Therefore, the flat IGBT does not have a structure capable of injecting a gel or the like, and therefore another measure for discharging is required. Therefore, conventionally, the chip surface from the main electrode on the emitter side to the edge surface is passivated in order to prevent edge discharge of the chip. This is because a passivation film is formed by applying about 10 μm of polyimide.
The electric field strength applied to the edge of the chip is weakened.

[0006]

The IGBT chip is obtained by cutting and separating one wafer having a plurality of chips by dicing.
At that time or during subsequent processing, fine shavings or fine metal powder may adhere to the chip. In the structure of the chip end surface of the flat IGBT, the space between the chip edge and the main electrode is protected by a polyimide film, but during assembly, etc., foreign matter such as metal powder as described above may be present on the polyimide film. I may ride. When metal powder or the like gets on the polyimide film, the electric field strength at that portion becomes strong, and the discharge withstand capability of the actual device is lowered, and there is a problem that discharge is generated there or the chip is destroyed by discharge.

The present invention has been made in view of the above circumstances, and is a semiconductor that eliminates internal edge discharge when mounting a plurality of MOS type devices such as IGBTs in a flat package. an object of the present invention is to provide the equipment.

[0008]

In order to solve the above problems, the present invention provides a MOS control having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface. In a semiconductor device in which a die semiconductor chip is incorporated in a flat package having an airtight structure, an insulating resin film having an outer dimension larger than at least the outer dimension of the chip is adhered to a chip edge portion of the first main surface. Provided is a semiconductor device .

According to such a semiconductor equipment, the relative position between the resin film and the chip of the insulating properties, by which the resin film has a structure projecting always outward than the chip, between the chip end face and the main electrode The edge distance can be extended and the discharge withstand capability can be increased. Also, even if a conductive foreign substance such as metal powder gets on the resin film, there is no sudden change in the electric field strength that induces edge discharge, so ensure stable operation in any atmosphere inside the package. Therefore, the reliability can be improved.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings by taking as an example a case where the flat power pack having a pressure contact structure mounting a plurality of IGBT chips is applied. .

FIG. 1 is a diagram showing the structure of an IGBT chip to which the present invention is applied, in which (A) is a plan view of the chip,
(B) is a side view of the chip taken along the arrow aa. In FIG. 1, the IGBT chip 1 has an emitter electrode which is a first main electrode and a gate electrode (not shown) which is a control electrode arranged on the upper surface thereof, and a lower surface which constitutes a collector electrode which is a second main electrode. There is. A guard ring portion 2 is formed on the upper surface of the IGBT chip 1 along the outer periphery thereof. A frame-shaped insulating film 3 is formed so as to cover the guard ring portion 2. The outer dimensions of this insulating film 3 are IGB
When the insulating film 3 is formed to be larger than the external dimensions of the T-chip 1 and the insulating film 3 is bonded to the IGBT chip 1, the outer peripheral end of the insulating film 3 is accurately aligned so that it is always projected outside the chip end face 4. Is done.
In this way, by providing the insulating film 3 so that the outer periphery is exposed to the outside of the chip end face 4, the edge face distance between the chip end face 4 and the emitter electrode is extended, so that the influence of the electric field strength is mitigated. The discharge withstand voltage increases by at least 500 V more than the withstand voltage of the device itself. Therefore, the amount of the length protruding to the outside of the insulating film 3 is determined by the necessary withstand voltage.

The power pack includes a plurality of IGBs.
T chip 1 is mounted, but these IGBT chips 1
At the same time, multiple flywheel diode chips are also built in. Similar to the IGBT chip 1, this flywheel diode chip also has a similar insulating film bonded to the outer periphery of the upper surface where the anode electrode, which is the main electrode, is located.

FIG. 2 is a sectional view of a power pack showing an example of mounting an IGBT chip. In FIG. 2, the molybdenum (Mo) substrate 5 has groove portions 6 formed in a grid pattern on its upper surface. A mesh-shaped positioning guide 7 made of heat-resistant resin is fitted in the groove 6. The IGBT chip 1 to which the insulating film 3 is adhered is mounted on the Mo substrate 5 defined by the positioning guide 7. At this time, the IGBT chip 1 has the collector electrode facing downward and the insulating film 3 with the positioning guide 7
It is inserted into the space surrounded by the positioning guide 7 while sliding along the inner wall surface of the. Therefore, this IG
When mounting the BT chip 1, the insulating film 3 is
Since the tip end surface 4 of the T-chip 1 projects outward from the tip end surface 4, the tip end surface 4 does not directly contact the inner wall surface of the positioning guide 7, and physical damage to the IGBT chip 1 due to the contact is prevented. . Therefore, the insulating film 3 needs to have a flexible material and thickness in order to avoid its bending. In addition, the IGBT chip 1
Are positioned through the insulating film 3, the thermal stress generated on the chip end surface 4 due to the difference in thermal expansion coefficient is absorbed by the insulating film 3, and even if the IGBT chip 1 vibrates, for example, the insulating film Since 3 is interposed, the tip end surface 4 does not rub against the positioning guide 7, and a stable state can be maintained. Further, an emitter terminal 8 made of molybdenum is arranged at a position corresponding to the emitter electrode of the IGBT chip 1. The IGBT chip 1 is electrically connected to the main electrodes by pressure contact from above and below by the emitter terminal 8 and the Mo substrate 5. The gate electrode of the IGBT chip 1 is led to the outside by wire-bonding to the wiring pattern on the ceramic substrate which is provided around the positioning guide 7, and the emitter terminal 8 has a brim-shaped protrusion at an intermediate height position. And is accurately positioned in the positioning guide 7 therethrough. Since the emitter terminal 8 presses the fine pattern of the IGBT chip 1 from above, the emitter terminal 8
The IGBT chip 1 and the IGBT chip 1 must be accurately aligned. Although the emitter terminal 8 is accurately positioned by the positioning guide 7, since the IGBT chip 1 is positioned via the insulating film 3, the insulating film 3 is bonded to the IGBT chip 1 at a relative position with respect to the emitter terminal 8. It must be done after accurate alignment taking into consideration.

3A and 3B are explanatory views showing a process of adhering an insulating film to an IGBT chip. FIG. 3A shows a chip alignment state, and FIG. 3B shows a thermocompression bonding operation state.
(C) shows a state after adhesion of the insulating film. I
In the GBT chip 1, when polyimide is used for the passivation film for ensuring stable withstand voltage, a polyimide resin is used as the insulating film 3. When the insulating film 3 is made of polyimide, a thermocompression bonding method can be used for adhesion to the IGBT chip 1. The insulating film 3 avoids bending of the film itself when the IGBT chip 1 is inserted into the positioning guide 7,
A thickness of at least 30 microns is required.

A positioning base 10 is used to define the relative position of the IGBT chip 1 and the insulating film 3. The upper surface of this base 10 has an IGB in the center thereof.
A recess for fitting the T-chip 1 is formed, and a ring-shaped regulating member for fitting the insulating film 3 is provided on the outer periphery. The recess and the ring-shaped regulating member serve as the emitter terminal 8
And the IGBT chip 1 are positioned relative to each other.

First, as shown in (A), the IGBT chip 1 is fitted in the recess in the center of the base 10, and the insulating film 3 is inserted into the ring-shaped regulating member from above. Next, as shown in (B), the heating device 11 whose bottom surface has a ring-shaped end face shape in conformity with the shape of the insulating film 3.
And the insulating film 3 is pressed. This allows
The insulating film 3 is adhered to the polyimide passivation film of the IGBT chip 1 to obtain the IGBT chip 1 to which the insulating film 3 is adhered, as shown in (C). As a result, the insulation film 3 is ± 50
It can be bonded to the IGBT chip 1 with a positioning accuracy of the order of microns.

FIG. 4 is a diagram showing discharge breakdown voltage characteristics of the IGBT chip. In FIG. 4, the horizontal axis represents the atmospheric pressure of the measurement atmosphere of the IGBT chip, and the vertical axis represents the breakdown voltage of the IGBT chip, which is the lowest voltage at which the air discharge is started. As a sample, an IG with an avalanche breakdown voltage of about 3000 volts
A BT chip was used.

For reference, a curve 20 shows the withstand voltage change characteristic of the IGBT chip without an insulating film and with no metal powder on the passivation film. From this characteristic, it is understood that the discharge generated between the vicinity of the passivation film on the emitter side of the IGBT chip and the chip end surface on the collector side linearly decreases as the atmospheric pressure decreases. From this result, it can be seen that the inside of the power pack is normally maintained at a pressure of 1.01 × 10 ⁵ Pa or higher by nitrogen, so that if discharge does not occur in an atmosphere lower than 1.01 × 10 ⁵ Pa, high discharge resistance It can be said that it has sex.

A curve 21 shows the withstand voltage change characteristic of the IGBT chip when there is no insulating film and a metal powder having a size of 500 μm is placed on the passivation film. From this characteristic, it can be seen that the discharge withstand voltage near 1.01 × 10 ⁵ Pa, which is close to that in actual use, is greatly reduced.

A curve 22 shows an insulating film, and shows a withstand voltage change characteristic of the IGBT chip in a state where metal powder having a size of 500 μm is placed on the insulating film. From this characteristic, even if the insulating film is adhered,
Atmospheric pressure is 0.202 × 10 ⁵ Pa even with metal powder
It can be seen that even if the temperature is lowered to 0, discharge does not occur, and good discharge resistance is exhibited.

[0021]

As described above, according to the present invention, in a MOS type multi-chip semiconductor device hermetically sealed in a ceramic package, an insulating resin whose chip edge portion has an outer dimension larger than at least the chip outer dimension. The film is adhered. As a result, the edge distance between the chip end surface and the main electrode is extended, and the electric field strength between them is relaxed, so that the discharge withstand capability can be increased, and even if a fine metal powder or the like is mixed in, it is not possible. Even if there is an environmental factor, the withstand voltage is not reduced and the reliability of the semiconductor device can be improved.

Further, since the resin film is larger than the outer dimensions of the chip, it has a function of positioning the chip when the chip is mounted using the positioning guide, and is separated from the positioning guide by a predetermined distance. Does not come into contact with the positioning guide or receive stress,
The stable state of the chip can be maintained.

[Brief description of drawings]

1A and 1B are diagrams showing a configuration of an IGBT chip to which the present invention is applied, in which FIG. 1A is a plan view of the chip and FIG. 1B is a side view of the chip taken along the arrow aa.

FIG. 2 is a cross-sectional view of a power pack showing an example of mounting an IGBT chip.

3A and 3B are explanatory views showing a step of adhering an insulating film to an IGBT chip, wherein FIG. 3A shows a chip alignment state, FIG. 3B shows a thermocompression bonding operation state, and FIG. 4 shows the state after the bonding.

FIG. 4 is a diagram showing discharge breakdown voltage characteristics of an IGBT chip.

[Explanation of symbols]

1 IGBT chip 2 Guard ring part 3 insulating film 4 chip end face 5 Molybdenum (Mo) substrate 6 groove 7 Positioning guide 8 Emitter terminal 10 bases 11 Heating device

Claims (3)

(57) [Claims] 1. A semiconductor device in which a MOS control type semiconductor chip having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface is incorporated in a flat package having an airtight structure. 2. A semiconductor device, wherein an insulating resin film having an outer dimension larger than at least a chip outer dimension is bonded to a chip edge portion of the first main surface. 2. The first member to which the resin film is adhered
The semiconductor device according to claim 1, wherein a polyimide film is applied to a region of the main surface of the semiconductor device. 3. The semiconductor device according to claim 2, wherein the resin film is a polyimide resin, and the polyimide film is adhered to the polyimide film by thermocompression bonding.