JPH11251339A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate edge surface discharge in the inside at all relating to a semiconductor device for which an MOS type device like IGBT is mounted to the flat type package of an airtight structure. SOLUTION: A guard ring part 2 is formed at the outer periphery of the surface where an emitter electrode is arranged of an IGBT chip 1 and a frame- like insulation film 3 is adhered so as to cover the guard ring part 2. The external dimension of the insulation film 3 is formed larger than the external dimension of the IGBT chip 1, and the outer peripheral end part is surely projected from a chip end face 4 to an outer side and adhered to the IGBT chip 1. Thus, an edge surface distance between the chip end face 4 and the emitter electrode is extended, the influence of electric field strength is mitigated and discharge withstanding current rating is raised. Even when fine metallic powder is mounted on the insulation film 3, since the electric field strength is not changed by it, the edge surface discharge does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
Especially insulated gate bipolar transistor (IGBT)
A semiconductor chip having a first main electrode (emitter electrode) and a control electrode (gate electrode) on one main surface of a substrate and a second main electrode (collector electrode) on another main surface for power devices such as The present invention relates to a semiconductor device incorporated in a flat ceramic package having a structure that is completely airtight with outside air.

[0002]

2. Description of the Related Art An IGBT is an element having characteristics of both a MOS (Metal Oxide Semiconductor) type FET (Field Effect Transistor) and a bipolar transistor, and is widely used as a power switching device for applications such as an inverter for controlling a motor. Have been done. Furthermore, recently, it is easy to use a voltage-driven type and has a wide safe operation area and is hard to be broken.
BT applications are expanding.

In a MOS control device such as an IGBT, a chip manufacturing process is required to have an accuracy of several microns to sub-micron unlike a GTO thyristor or the like. 10mm
It is necessary to mount a plurality of chips each having a size of about 28 mm square.

Further, MOS such as IGBT is used.
In the control device, an emitter electrode and a gate electrode are formed side by side on one main surface of a semiconductor chip. For this reason, in a general module structure, when an IGBT chip is incorporated in a package container, a collector formed on the lower side mounts the IGBT on a metal base also serving as a heat radiator and pulls out the IGBT to the outside, and emits an emitter electrode and a gate electrode. Separately from the external lead-out terminal, and thereby mounted inside the package. Thereafter, a plastic package is provided outside, and a silicone-based resin such as a gel is sealed therein to prevent discharge.

[0005] However, a flat IGBT in which the IGBT is incorporated in a flat ceramic package such as a GTO thyristor uses a ceramic package, in which nitrogen is sealed to completely maintain airtightness. Therefore, the flat type IGBT does not have a structure in which a gel or the like can be injected, so that another discharge countermeasure is required. For this reason, conventionally, the chip surface from the main electrode on the emitter side to the edge surface has been passivated in order to prevent the edge surface discharge of the chip. This forms a passivation film by applying polyimide about 10 microns,
The field strength applied to the edge of the chip is reduced.

[0006]

IGBT chips can be obtained by cutting and separating a single wafer on which a plurality of chips are formed by dicing.
At this time or at the time of subsequent processing, fine shavings or fine metal powder may adhere to the chip. In the structure of the chip end face of the flat type IGBT, the gap between the chip edge and the main electrode is protected by a polyimide film. May ride. When a metal powder or the like rides on the polyimide film, the electric field strength in that portion increases, and the discharge withstand capability of the actual device is reduced, so that there is a problem that a discharge is generated or the chip is broken by the discharge.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been made in view of the fact that a plurality of MOS-type devices such as IGBTs are mounted on a flat package, and the internal surface discharge is completely eliminated. It is intended to provide a device.

[0008]

According to the present invention, in order to solve the above-mentioned problems, a MOS control having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface is provided. In a semiconductor device having a semiconductor chip incorporated in a flat package having an airtight structure, an insulating resin film having an outer dimension at least larger than the outer dimension of the chip is bonded to a chip edge portion of the first main surface. Semiconductor device is provided.

According to such a semiconductor device, the relative position between the insulating resin film and the chip is determined such that the resin film always projects outward from the chip, so that the distance between the chip end surface and the main electrode can be reduced. The edge distance is extended, and the discharge withstand capability can be increased. In addition, even if conductive foreign substances such as metal powders get on the resin film, there is no sudden change in electric field strength that induces edge surface discharge, so that stable operation against any atmosphere inside the package must be ensured. And reliability can be improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking as an example a case where the present invention is applied to a flat power pack having a pressure contact structure on which a plurality of IGBT chips are mounted. .

FIG. 1 is a diagram showing a configuration of an IGBT chip to which the present invention is applied, wherein (A) is a plan view of the chip,
(B) is a side view of the chip as viewed from aa arrow. In FIG. 1, an IGBT chip 1 has an emitter electrode as a first main electrode and a gate electrode (not shown) as a control electrode arranged on an upper surface, and a collector electrode as a second main electrode on a lower surface. I have. On the upper surface of the IGBT chip 1, a guard ring portion 2 is formed along the outer periphery. A frame-shaped insulating film 3 is formed so as to cover the guard ring portion 2. The outer dimensions of this insulating film 3 are IGB
When the insulating film 3 is formed to be larger than the outer dimensions of the T chip 1 and the insulating film 3 is bonded to the IGBT chip 1, accurate positioning is performed so that the outer peripheral end of the insulating film 3 always projects outside the chip end face 4. Is performed.
As described above, by providing the insulating film 3 so that the outer periphery protrudes outside the chip end surface 4, the edge surface distance between the chip end surface 4 and the emitter electrode is extended, so that the influence of the electric field intensity is reduced. At least 500 volts of discharge withstand voltage is higher than the withstand voltage of the element itself. Therefore, the amount of the length protruding outside the insulating film 3 is determined by the required withstand voltage.

The power pack includes a plurality of IGBs.
T chip 1 is mounted, and these IGBT chips 1
At the same time, a plurality of flywheel diode chips are built in. As with the IGBT chip 1, a similar insulating film is bonded to the outer periphery of the upper surface of the flywheel diode chip having the anode electrode as its main electrode.

FIG. 2 is a sectional view of a power pack showing an example of mounting an IGBT chip. In FIG. 2, the molybdenum (Mo) substrate 5 has a groove 6 formed in a grid pattern on the upper surface thereof. A mesh-shaped positioning guide 7 made of a heat-resistant resin is fitted into the groove 6. The IGBT chips 1 to which the insulating films 3 are respectively adhered are mounted on Mo substrates 5 defined by positioning guides 7. At this time, the IGBT chip 1 holds the insulating film 3 with the collector electrode facing down and the positioning guide 7.
Is inserted into the space surrounded by the positioning guide 7 while being slid along the inner wall surface. Therefore, this IG
When mounting the BT chip 1, the insulating film 3
By protruding outward from the chip end surface 4 of the T chip 1, the chip end surface 4 does not directly contact the inner wall surface of the positioning guide 7, thereby preventing physical damage to the IGBT chip 1 due to the contact. . For this reason, the insulating film 3 requires a flexible material and a thickness to avoid its own bending. IGBT chip 1
Is positioned via the insulating film 3, so that the thermal stress on the chip end face 4 generated due to the difference in the coefficient of thermal expansion is absorbed by the insulating film 3, and even if the IGBT chip 1 vibrates, for example, the insulating film With the interposition of 3, the chip end surface 4 does not rub against the positioning guide 7, and a stable state can be maintained. Furthermore, an emitter terminal 8 made of molybdenum is arranged at a position corresponding to the emitter electrode of the IGBT chip 1. The IGBT chip 1 is electrically connected to the main electrode by pressure contact from above and below by the emitter terminal 8 and the Mo substrate 5. The gate electrode of the IGBT chip 1 is wire-bonded to a wiring pattern on a ceramic substrate provided around the positioning guide 7 so that the emitter terminal 8 guided to the outside has a brim-like projection at an intermediate height. And is accurately positioned in the positioning guide 7 therethrough. Since the emitter terminal 8 presses the fine pattern of the IGBT chip 1 from above, the emitter terminal 8 is pressed.
And the IGBT chip 1 must be accurately aligned. Although the emitter terminal 8 is accurately positioned by the positioning guide 7, the positioning of the IGBT chip 1 is performed via the insulating film 3. Therefore, the bonding of the insulating film 3 to the IGBT chip 1 requires the relative position with respect to the emitter terminal 8. It must be done after accurate alignment taking into account.

FIG. 3 is an explanatory view showing a step of bonding an insulating film to an IGBT chip, wherein (A) shows a state of chip alignment, (B) shows a thermocompression operation state,
(C) shows the state after bonding of the insulating film. I
In the case where the GBT chip 1 uses polyimide as a passivation film for ensuring stable withstand voltage, a polyimide resin is used as the insulating film 3. When the insulating film 3 is made of polyimide, a thermocompression bonding method can be used for bonding to the IGBT chip 1. The insulating film 3 avoids bending of the film itself when the IGBT chip 1 is inserted into the positioning guide 7,
A thickness of at least 30 microns is required.

In order to define the relative position between the IGBT chip 1 and the insulating film 3, a positioning base 10 is used. On the upper surface of the base 10, an IGB
A concave portion into which the T chip 1 is fitted is formed, and a ring-shaped regulating member into which the insulating film 3 is fitted is provided on the outer periphery. The recess and the ring-shaped regulating member are connected to the emitter terminal 8.
And the IGBT chip 1.

First, as shown in FIG. 1A, the IGBT chip 1 is fitted into a recess at the center of the base 10, and the insulating film 3 is inserted into the ring-shaped regulating member from above. Next, as shown in (B), the heating device 11 whose lower surface has a ring-shaped end surface shape according to the shape of the insulating film 3.
And pressurize the insulating film 3. This allows
The insulating film 3 is bonded to the passivation film using polyimide of the IGBT chip 1, and as shown in (C), the IGBT chip 1 to which the insulating film 3 is bonded can be obtained. Thereby, the insulating film 3 is ± 50
It can be bonded to the IGBT chip 1 with a positioning accuracy on the order of microns.

FIG. 4 is a diagram showing the discharge withstand voltage characteristics of the IGBT chip. In FIG. 4, the horizontal axis indicates the atmospheric pressure of the measurement atmosphere of the IGBT chip, and the vertical axis indicates the withstand voltage of the IGBT chip which is the lowest voltage at which air discharge starts. As a sample, an IG having an avalanche withstand voltage of about 3000 volts was used.
BT chips were used.

Here, a curve 20 shows a withstand voltage change characteristic of the IGBT chip in a state where there is no insulating film and no metal powder is put on the passivation film for reference. From this characteristic, it can be seen that the discharge generated between the vicinity of the passivation film on the emitter side of the IGBT chip and the end face of the chip on the collector side decreases linearly as the atmospheric pressure decreases. From this result, since the inside of the power pack is normally maintained at a pressure of 1.01 × 10 ⁵ Pa or more by nitrogen, if discharge does not occur in an atmosphere lower than 1.01 × 10 ⁵ Pa, a high discharge resistance is obtained. It can be said that it has the property.

A curve 21 shows the withstand voltage change characteristic of the IGBT chip in a state where there is no insulating film and a metal powder having a size of 500 μm is placed on the passivation film. From this characteristic, it can be seen that the discharge breakdown voltage near 1.01 × 10 ⁵ Pa, which is close to the actual use, is greatly reduced.

A curve 22 shows the withstand voltage change characteristics of the IGBT chip in a state where there is an insulating film, and a metal powder having a size of 500 μm is placed on the insulating film. From this characteristic, by bonding the insulating film,
Atmospheric pressure of 0.202 × 10 ⁵ Pa even with metal powder on
It can be seen that no discharge was generated even when the temperature decreased to a low level, indicating that excellent discharge resistance was exhibited.

[0021]

As described above, according to the present invention, in a MOS type multi-chip semiconductor device hermetically sealed in a ceramic package, an insulating resin whose outer dimensions are at least larger than the outer dimensions of the chip is provided at the chip edge. The film was bonded. As a result, the edge distance between the chip end face and the main electrode is extended, and the electric field strength therebetween is reduced, so that the discharge withstand capability can be increased. Even if there is an environmental factor, the withstand voltage does not decrease, and the reliability of the semiconductor device can be improved.

Since the resin film is larger than the outer dimensions of the chip, the resin film has a chip positioning function when mounting the chip using the positioning guide, and is separated from the positioning guide by a predetermined distance. Is no longer in contact with or stressed by the positioning guide,
The stable state of the chip can be maintained.

[Brief description of the drawings]

1A and 1B are diagrams showing a configuration of an IGBT chip to which the present invention is applied, wherein FIG. 1A is a plan view of the chip, and FIG. 1B is a side view of the chip as viewed from aa arrow.

FIG. 2 is a cross-sectional view of a power pack showing an example of mounting an IGBT chip.

3A and 3B are explanatory diagrams showing a process of bonding an insulating film to an IGBT chip, wherein FIG. 3A shows a chip alignment state, FIG. 3B shows a thermocompression bonding operation state, and FIG. Shows a state after bonding.

FIG. 4 is a diagram showing a discharge breakdown voltage characteristic of an IGBT chip.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 IGBT chip 2 Guard ring part 3 Insulating film 4 Chip end face 5 Molybdenum (Mo) substrate 6 Groove part 7 Positioning guide 8 Emitter terminal 10 Base 11 Heating device

Claims (3)

[Claims] A semiconductor device in which a MOS control type semiconductor chip having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface is incorporated in a flat package having an airtight structure. 3. The semiconductor device according to claim 1, wherein an insulating resin film whose outer dimension is at least larger than the outer dimension of the chip is bonded to the chip edge portion of the first main surface. 2. A method according to claim 1, wherein said first resin film is bonded to said first film.
2. The semiconductor device according to claim 1, wherein a polyimide film is applied to a region of the main surface of the semiconductor device. 3. The semiconductor device according to claim 2, wherein said resin film is made of a polyimide resin, and is bonded to said polyimide film by thermocompression bonding.